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------------------------------------------------------------------------------- -- Moving average filter -- -- n=0 "00" no averaging -- n=1 "01" 2 samples -- n=2 "10" 4 samples -- n=3 "11" undefined -- -- TODO: adapt to incoming signal length -- TODO: carry correct overflow bits to result -- -- Author: Peter Würtz, TU Kaiserslautern (2016) -- Distributed under the terms of the GNU General Public License Version 3. -- The full license is in the file COPYING.txt, distributed with this software. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.sampling_pkg.all; entity sample_average is port ( clk: in std_logic; n: in std_logic_vector(1 downto 0); samples_a_in: in adc_samples_t(0 to 1); samples_a_out: out adc_samples_t(0 to 1) ); end sample_average; architecture sample_average_arch of sample_average is type samples_t is array (integer range <>) of signed(ADC_SAMPLE_BITS-1 downto 0); signal s0_samples: samples_t(0 to 4); signal s1_samples: samples_t(0 to 3); signal s2_samples: samples_t(0 to 1); begin stage0: process(clk) begin if rising_edge(clk) then -- shift buffer s0_samples(0 to 2) <= s0_samples(2 to 4); -- add new samples s0_samples(3) <= signed(samples_a_in(0).data); s0_samples(4) <= signed(samples_a_in(1).data); end if; end process; stage1: process(clk) variable a2, a3: signed(ADC_SAMPLE_BITS downto 0); begin if rising_edge(clk) then -- shift buffer s1_samples(0 to 1) <= s1_samples(2 to 3); -- calculate new averages a2 := resize(s0_samples(2), ADC_SAMPLE_BITS+1) + resize(s0_samples(3), ADC_SAMPLE_BITS+1); a3 := resize(s0_samples(3), ADC_SAMPLE_BITS+1) + resize(s0_samples(4), ADC_SAMPLE_BITS+1); s1_samples(2) <= a2(ADC_SAMPLE_BITS downto 1); s1_samples(3) <= a3(ADC_SAMPLE_BITS downto 1); end if; end process; stage2: process(clk) variable a0, a1: signed(ADC_SAMPLE_BITS downto 0); begin if rising_edge(clk) then -- calculate new averages a0 := resize(s1_samples(0), ADC_SAMPLE_BITS+1) + resize(s1_samples(2), ADC_SAMPLE_BITS+1); a1 := resize(s1_samples(1), ADC_SAMPLE_BITS+1) + resize(s1_samples(3), ADC_SAMPLE_BITS+1); s2_samples(0) <= a0(ADC_SAMPLE_BITS downto 1); s2_samples(1) <= a1(ADC_SAMPLE_BITS downto 1); end if; end process; output_selection: process(n, samples_a_in, s1_samples, s2_samples) begin samples_a_out(0).ovfl <= samples_a_in(0).ovfl; samples_a_out(1).ovfl <= samples_a_in(1).ovfl; case n is when "00" => samples_a_out(0).data <= samples_a_in(0).data; samples_a_out(1).data <= samples_a_in(1).data; when "01" => samples_a_out(0).data <= signed(s1_samples(2)); samples_a_out(1).data <= signed(s1_samples(3)); when "10" => samples_a_out(0).data <= signed(s2_samples(0)); samples_a_out(1).data <= signed(s2_samples(1)); when others => samples_a_out(0).data <= (others => '-'); samples_a_out(1).data <= (others => '-'); end case; end process; end sample_average_arch;
--================================================================================================================================ -- Copyright 2020 Bitvis -- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. -- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT. -- -- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on -- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and limitations under the License. --================================================================================================================================ -- Note : Any functionality not explicitly described in the documentation is subject to change at any time ---------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------ -- Description : See library quick reference (under 'doc') and README-file(s) ------------------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library uvvm_util; context uvvm_util.uvvm_util_context; library uvvm_vvc_framework; use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all; library bitvis_vip_scoreboard; use bitvis_vip_scoreboard.generic_sb_support_pkg.all; library work; use work.axi_sb_pkg.all; use work.axi_bfm_pkg.all; use work.vvc_cmd_pkg.all; use work.td_target_support_pkg.all; use work.transaction_pkg.all; --================================================================================================= --================================================================================================= --================================================================================================= package vvc_methods_pkg is --=============================================================================================== -- Types and constants for the AXI VVC --=============================================================================================== constant C_VVC_NAME : string := "AXI_VVC"; signal AXI_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME); alias THIS_VVCT : t_vvc_target_record is AXI_VVCT; alias t_bfm_config is t_axi_bfm_config; type t_executor_result is record cmd_idx : natural; -- from UVVM handshake mechanism data : std_logic_vector(127 downto 0); value_is_new : boolean; -- turn true/false for put/fetch fetch_is_accepted : boolean; end record; type t_executor_result_array is array (natural range <>) of t_executor_result; -- Type found in UVVM-Util types_pkg constant C_AXI_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := ( delay_type => NO_DELAY, delay_in_time => 0 ns, inter_bfm_delay_violation_severity => WARNING ); type t_vvc_config is record inter_bfm_delay : t_inter_bfm_delay; -- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay. cmd_queue_count_max : natural; -- Maximum pending number in command queue before queue is full. Adding additional commands will result in an ERROR. cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if command queue is almost full. Will be ignored if set to 0. cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full. result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count. Used for early warning if result queue is almost full. Will be ignored if set to 0. result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold bfm_config : t_axi_bfm_config; -- Configuration for AXI4 BFM. See quick reference for AXI4 BFM msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel parent_msg_id_panel : t_msg_id_panel; -- UVVM: temporary fix for HVVC, remove in v3.0 force_single_pending_transaction : boolean; -- Waits until the previous transaction is completed before starting the next one end record; type t_vvc_config_array is array (natural range <>) of t_vvc_config; constant C_AXI_VVC_CONFIG_DEFAULT : t_vvc_config := ( inter_bfm_delay => C_AXI_INTER_BFM_DELAY_DEFAULT, cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD, cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY, result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX, result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY, result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD, bfm_config => C_AXI_BFM_CONFIG_DEFAULT, msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT, parent_msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT, force_single_pending_transaction => false ); type t_vvc_status is record current_cmd_idx : natural; previous_cmd_idx : natural; pending_cmd_cnt : natural; end record; type t_vvc_status_array is array (natural range <>) of t_vvc_status; constant C_VVC_STATUS_DEFAULT : t_vvc_status := ( current_cmd_idx => 0, previous_cmd_idx => 0, pending_cmd_cnt => 0 ); -- Transaction information for the wave view during simulation type t_transaction_info is record operation : t_operation; addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0); data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0); byte_enable : std_logic_vector(C_VVC_CMD_BYTE_ENABLE_MAX_LENGTH-1 downto 0); msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH); end record; shared variable shared_axi_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_AXI_VVC_CONFIG_DEFAULT); shared variable shared_axi_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT); -- Scoreboard shared variable AXI_VVC_SB : t_generic_sb; --========================================================================================== -- Methods dedicated to this VVC -- - These procedures are called from the testbench in order for the VVC to execute -- BFM calls towards the given interface. The VVC interpreter will queue these calls -- and then the VVC executor will fetch the commands from the queue and handle the -- actual BFM execution. -- For details on how the BFM procedures work, see the QuickRef. --========================================================================================== procedure axi_write( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant awid : in std_logic_vector := ""; constant awaddr : in unsigned; constant awlen : in unsigned(7 downto 0) := (others=>'0'); constant awsize : in integer range 1 to 128 := 4; constant awburst : in t_axburst := INCR; constant awlock : in t_axlock := NORMAL; constant awcache : in std_logic_vector(3 downto 0) := (others=>'0'); constant awprot : in t_axprot := UNPRIVILEGED_NONSECURE_DATA; constant awqos : in std_logic_vector(3 downto 0) := (others=>'0'); constant awregion : in std_logic_vector(3 downto 0) := (others=>'0'); constant awuser : in std_logic_vector := ""; constant wdata : in t_slv_array; constant wstrb : in t_slv_array := C_EMPTY_SLV_ARRAY; constant wuser : in t_slv_array := C_EMPTY_SLV_ARRAY; constant bresp_exp : in t_xresp := OKAY; constant buser_exp : in std_logic_vector := ""; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure axi_read( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant arid : in std_logic_vector := ""; constant araddr : in unsigned; constant arlen : in unsigned(7 downto 0) := (others=>'0'); constant arsize : in integer range 1 to 128 := 4; constant arburst : in t_axburst := INCR; constant arlock : in t_axlock := NORMAL; constant arcache : in std_logic_vector(3 downto 0) := (others=>'0'); constant arprot : in t_axprot := UNPRIVILEGED_NONSECURE_DATA; constant arqos : in std_logic_vector(3 downto 0) := (others=>'0'); constant arregion : in std_logic_vector(3 downto 0) := (others=>'0'); constant aruser : in std_logic_vector := ""; constant data_routing : in t_data_routing; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); procedure axi_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant arid : in std_logic_vector := ""; constant araddr : in unsigned; constant arlen : in unsigned(7 downto 0) := (others=>'0'); constant arsize : in integer range 1 to 128 := 4; constant arburst : in t_axburst := INCR; constant arlock : in t_axlock := NORMAL; constant arcache : in std_logic_vector(3 downto 0) := (others=>'0'); constant arprot : in t_axprot := UNPRIVILEGED_NONSECURE_DATA; constant arqos : in std_logic_vector(3 downto 0) := (others=>'0'); constant arregion : in std_logic_vector(3 downto 0) := (others=>'0'); constant aruser : in std_logic_vector := ""; constant rdata_exp : in t_slv_array; constant rresp_exp : in t_xresp_array := C_EMPTY_XRESP_ARRAY; constant ruser_exp : in t_slv_array := C_EMPTY_SLV_ARRAY; constant msg : in string; constant alert_level : in t_alert_level := ERROR; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ); --============================================================================== -- Transaction info methods --============================================================================== procedure set_global_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_arw_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_w_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_b_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure set_r_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ); procedure reset_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record ); procedure reset_arw_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record ); procedure reset_w_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ); procedure reset_b_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ); procedure reset_r_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ); --============================================================================== -- VVC Activity --============================================================================== procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic; variable vvc_status : inout t_vvc_status; constant activity : in t_activity; constant entry_num_in_vvc_activity_register : in integer; constant last_cmd_idx_executed : in natural; constant command_queue_is_empty : in boolean; constant scope : in string := C_VVC_NAME); end package vvc_methods_pkg; package body vvc_methods_pkg is --============================================================================== -- Methods dedicated to this VVC -- Notes: -- - shared_vvc_cmd is initialised to C_VVC_CMD_DEFAULT, and also reset to this after every command --============================================================================== procedure axi_write( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant awid : in std_logic_vector := ""; constant awaddr : in unsigned; constant awlen : in unsigned(7 downto 0) := (others=>'0'); constant awsize : in integer range 1 to 128 := 4; constant awburst : in t_axburst := INCR; constant awlock : in t_axlock := NORMAL; constant awcache : in std_logic_vector(3 downto 0) := (others=>'0'); constant awprot : in t_axprot := UNPRIVILEGED_NONSECURE_DATA; constant awqos : in std_logic_vector(3 downto 0) := (others=>'0'); constant awregion : in std_logic_vector(3 downto 0) := (others=>'0'); constant awuser : in std_logic_vector := ""; constant wdata : in t_slv_array; constant wstrb : in t_slv_array := C_EMPTY_SLV_ARRAY; constant wuser : in t_slv_array := C_EMPTY_SLV_ARRAY; constant bresp_exp : in t_xresp := OKAY; constant buser_exp : in std_logic_vector := ""; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(awaddr, HEX, AS_IS, INCL_RADIX) & ")"; variable v_normalised_awid : std_logic_vector(shared_vvc_cmd.id'length-1 downto 0); variable v_normalised_awaddr : unsigned(shared_vvc_cmd.addr'length-1 downto 0); variable v_normalised_awuser : std_logic_vector(shared_vvc_cmd.auser'length-1 downto 0); variable v_normalised_wdata : t_slv_array(0 to shared_vvc_cmd.data_array'length-1)(shared_vvc_cmd.data_array(0)'length-1 downto 0); variable v_normalised_wstrb : t_slv_array(0 to shared_vvc_cmd.strb_array'length-1)(shared_vvc_cmd.strb_array(0)'length-1 downto 0); variable v_normalised_wuser : t_slv_array(0 to shared_vvc_cmd.user_array'length-1)(shared_vvc_cmd.user_array(0)'length-1 downto 0); variable v_normalised_buser_exp : std_logic_vector(shared_vvc_cmd.user'length-1 downto 0); variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Normalizing inputs to the command record if awid'length = 0 then v_normalised_awid := C_VVC_CMD_DEFAULT.id; else v_normalised_awid := normalize_and_check(awid, shared_vvc_cmd.id, ALLOW_WIDER_NARROWER, "awid", "shared_vvc_cmd.id", "Normalizing awid. " & add_msg_delimiter(msg)); end if; v_normalised_awaddr := normalize_and_check(awaddr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "awaddr", "shared_vvc_cmd.addr", "Normalizing awaddr. " & add_msg_delimiter(msg)); if awuser'length = 0 then v_normalised_awuser := C_VVC_CMD_DEFAULT.auser; else v_normalised_awuser := normalize_and_check(awuser, shared_vvc_cmd.auser, ALLOW_WIDER_NARROWER, "awuser", "shared_vvc_cmd.auser", "Normalizing awuser. " & add_msg_delimiter(msg)); end if; v_normalised_wdata := normalize_and_check(wdata, shared_vvc_cmd.data_array, ALLOW_WIDER_NARROWER, "wdata", "shared_vvc_cmd.data_array", "Normalizing wdata. " & add_msg_delimiter(msg)); if wstrb'length = 1 and wstrb(0)'length = 1 and wstrb(0) = "U" then v_normalised_wstrb := C_VVC_CMD_DEFAULT.strb_array; else v_normalised_wstrb := normalize_and_check(wstrb, shared_vvc_cmd.strb_array, ALLOW_WIDER_NARROWER, "wstrb", "shared_vvc_cmd.strb_array", "Normalizing wstrb. " & add_msg_delimiter(msg)); end if; if wuser'length = 1 and wuser(0)'length = 1 and wuser(0) = "U" then v_normalised_wuser := C_VVC_CMD_DEFAULT.user_array; else v_normalised_wuser := normalize_and_check(wuser, shared_vvc_cmd.user_array, ALLOW_WIDER_NARROWER, "wuser", "shared_vvc_cmd.user_array", "Normalizing wuser. " & add_msg_delimiter(msg)); end if; if buser_exp'length = 0 then v_normalised_buser_exp := C_VVC_CMD_DEFAULT.user; else v_normalised_buser_exp := normalize_and_check(buser_exp, shared_vvc_cmd.user, ALLOW_WIDER_NARROWER, "buser_exp", "shared_vvc_cmd.user", "Normalizing buser. " & add_msg_delimiter(msg)); end if; -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, WRITE); shared_vvc_cmd.id := v_normalised_awid; shared_vvc_cmd.addr := v_normalised_awaddr; shared_vvc_cmd.len := awlen; shared_vvc_cmd.size := awsize; shared_vvc_cmd.burst := awburst; shared_vvc_cmd.lock := awlock; shared_vvc_cmd.cache := awcache; shared_vvc_cmd.prot := awprot; shared_vvc_cmd.qos := awqos; shared_vvc_cmd.region := awregion; shared_vvc_cmd.resp := bresp_exp; shared_vvc_cmd.auser := v_normalised_awuser; shared_vvc_cmd.user := v_normalised_buser_exp; shared_vvc_cmd.data_array := v_normalised_wdata; shared_vvc_cmd.strb_array := v_normalised_wstrb; shared_vvc_cmd.user_array := v_normalised_wuser; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure axi_read( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant arid : in std_logic_vector := ""; constant araddr : in unsigned; constant arlen : in unsigned(7 downto 0) := (others=>'0'); constant arsize : in integer range 1 to 128 := 4; constant arburst : in t_axburst := INCR; constant arlock : in t_axlock := NORMAL; constant arcache : in std_logic_vector(3 downto 0) := (others=>'0'); constant arprot : in t_axprot := UNPRIVILEGED_NONSECURE_DATA; constant arqos : in std_logic_vector(3 downto 0) := (others=>'0'); constant arregion : in std_logic_vector(3 downto 0) := (others=>'0'); constant aruser : in std_logic_vector := ""; constant data_routing : in t_data_routing; constant msg : in string; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(araddr, HEX, AS_IS, INCL_RADIX) & ")"; variable v_normalised_arid : std_logic_vector(shared_vvc_cmd.id'length-1 downto 0); variable v_normalised_araddr : unsigned(shared_vvc_cmd.addr'length-1 downto 0); variable v_normalised_aruser : std_logic_vector(shared_vvc_cmd.user'length-1 downto 0); variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Normalizing inputs to the command record if arid'length = 0 then v_normalised_arid := C_VVC_CMD_DEFAULT.id; else v_normalised_arid := normalize_and_check(arid, shared_vvc_cmd.id, ALLOW_WIDER_NARROWER, "arid", "shared_vvc_cmd.id", "Normalizing arid. " & add_msg_delimiter(msg)); end if; v_normalised_araddr := normalize_and_check(araddr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "araddr", "shared_vvc_cmd.addr", msg); if aruser'length = 0 then v_normalised_aruser := C_VVC_CMD_DEFAULT.auser; else v_normalised_aruser := normalize_and_check(aruser, shared_vvc_cmd.user, ALLOW_WIDER_NARROWER, "aruser", "shared_vvc_cmd.auser", "Normalizing aruser. " & add_msg_delimiter(msg)); end if; -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, READ); shared_vvc_cmd.id := v_normalised_arid; shared_vvc_cmd.addr := v_normalised_araddr; shared_vvc_cmd.len := arlen; shared_vvc_cmd.size := arsize; shared_vvc_cmd.burst := arburst; shared_vvc_cmd.lock := arlock; shared_vvc_cmd.cache := arcache; shared_vvc_cmd.prot := arprot; shared_vvc_cmd.qos := arqos; shared_vvc_cmd.region := arregion; shared_vvc_cmd.auser := v_normalised_aruser; shared_vvc_cmd.data_routing := data_routing; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; procedure axi_check( signal VVCT : inout t_vvc_target_record; constant vvc_instance_idx : in integer; constant arid : in std_logic_vector := ""; constant araddr : in unsigned; constant arlen : in unsigned(7 downto 0) := (others=>'0'); constant arsize : in integer range 1 to 128 := 4; constant arburst : in t_axburst := INCR; constant arlock : in t_axlock := NORMAL; constant arcache : in std_logic_vector(3 downto 0) := (others=>'0'); constant arprot : in t_axprot := UNPRIVILEGED_NONSECURE_DATA; constant arqos : in std_logic_vector(3 downto 0) := (others=>'0'); constant arregion : in std_logic_vector(3 downto 0) := (others=>'0'); constant aruser : in std_logic_vector := ""; constant rdata_exp : in t_slv_array; constant rresp_exp : in t_xresp_array := C_EMPTY_XRESP_ARRAY; constant ruser_exp : in t_slv_array := C_EMPTY_SLV_ARRAY; constant msg : in string; constant alert_level : in t_alert_level := ERROR; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT; constant parent_msg_id_panel : in t_msg_id_panel := C_UNUSED_MSG_ID_PANEL -- Only intended for usage by parent HVVCs ) is constant proc_name : string := get_procedure_name_from_instance_name(vvc_instance_idx'instance_name); constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all & ", " & to_string(araddr, HEX, AS_IS, INCL_RADIX) & ")"; variable v_normalised_arid : std_logic_vector(shared_vvc_cmd.id'length-1 downto 0); variable v_normalised_araddr : unsigned(shared_vvc_cmd.addr'length-1 downto 0); variable v_normalised_aruser : std_logic_vector(shared_vvc_cmd.auser'length-1 downto 0); variable v_normalised_rdata : t_slv_array(0 to shared_vvc_cmd.data_array'length-1)(shared_vvc_cmd.data_array(0)'length-1 downto 0); variable v_normalised_rresp : t_xresp_array(0 to shared_vvc_cmd.data_array'length-1) := (others=>ILLEGAL); variable v_normalised_ruser : t_slv_array(0 to shared_vvc_cmd.user_array'length-1)(shared_vvc_cmd.user_array(0)'length-1 downto 0); variable v_msg_id_panel : t_msg_id_panel := shared_msg_id_panel; begin -- Normalizing inputs to the command record if arid'length = 0 then v_normalised_arid := C_VVC_CMD_DEFAULT.id; else v_normalised_arid := normalize_and_check(arid, shared_vvc_cmd.id, ALLOW_WIDER_NARROWER, "arid", "shared_vvc_cmd.id", "Normalizing arid. " & add_msg_delimiter(msg)); end if; v_normalised_araddr := normalize_and_check(araddr, shared_vvc_cmd.addr, ALLOW_WIDER_NARROWER, "araddr", "shared_vvc_cmd.addr", msg); if aruser'length = 0 then v_normalised_aruser := C_VVC_CMD_DEFAULT.auser; else v_normalised_aruser := normalize_and_check(aruser, shared_vvc_cmd.user, ALLOW_WIDER_NARROWER, "aruser", "shared_vvc_cmd.user", "Normalizing aruser. " & add_msg_delimiter(msg)); end if; v_normalised_rdata := normalize_and_check(rdata_exp, shared_vvc_cmd.data_array, ALLOW_WIDER_NARROWER, "rdata_exp", "shared_vvc_cmd.data_array", "Normalizing rdata. " & add_msg_delimiter(msg)); if rresp_exp'length = 1 and rresp_exp(0) = ILLEGAL then v_normalised_rresp := C_VVC_CMD_DEFAULT.resp_array; else if not rresp_exp'ascending then tb_error("The array rresp_exp is instantiated as 'downto', but only 'to' is supported" & add_msg_delimiter(msg), scope); else for i in 0 to minimum(rresp_exp'length, shared_vvc_cmd.resp_array'length) - 1 loop v_normalised_rresp(i) := rresp_exp(i); end loop; end if; end if; if ruser_exp'length = 1 and ruser_exp(0)'length = 1 and ruser_exp(0) = "U" then v_normalised_ruser := C_VVC_CMD_DEFAULT.user_array; else v_normalised_ruser := normalize_and_check(ruser_exp, shared_vvc_cmd.user_array, ALLOW_WIDER_NARROWER, "ruser_exp", "shared_vvc_cmd.user_array", "Normalizing ruser. " & add_msg_delimiter(msg)); end if; -- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record -- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd -- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, CHECK); shared_vvc_cmd.id := v_normalised_arid; shared_vvc_cmd.addr := v_normalised_araddr; shared_vvc_cmd.len := arlen; shared_vvc_cmd.size := arsize; shared_vvc_cmd.burst := arburst; shared_vvc_cmd.lock := arlock; shared_vvc_cmd.cache := arcache; shared_vvc_cmd.prot := arprot; shared_vvc_cmd.qos := arqos; shared_vvc_cmd.region := arregion; shared_vvc_cmd.auser := v_normalised_aruser; shared_vvc_cmd.data_array := v_normalised_rdata; shared_vvc_cmd.resp_array := v_normalised_rresp; shared_vvc_cmd.user_array := v_normalised_ruser; shared_vvc_cmd.alert_level := alert_level; shared_vvc_cmd.parent_msg_id_panel := parent_msg_id_panel; if parent_msg_id_panel /= C_UNUSED_MSG_ID_PANEL then v_msg_id_panel := parent_msg_id_panel; end if; send_command_to_vvc(VVCT, std.env.resolution_limit, scope, v_msg_id_panel); end procedure; --============================================================================== -- Transaction info methods --============================================================================== procedure set_global_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin case vvc_cmd.operation is when WRITE => vvc_transaction_info_group.bt_wr.operation := vvc_cmd.operation; vvc_transaction_info_group.bt_wr.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.bt_wr.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.bt_wr.transaction_status := IN_PROGRESS; when READ | CHECK => vvc_transaction_info_group.bt_rd.operation := vvc_cmd.operation; vvc_transaction_info_group.bt_rd.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.bt_rd.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.bt_rd.transaction_status := IN_PROGRESS; when others => alert(TB_ERROR, "VVC operation not recognized"); end case; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_global_vvc_transaction_info; procedure set_arw_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin case vvc_cmd.operation is when WRITE => vvc_transaction_info_group.st_aw.operation := vvc_cmd.operation; vvc_transaction_info_group.st_aw.arwid := vvc_cmd.aid; vvc_transaction_info_group.st_aw.arwaddr := vvc_cmd.addr; vvc_transaction_info_group.st_aw.arwlen := vvc_cmd.len; vvc_transaction_info_group.st_aw.arwsize := vvc_cmd.size; vvc_transaction_info_group.st_aw.arwburst := vvc_cmd.burst; vvc_transaction_info_group.st_aw.arwlock := vvc_cmd.lock; vvc_transaction_info_group.st_aw.arwcache := vvc_cmd.cache; vvc_transaction_info_group.st_aw.arwprot := vvc_cmd.prot; vvc_transaction_info_group.st_aw.arwqos := vvc_cmd.qos; vvc_transaction_info_group.st_aw.arwregion := vvc_cmd.region; vvc_transaction_info_group.st_aw.arwuser := vvc_cmd.auser; vvc_transaction_info_group.st_aw.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_aw.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_aw.transaction_status := IN_PROGRESS; when READ | CHECK => vvc_transaction_info_group.st_ar.operation := vvc_cmd.operation; vvc_transaction_info_group.st_ar.arwid := vvc_cmd.aid; vvc_transaction_info_group.st_ar.arwaddr := vvc_cmd.addr; vvc_transaction_info_group.st_ar.arwlen := vvc_cmd.len; vvc_transaction_info_group.st_ar.arwsize := vvc_cmd.size; vvc_transaction_info_group.st_ar.arwburst := vvc_cmd.burst; vvc_transaction_info_group.st_ar.arwlock := vvc_cmd.lock; vvc_transaction_info_group.st_ar.arwcache := vvc_cmd.cache; vvc_transaction_info_group.st_ar.arwprot := vvc_cmd.prot; vvc_transaction_info_group.st_ar.arwqos := vvc_cmd.qos; vvc_transaction_info_group.st_ar.arwregion := vvc_cmd.region; vvc_transaction_info_group.st_ar.arwuser := vvc_cmd.auser; vvc_transaction_info_group.st_ar.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_ar.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_ar.transaction_status := IN_PROGRESS; when others => alert(TB_ERROR, "VVC operation not recognized"); end case; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_arw_vvc_transaction_info; procedure set_w_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin vvc_transaction_info_group.st_w.operation := vvc_cmd.operation; vvc_transaction_info_group.st_w.wdata := vvc_cmd.data_array; vvc_transaction_info_group.st_w.wstrb := vvc_cmd.strb_array; vvc_transaction_info_group.st_w.wuser := vvc_cmd.user_array; vvc_transaction_info_group.st_w.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_w.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_w.transaction_status := IN_PROGRESS; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_w_vvc_transaction_info; procedure set_b_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin vvc_transaction_info_group.st_b.operation := vvc_cmd.operation; vvc_transaction_info_group.st_b.bid := vvc_cmd.id; vvc_transaction_info_group.st_b.bresp := vvc_cmd.resp; vvc_transaction_info_group.st_b.buser := vvc_cmd.user; vvc_transaction_info_group.st_b.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_b.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_b.transaction_status := IN_PROGRESS; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_b_vvc_transaction_info; procedure set_r_vvc_transaction_info( signal vvc_transaction_info_trigger : inout std_logic; variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record; constant vvc_config : in t_vvc_config; constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT ) is begin vvc_transaction_info_group.st_r.operation := vvc_cmd.operation; vvc_transaction_info_group.st_r.rid := vvc_cmd.id; vvc_transaction_info_group.st_r.rdata := vvc_cmd.data_array; vvc_transaction_info_group.st_r.rresp := vvc_cmd.resp_array; vvc_transaction_info_group.st_r.ruser := vvc_cmd.user_array; vvc_transaction_info_group.st_r.vvc_meta.msg(1 to vvc_cmd.msg'length) := vvc_cmd.msg; vvc_transaction_info_group.st_r.vvc_meta.cmd_idx := vvc_cmd.cmd_idx; vvc_transaction_info_group.st_r.transaction_status := IN_PROGRESS; gen_pulse(vvc_transaction_info_trigger, 0 ns, "pulsing global vvc transaction info trigger", scope, ID_NEVER); wait for 0 ns; end procedure set_r_vvc_transaction_info; procedure reset_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record ) is begin case vvc_cmd.operation is when WRITE => if vvc_cmd.cmd_idx = vvc_transaction_info_group.bt_wr.vvc_meta.cmd_idx then vvc_transaction_info_group.bt_wr := C_BASE_TRANSACTION_SET_DEFAULT; end if; when READ | CHECK => if vvc_cmd.cmd_idx = vvc_transaction_info_group.bt_rd.vvc_meta.cmd_idx then vvc_transaction_info_group.bt_rd := C_BASE_TRANSACTION_SET_DEFAULT; end if; when others => null; end case; wait for 0 ns; end procedure reset_vvc_transaction_info; procedure reset_arw_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group; constant vvc_cmd : in t_vvc_cmd_record ) is begin case vvc_cmd.operation is when WRITE => vvc_transaction_info_group.st_aw := C_ARW_TRANSACTION_DEFAULT; when READ | CHECK => vvc_transaction_info_group.st_ar := C_ARW_TRANSACTION_DEFAULT; when others => null; end case; wait for 0 ns; end procedure reset_arw_vvc_transaction_info; procedure reset_w_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ) is begin vvc_transaction_info_group.st_w := C_W_TRANSACTION_DEFAULT; end procedure reset_w_vvc_transaction_info; procedure reset_b_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ) is begin vvc_transaction_info_group.st_b := C_B_TRANSACTION_DEFAULT; end procedure reset_b_vvc_transaction_info; procedure reset_r_vvc_transaction_info( variable vvc_transaction_info_group : inout t_transaction_group ) is begin vvc_transaction_info_group.st_r := C_R_TRANSACTION_DEFAULT; end procedure reset_r_vvc_transaction_info; --============================================================================== -- VVC Activity --============================================================================== procedure update_vvc_activity_register( signal global_trigger_vvc_activity_register : inout std_logic; variable vvc_status : inout t_vvc_status; constant activity : in t_activity; constant entry_num_in_vvc_activity_register : in integer; constant last_cmd_idx_executed : in natural; constant command_queue_is_empty : in boolean; constant scope : in string := C_VVC_NAME) is variable v_activity : t_activity := activity; begin -- Update vvc_status after a command has finished (during same delta cycle the activity register is updated) if activity = INACTIVE then vvc_status.previous_cmd_idx := last_cmd_idx_executed; vvc_status.current_cmd_idx := 0; end if; if v_activity = INACTIVE and not(command_queue_is_empty) then v_activity := ACTIVE; end if; shared_vvc_activity_register.priv_report_vvc_activity(vvc_idx => entry_num_in_vvc_activity_register, activity => v_activity, last_cmd_idx_executed => last_cmd_idx_executed); if global_trigger_vvc_activity_register /= 'L' then wait until global_trigger_vvc_activity_register = 'L'; end if; gen_pulse(global_trigger_vvc_activity_register, 0 ns, "pulsing global trigger for vvc activity register", scope, ID_NEVER); end procedure; end package body vvc_methods_pkg;
-- Libraries imports library ieee; use ieee.std_logic_1164.all; -- Module interface description entity my_module is port( clk : in std_logic; o : out std_logic ); end entity; -- Module architecture description architecture rtl of my_module is signal d : std_logic; signal q : std_logic; begin -- Combinatorial logic o <= q; d <= not q; -- Synchronous logic process(clk) begin if rising_edge(clk) then d <= q end if; end process end rtl;
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------- --Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017 --Date : Mon Mar 20 20:54:09 2017 --Host : N73-PC running 64-bit major release (build 9200) --Command : generate_target system_wrapper.bd --Design : system_wrapper --Purpose : IP block netlist ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_wrapper is port ( DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 ); DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); DDR3_cas_n : out STD_LOGIC; DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_ras_n : out STD_LOGIC; DDR3_reset_n : out STD_LOGIC; DDR3_we_n : out STD_LOGIC; Vaux0_v_n : in STD_LOGIC; Vaux0_v_p : in STD_LOGIC; Vaux10_v_n : in STD_LOGIC; Vaux10_v_p : in STD_LOGIC; Vaux12_v_n : in STD_LOGIC; Vaux12_v_p : in STD_LOGIC; Vaux13_v_n : in STD_LOGIC; Vaux13_v_p : in STD_LOGIC; Vaux14_v_n : in STD_LOGIC; Vaux14_v_p : in STD_LOGIC; Vaux15_v_n : in STD_LOGIC; Vaux15_v_p : in STD_LOGIC; Vaux1_v_n : in STD_LOGIC; Vaux1_v_p : in STD_LOGIC; Vaux2_v_n : in STD_LOGIC; Vaux2_v_p : in STD_LOGIC; Vaux4_v_n : in STD_LOGIC; Vaux4_v_p : in STD_LOGIC; Vaux5_v_n : in STD_LOGIC; Vaux5_v_p : in STD_LOGIC; Vaux6_v_n : in STD_LOGIC; Vaux6_v_p : in STD_LOGIC; Vaux7_v_n : in STD_LOGIC; Vaux7_v_p : in STD_LOGIC; Vaux9_v_n : in STD_LOGIC; Vaux9_v_p : in STD_LOGIC; Vp_Vn_v_n : in STD_LOGIC; Vp_Vn_v_p : in STD_LOGIC; dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); eth_mdio_mdc_mdc : out STD_LOGIC; eth_mdio_mdc_mdio_io : inout STD_LOGIC; eth_mii_col : in STD_LOGIC; eth_mii_crs : in STD_LOGIC; eth_mii_rst_n : out STD_LOGIC; eth_mii_rx_clk : in STD_LOGIC; eth_mii_rx_dv : in STD_LOGIC; eth_mii_rx_er : in STD_LOGIC; eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 ); eth_mii_tx_clk : in STD_LOGIC; eth_mii_tx_en : out STD_LOGIC; eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 ); eth_ref_clk : out STD_LOGIC; i2c_pullups_tri_io : inout STD_LOGIC_VECTOR ( 1 downto 0 ); i2c_scl_io : inout STD_LOGIC; i2c_sda_io : inout STD_LOGIC; led_4bits_tri_io : inout STD_LOGIC_VECTOR ( 3 downto 0 ); push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); qspi_flash_io0_io : inout STD_LOGIC; qspi_flash_io1_io : inout STD_LOGIC; qspi_flash_io2_io : inout STD_LOGIC; qspi_flash_io3_io : inout STD_LOGIC; qspi_flash_sck_io : inout STD_LOGIC; qspi_flash_ss_io : inout STD_LOGIC; reset : in STD_LOGIC; rgb_led_tri_io : inout STD_LOGIC_VECTOR ( 11 downto 0 ); shield_dp0_dp19_tri_io : inout STD_LOGIC_VECTOR ( 19 downto 0 ); shield_dp26_dp41_tri_io : inout STD_LOGIC_VECTOR ( 15 downto 0 ); spi_io0_io : inout STD_LOGIC; spi_io1_io : inout STD_LOGIC; spi_sck_io : inout STD_LOGIC; spi_ss_io : inout STD_LOGIC; sys_clock : in STD_LOGIC; usb_uart_rxd : in STD_LOGIC; usb_uart_txd : out STD_LOGIC ); end system_wrapper; architecture STRUCTURE of system_wrapper is component system is port ( DDR3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); DDR3_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR3_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); DDR3_addr : out STD_LOGIC_VECTOR ( 13 downto 0 ); DDR3_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); DDR3_ras_n : out STD_LOGIC; DDR3_cas_n : out STD_LOGIC; DDR3_we_n : out STD_LOGIC; DDR3_reset_n : out STD_LOGIC; DDR3_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); DDR3_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); DDR3_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); Vaux0_v_n : in STD_LOGIC; Vaux0_v_p : in STD_LOGIC; Vaux1_v_n : in STD_LOGIC; Vaux1_v_p : in STD_LOGIC; Vaux2_v_n : in STD_LOGIC; Vaux2_v_p : in STD_LOGIC; Vaux4_v_n : in STD_LOGIC; Vaux4_v_p : in STD_LOGIC; Vaux5_v_n : in STD_LOGIC; Vaux5_v_p : in STD_LOGIC; Vaux6_v_n : in STD_LOGIC; Vaux6_v_p : in STD_LOGIC; Vaux7_v_n : in STD_LOGIC; Vaux7_v_p : in STD_LOGIC; Vaux9_v_n : in STD_LOGIC; Vaux9_v_p : in STD_LOGIC; Vaux10_v_n : in STD_LOGIC; Vaux10_v_p : in STD_LOGIC; Vaux12_v_n : in STD_LOGIC; Vaux12_v_p : in STD_LOGIC; Vaux13_v_n : in STD_LOGIC; Vaux13_v_p : in STD_LOGIC; Vaux14_v_n : in STD_LOGIC; Vaux14_v_p : in STD_LOGIC; Vaux15_v_n : in STD_LOGIC; Vaux15_v_p : in STD_LOGIC; Vp_Vn_v_n : in STD_LOGIC; Vp_Vn_v_p : in STD_LOGIC; dip_switches_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); eth_mdio_mdc_mdc : out STD_LOGIC; eth_mdio_mdc_mdio_i : in STD_LOGIC; eth_mdio_mdc_mdio_o : out STD_LOGIC; eth_mdio_mdc_mdio_t : out STD_LOGIC; eth_mii_col : in STD_LOGIC; eth_mii_crs : in STD_LOGIC; eth_mii_rst_n : out STD_LOGIC; eth_mii_rx_clk : in STD_LOGIC; eth_mii_rx_dv : in STD_LOGIC; eth_mii_rx_er : in STD_LOGIC; eth_mii_rxd : in STD_LOGIC_VECTOR ( 3 downto 0 ); eth_mii_tx_clk : in STD_LOGIC; eth_mii_tx_en : out STD_LOGIC; eth_mii_txd : out STD_LOGIC_VECTOR ( 3 downto 0 ); i2c_scl_i : in STD_LOGIC; i2c_scl_o : out STD_LOGIC; i2c_scl_t : out STD_LOGIC; i2c_sda_i : in STD_LOGIC; i2c_sda_o : out STD_LOGIC; i2c_sda_t : out STD_LOGIC; i2c_pullups_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 ); i2c_pullups_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 ); i2c_pullups_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 ); led_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); led_4bits_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 ); led_4bits_tri_t : out STD_LOGIC_VECTOR ( 3 downto 0 ); push_buttons_4bits_tri_i : in STD_LOGIC_VECTOR ( 3 downto 0 ); qspi_flash_io0_i : in STD_LOGIC; qspi_flash_io0_o : out STD_LOGIC; qspi_flash_io0_t : out STD_LOGIC; qspi_flash_io1_i : in STD_LOGIC; qspi_flash_io1_o : out STD_LOGIC; qspi_flash_io1_t : out STD_LOGIC; qspi_flash_io2_i : in STD_LOGIC; qspi_flash_io2_o : out STD_LOGIC; qspi_flash_io2_t : out STD_LOGIC; qspi_flash_io3_i : in STD_LOGIC; qspi_flash_io3_o : out STD_LOGIC; qspi_flash_io3_t : out STD_LOGIC; qspi_flash_sck_i : in STD_LOGIC; qspi_flash_sck_o : out STD_LOGIC; qspi_flash_sck_t : out STD_LOGIC; qspi_flash_ss_i : in STD_LOGIC; qspi_flash_ss_o : out STD_LOGIC; qspi_flash_ss_t : out STD_LOGIC; rgb_led_tri_i : in STD_LOGIC_VECTOR ( 11 downto 0 ); rgb_led_tri_o : out STD_LOGIC_VECTOR ( 11 downto 0 ); rgb_led_tri_t : out STD_LOGIC_VECTOR ( 11 downto 0 ); shield_dp0_dp19_tri_i : in STD_LOGIC_VECTOR ( 19 downto 0 ); shield_dp0_dp19_tri_o : out STD_LOGIC_VECTOR ( 19 downto 0 ); shield_dp0_dp19_tri_t : out STD_LOGIC_VECTOR ( 19 downto 0 ); shield_dp26_dp41_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 ); shield_dp26_dp41_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); shield_dp26_dp41_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 ); spi_io0_i : in STD_LOGIC; spi_io0_o : out STD_LOGIC; spi_io0_t : out STD_LOGIC; spi_io1_i : in STD_LOGIC; spi_io1_o : out STD_LOGIC; spi_io1_t : out STD_LOGIC; spi_sck_i : in STD_LOGIC; spi_sck_o : out STD_LOGIC; spi_sck_t : out STD_LOGIC; spi_ss_i : in STD_LOGIC; spi_ss_o : out STD_LOGIC; spi_ss_t : out STD_LOGIC; usb_uart_rxd : in STD_LOGIC; usb_uart_txd : out STD_LOGIC; eth_ref_clk : out STD_LOGIC; reset : in STD_LOGIC; sys_clock : in STD_LOGIC ); end component system; component IOBUF is port ( I : in STD_LOGIC; O : out STD_LOGIC; T : in STD_LOGIC; IO : inout STD_LOGIC ); end component IOBUF; signal eth_mdio_mdc_mdio_i : STD_LOGIC; signal eth_mdio_mdc_mdio_o : STD_LOGIC; signal eth_mdio_mdc_mdio_t : STD_LOGIC; signal i2c_pullups_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal i2c_pullups_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal i2c_pullups_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal i2c_pullups_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal i2c_pullups_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal i2c_pullups_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal i2c_pullups_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal i2c_pullups_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal i2c_scl_i : STD_LOGIC; signal i2c_scl_o : STD_LOGIC; signal i2c_scl_t : STD_LOGIC; signal i2c_sda_i : STD_LOGIC; signal i2c_sda_o : STD_LOGIC; signal i2c_sda_t : STD_LOGIC; signal led_4bits_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal led_4bits_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal led_4bits_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal led_4bits_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal led_4bits_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal led_4bits_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal led_4bits_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal led_4bits_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal led_4bits_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal led_4bits_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal led_4bits_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal led_4bits_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal led_4bits_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal led_4bits_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal led_4bits_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal led_4bits_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal qspi_flash_io0_i : STD_LOGIC; signal qspi_flash_io0_o : STD_LOGIC; signal qspi_flash_io0_t : STD_LOGIC; signal qspi_flash_io1_i : STD_LOGIC; signal qspi_flash_io1_o : STD_LOGIC; signal qspi_flash_io1_t : STD_LOGIC; signal qspi_flash_io2_i : STD_LOGIC; signal qspi_flash_io2_o : STD_LOGIC; signal qspi_flash_io2_t : STD_LOGIC; signal qspi_flash_io3_i : STD_LOGIC; signal qspi_flash_io3_o : STD_LOGIC; signal qspi_flash_io3_t : STD_LOGIC; signal qspi_flash_sck_i : STD_LOGIC; signal qspi_flash_sck_o : STD_LOGIC; signal qspi_flash_sck_t : STD_LOGIC; signal qspi_flash_ss_i : STD_LOGIC; signal qspi_flash_ss_o : STD_LOGIC; signal qspi_flash_ss_t : STD_LOGIC; signal rgb_led_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal rgb_led_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal rgb_led_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal rgb_led_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal rgb_led_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal rgb_led_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal rgb_led_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal rgb_led_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal rgb_led_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal rgb_led_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal rgb_led_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal rgb_led_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal rgb_led_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal rgb_led_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal rgb_led_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal rgb_led_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal rgb_led_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal rgb_led_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal rgb_led_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal rgb_led_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal rgb_led_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal rgb_led_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal rgb_led_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal rgb_led_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal rgb_led_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal rgb_led_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal rgb_led_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal rgb_led_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal rgb_led_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal rgb_led_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal rgb_led_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal rgb_led_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal rgb_led_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal rgb_led_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal rgb_led_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal rgb_led_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal rgb_led_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal rgb_led_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal rgb_led_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal rgb_led_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal rgb_led_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal rgb_led_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal rgb_led_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal rgb_led_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal rgb_led_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal rgb_led_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal rgb_led_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal rgb_led_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp0_dp19_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp0_dp19_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp0_dp19_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp0_dp19_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp0_dp19_tri_i_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp0_dp19_tri_i_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp0_dp19_tri_i_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp0_dp19_tri_i_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp0_dp19_tri_i_16 : STD_LOGIC_VECTOR ( 16 to 16 ); signal shield_dp0_dp19_tri_i_17 : STD_LOGIC_VECTOR ( 17 to 17 ); signal shield_dp0_dp19_tri_i_18 : STD_LOGIC_VECTOR ( 18 to 18 ); signal shield_dp0_dp19_tri_i_19 : STD_LOGIC_VECTOR ( 19 to 19 ); signal shield_dp0_dp19_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp0_dp19_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp0_dp19_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp0_dp19_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp0_dp19_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp0_dp19_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp0_dp19_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp0_dp19_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp0_dp19_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp0_dp19_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp0_dp19_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp0_dp19_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp0_dp19_tri_io_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp0_dp19_tri_io_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp0_dp19_tri_io_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp0_dp19_tri_io_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp0_dp19_tri_io_16 : STD_LOGIC_VECTOR ( 16 to 16 ); signal shield_dp0_dp19_tri_io_17 : STD_LOGIC_VECTOR ( 17 to 17 ); signal shield_dp0_dp19_tri_io_18 : STD_LOGIC_VECTOR ( 18 to 18 ); signal shield_dp0_dp19_tri_io_19 : STD_LOGIC_VECTOR ( 19 to 19 ); signal shield_dp0_dp19_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp0_dp19_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp0_dp19_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp0_dp19_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp0_dp19_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp0_dp19_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp0_dp19_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp0_dp19_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp0_dp19_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp0_dp19_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp0_dp19_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp0_dp19_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp0_dp19_tri_o_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp0_dp19_tri_o_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp0_dp19_tri_o_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp0_dp19_tri_o_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp0_dp19_tri_o_16 : STD_LOGIC_VECTOR ( 16 to 16 ); signal shield_dp0_dp19_tri_o_17 : STD_LOGIC_VECTOR ( 17 to 17 ); signal shield_dp0_dp19_tri_o_18 : STD_LOGIC_VECTOR ( 18 to 18 ); signal shield_dp0_dp19_tri_o_19 : STD_LOGIC_VECTOR ( 19 to 19 ); signal shield_dp0_dp19_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp0_dp19_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp0_dp19_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp0_dp19_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp0_dp19_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp0_dp19_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp0_dp19_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp0_dp19_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp0_dp19_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp0_dp19_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp0_dp19_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp0_dp19_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp0_dp19_tri_t_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp0_dp19_tri_t_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp0_dp19_tri_t_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp0_dp19_tri_t_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp0_dp19_tri_t_16 : STD_LOGIC_VECTOR ( 16 to 16 ); signal shield_dp0_dp19_tri_t_17 : STD_LOGIC_VECTOR ( 17 to 17 ); signal shield_dp0_dp19_tri_t_18 : STD_LOGIC_VECTOR ( 18 to 18 ); signal shield_dp0_dp19_tri_t_19 : STD_LOGIC_VECTOR ( 19 to 19 ); signal shield_dp0_dp19_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp0_dp19_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp0_dp19_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp0_dp19_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp0_dp19_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp0_dp19_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp0_dp19_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp0_dp19_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp26_dp41_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp26_dp41_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp26_dp41_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp26_dp41_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp26_dp41_tri_i_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp26_dp41_tri_i_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp26_dp41_tri_i_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp26_dp41_tri_i_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp26_dp41_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp26_dp41_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp26_dp41_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp26_dp41_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp26_dp41_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp26_dp41_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp26_dp41_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp26_dp41_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp26_dp41_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp26_dp41_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp26_dp41_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp26_dp41_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp26_dp41_tri_io_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp26_dp41_tri_io_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp26_dp41_tri_io_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp26_dp41_tri_io_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp26_dp41_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp26_dp41_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp26_dp41_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp26_dp41_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp26_dp41_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp26_dp41_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp26_dp41_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp26_dp41_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp26_dp41_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp26_dp41_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp26_dp41_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp26_dp41_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp26_dp41_tri_o_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp26_dp41_tri_o_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp26_dp41_tri_o_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp26_dp41_tri_o_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp26_dp41_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp26_dp41_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp26_dp41_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp26_dp41_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp26_dp41_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp26_dp41_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp26_dp41_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp26_dp41_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal shield_dp26_dp41_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal shield_dp26_dp41_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 ); signal shield_dp26_dp41_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 ); signal shield_dp26_dp41_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 ); signal shield_dp26_dp41_tri_t_12 : STD_LOGIC_VECTOR ( 12 to 12 ); signal shield_dp26_dp41_tri_t_13 : STD_LOGIC_VECTOR ( 13 to 13 ); signal shield_dp26_dp41_tri_t_14 : STD_LOGIC_VECTOR ( 14 to 14 ); signal shield_dp26_dp41_tri_t_15 : STD_LOGIC_VECTOR ( 15 to 15 ); signal shield_dp26_dp41_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 ); signal shield_dp26_dp41_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 ); signal shield_dp26_dp41_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 ); signal shield_dp26_dp41_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 ); signal shield_dp26_dp41_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 ); signal shield_dp26_dp41_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 ); signal shield_dp26_dp41_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 ); signal shield_dp26_dp41_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 ); signal spi_io0_i : STD_LOGIC; signal spi_io0_o : STD_LOGIC; signal spi_io0_t : STD_LOGIC; signal spi_io1_i : STD_LOGIC; signal spi_io1_o : STD_LOGIC; signal spi_io1_t : STD_LOGIC; signal spi_sck_i : STD_LOGIC; signal spi_sck_o : STD_LOGIC; signal spi_sck_t : STD_LOGIC; signal spi_ss_i : STD_LOGIC; signal spi_ss_o : STD_LOGIC; signal spi_ss_t : STD_LOGIC; begin eth_mdio_mdc_mdio_iobuf: component IOBUF port map ( I => eth_mdio_mdc_mdio_o, IO => eth_mdio_mdc_mdio_io, O => eth_mdio_mdc_mdio_i, T => eth_mdio_mdc_mdio_t ); i2c_pullups_tri_iobuf_0: component IOBUF port map ( I => i2c_pullups_tri_o_0(0), IO => i2c_pullups_tri_io(0), O => i2c_pullups_tri_i_0(0), T => i2c_pullups_tri_t_0(0) ); i2c_pullups_tri_iobuf_1: component IOBUF port map ( I => i2c_pullups_tri_o_1(1), IO => i2c_pullups_tri_io(1), O => i2c_pullups_tri_i_1(1), T => i2c_pullups_tri_t_1(1) ); i2c_scl_iobuf: component IOBUF port map ( I => i2c_scl_o, IO => i2c_scl_io, O => i2c_scl_i, T => i2c_scl_t ); i2c_sda_iobuf: component IOBUF port map ( I => i2c_sda_o, IO => i2c_sda_io, O => i2c_sda_i, T => i2c_sda_t ); led_4bits_tri_iobuf_0: component IOBUF port map ( I => led_4bits_tri_o_0(0), IO => led_4bits_tri_io(0), O => led_4bits_tri_i_0(0), T => led_4bits_tri_t_0(0) ); led_4bits_tri_iobuf_1: component IOBUF port map ( I => led_4bits_tri_o_1(1), IO => led_4bits_tri_io(1), O => led_4bits_tri_i_1(1), T => led_4bits_tri_t_1(1) ); led_4bits_tri_iobuf_2: component IOBUF port map ( I => led_4bits_tri_o_2(2), IO => led_4bits_tri_io(2), O => led_4bits_tri_i_2(2), T => led_4bits_tri_t_2(2) ); led_4bits_tri_iobuf_3: component IOBUF port map ( I => led_4bits_tri_o_3(3), IO => led_4bits_tri_io(3), O => led_4bits_tri_i_3(3), T => led_4bits_tri_t_3(3) ); qspi_flash_io0_iobuf: component IOBUF port map ( I => qspi_flash_io0_o, IO => qspi_flash_io0_io, O => qspi_flash_io0_i, T => qspi_flash_io0_t ); qspi_flash_io1_iobuf: component IOBUF port map ( I => qspi_flash_io1_o, IO => qspi_flash_io1_io, O => qspi_flash_io1_i, T => qspi_flash_io1_t ); qspi_flash_io2_iobuf: component IOBUF port map ( I => qspi_flash_io2_o, IO => qspi_flash_io2_io, O => qspi_flash_io2_i, T => qspi_flash_io2_t ); qspi_flash_io3_iobuf: component IOBUF port map ( I => qspi_flash_io3_o, IO => qspi_flash_io3_io, O => qspi_flash_io3_i, T => qspi_flash_io3_t ); qspi_flash_sck_iobuf: component IOBUF port map ( I => qspi_flash_sck_o, IO => qspi_flash_sck_io, O => qspi_flash_sck_i, T => qspi_flash_sck_t ); qspi_flash_ss_iobuf: component IOBUF port map ( I => qspi_flash_ss_o, IO => qspi_flash_ss_io, O => qspi_flash_ss_i, T => qspi_flash_ss_t ); rgb_led_tri_iobuf_0: component IOBUF port map ( I => rgb_led_tri_o_0(0), IO => rgb_led_tri_io(0), O => rgb_led_tri_i_0(0), T => rgb_led_tri_t_0(0) ); rgb_led_tri_iobuf_1: component IOBUF port map ( I => rgb_led_tri_o_1(1), IO => rgb_led_tri_io(1), O => rgb_led_tri_i_1(1), T => rgb_led_tri_t_1(1) ); rgb_led_tri_iobuf_10: component IOBUF port map ( I => rgb_led_tri_o_10(10), IO => rgb_led_tri_io(10), O => rgb_led_tri_i_10(10), T => rgb_led_tri_t_10(10) ); rgb_led_tri_iobuf_11: component IOBUF port map ( I => rgb_led_tri_o_11(11), IO => rgb_led_tri_io(11), O => rgb_led_tri_i_11(11), T => rgb_led_tri_t_11(11) ); rgb_led_tri_iobuf_2: component IOBUF port map ( I => rgb_led_tri_o_2(2), IO => rgb_led_tri_io(2), O => rgb_led_tri_i_2(2), T => rgb_led_tri_t_2(2) ); rgb_led_tri_iobuf_3: component IOBUF port map ( I => rgb_led_tri_o_3(3), IO => rgb_led_tri_io(3), O => rgb_led_tri_i_3(3), T => rgb_led_tri_t_3(3) ); rgb_led_tri_iobuf_4: component IOBUF port map ( I => rgb_led_tri_o_4(4), IO => rgb_led_tri_io(4), O => rgb_led_tri_i_4(4), T => rgb_led_tri_t_4(4) ); rgb_led_tri_iobuf_5: component IOBUF port map ( I => rgb_led_tri_o_5(5), IO => rgb_led_tri_io(5), O => rgb_led_tri_i_5(5), T => rgb_led_tri_t_5(5) ); rgb_led_tri_iobuf_6: component IOBUF port map ( I => rgb_led_tri_o_6(6), IO => rgb_led_tri_io(6), O => rgb_led_tri_i_6(6), T => rgb_led_tri_t_6(6) ); rgb_led_tri_iobuf_7: component IOBUF port map ( I => rgb_led_tri_o_7(7), IO => rgb_led_tri_io(7), O => rgb_led_tri_i_7(7), T => rgb_led_tri_t_7(7) ); rgb_led_tri_iobuf_8: component IOBUF port map ( I => rgb_led_tri_o_8(8), IO => rgb_led_tri_io(8), O => rgb_led_tri_i_8(8), T => rgb_led_tri_t_8(8) ); rgb_led_tri_iobuf_9: component IOBUF port map ( I => rgb_led_tri_o_9(9), IO => rgb_led_tri_io(9), O => rgb_led_tri_i_9(9), T => rgb_led_tri_t_9(9) ); shield_dp0_dp19_tri_iobuf_0: component IOBUF port map ( I => shield_dp0_dp19_tri_o_0(0), IO => shield_dp0_dp19_tri_io(0), O => shield_dp0_dp19_tri_i_0(0), T => shield_dp0_dp19_tri_t_0(0) ); shield_dp0_dp19_tri_iobuf_1: component IOBUF port map ( I => shield_dp0_dp19_tri_o_1(1), IO => shield_dp0_dp19_tri_io(1), O => shield_dp0_dp19_tri_i_1(1), T => shield_dp0_dp19_tri_t_1(1) ); shield_dp0_dp19_tri_iobuf_10: component IOBUF port map ( I => shield_dp0_dp19_tri_o_10(10), IO => shield_dp0_dp19_tri_io(10), O => shield_dp0_dp19_tri_i_10(10), T => shield_dp0_dp19_tri_t_10(10) ); shield_dp0_dp19_tri_iobuf_11: component IOBUF port map ( I => shield_dp0_dp19_tri_o_11(11), IO => shield_dp0_dp19_tri_io(11), O => shield_dp0_dp19_tri_i_11(11), T => shield_dp0_dp19_tri_t_11(11) ); shield_dp0_dp19_tri_iobuf_12: component IOBUF port map ( I => shield_dp0_dp19_tri_o_12(12), IO => shield_dp0_dp19_tri_io(12), O => shield_dp0_dp19_tri_i_12(12), T => shield_dp0_dp19_tri_t_12(12) ); shield_dp0_dp19_tri_iobuf_13: component IOBUF port map ( I => shield_dp0_dp19_tri_o_13(13), IO => shield_dp0_dp19_tri_io(13), O => shield_dp0_dp19_tri_i_13(13), T => shield_dp0_dp19_tri_t_13(13) ); shield_dp0_dp19_tri_iobuf_14: component IOBUF port map ( I => shield_dp0_dp19_tri_o_14(14), IO => shield_dp0_dp19_tri_io(14), O => shield_dp0_dp19_tri_i_14(14), T => shield_dp0_dp19_tri_t_14(14) ); shield_dp0_dp19_tri_iobuf_15: component IOBUF port map ( I => shield_dp0_dp19_tri_o_15(15), IO => shield_dp0_dp19_tri_io(15), O => shield_dp0_dp19_tri_i_15(15), T => shield_dp0_dp19_tri_t_15(15) ); shield_dp0_dp19_tri_iobuf_16: component IOBUF port map ( I => shield_dp0_dp19_tri_o_16(16), IO => shield_dp0_dp19_tri_io(16), O => shield_dp0_dp19_tri_i_16(16), T => shield_dp0_dp19_tri_t_16(16) ); shield_dp0_dp19_tri_iobuf_17: component IOBUF port map ( I => shield_dp0_dp19_tri_o_17(17), IO => shield_dp0_dp19_tri_io(17), O => shield_dp0_dp19_tri_i_17(17), T => shield_dp0_dp19_tri_t_17(17) ); shield_dp0_dp19_tri_iobuf_18: component IOBUF port map ( I => shield_dp0_dp19_tri_o_18(18), IO => shield_dp0_dp19_tri_io(18), O => shield_dp0_dp19_tri_i_18(18), T => shield_dp0_dp19_tri_t_18(18) ); shield_dp0_dp19_tri_iobuf_19: component IOBUF port map ( I => shield_dp0_dp19_tri_o_19(19), IO => shield_dp0_dp19_tri_io(19), O => shield_dp0_dp19_tri_i_19(19), T => shield_dp0_dp19_tri_t_19(19) ); shield_dp0_dp19_tri_iobuf_2: component IOBUF port map ( I => shield_dp0_dp19_tri_o_2(2), IO => shield_dp0_dp19_tri_io(2), O => shield_dp0_dp19_tri_i_2(2), T => shield_dp0_dp19_tri_t_2(2) ); shield_dp0_dp19_tri_iobuf_3: component IOBUF port map ( I => shield_dp0_dp19_tri_o_3(3), IO => shield_dp0_dp19_tri_io(3), O => shield_dp0_dp19_tri_i_3(3), T => shield_dp0_dp19_tri_t_3(3) ); shield_dp0_dp19_tri_iobuf_4: component IOBUF port map ( I => shield_dp0_dp19_tri_o_4(4), IO => shield_dp0_dp19_tri_io(4), O => shield_dp0_dp19_tri_i_4(4), T => shield_dp0_dp19_tri_t_4(4) ); shield_dp0_dp19_tri_iobuf_5: component IOBUF port map ( I => shield_dp0_dp19_tri_o_5(5), IO => shield_dp0_dp19_tri_io(5), O => shield_dp0_dp19_tri_i_5(5), T => shield_dp0_dp19_tri_t_5(5) ); shield_dp0_dp19_tri_iobuf_6: component IOBUF port map ( I => shield_dp0_dp19_tri_o_6(6), IO => shield_dp0_dp19_tri_io(6), O => shield_dp0_dp19_tri_i_6(6), T => shield_dp0_dp19_tri_t_6(6) ); shield_dp0_dp19_tri_iobuf_7: component IOBUF port map ( I => shield_dp0_dp19_tri_o_7(7), IO => shield_dp0_dp19_tri_io(7), O => shield_dp0_dp19_tri_i_7(7), T => shield_dp0_dp19_tri_t_7(7) ); shield_dp0_dp19_tri_iobuf_8: component IOBUF port map ( I => shield_dp0_dp19_tri_o_8(8), IO => shield_dp0_dp19_tri_io(8), O => shield_dp0_dp19_tri_i_8(8), T => shield_dp0_dp19_tri_t_8(8) ); shield_dp0_dp19_tri_iobuf_9: component IOBUF port map ( I => shield_dp0_dp19_tri_o_9(9), IO => shield_dp0_dp19_tri_io(9), O => shield_dp0_dp19_tri_i_9(9), T => shield_dp0_dp19_tri_t_9(9) ); shield_dp26_dp41_tri_iobuf_0: component IOBUF port map ( I => shield_dp26_dp41_tri_o_0(0), IO => shield_dp26_dp41_tri_io(0), O => shield_dp26_dp41_tri_i_0(0), T => shield_dp26_dp41_tri_t_0(0) ); shield_dp26_dp41_tri_iobuf_1: component IOBUF port map ( I => shield_dp26_dp41_tri_o_1(1), IO => shield_dp26_dp41_tri_io(1), O => shield_dp26_dp41_tri_i_1(1), T => shield_dp26_dp41_tri_t_1(1) ); shield_dp26_dp41_tri_iobuf_10: component IOBUF port map ( I => shield_dp26_dp41_tri_o_10(10), IO => shield_dp26_dp41_tri_io(10), O => shield_dp26_dp41_tri_i_10(10), T => shield_dp26_dp41_tri_t_10(10) ); shield_dp26_dp41_tri_iobuf_11: component IOBUF port map ( I => shield_dp26_dp41_tri_o_11(11), IO => shield_dp26_dp41_tri_io(11), O => shield_dp26_dp41_tri_i_11(11), T => shield_dp26_dp41_tri_t_11(11) ); shield_dp26_dp41_tri_iobuf_12: component IOBUF port map ( I => shield_dp26_dp41_tri_o_12(12), IO => shield_dp26_dp41_tri_io(12), O => shield_dp26_dp41_tri_i_12(12), T => shield_dp26_dp41_tri_t_12(12) ); shield_dp26_dp41_tri_iobuf_13: component IOBUF port map ( I => shield_dp26_dp41_tri_o_13(13), IO => shield_dp26_dp41_tri_io(13), O => shield_dp26_dp41_tri_i_13(13), T => shield_dp26_dp41_tri_t_13(13) ); shield_dp26_dp41_tri_iobuf_14: component IOBUF port map ( I => shield_dp26_dp41_tri_o_14(14), IO => shield_dp26_dp41_tri_io(14), O => shield_dp26_dp41_tri_i_14(14), T => shield_dp26_dp41_tri_t_14(14) ); shield_dp26_dp41_tri_iobuf_15: component IOBUF port map ( I => shield_dp26_dp41_tri_o_15(15), IO => shield_dp26_dp41_tri_io(15), O => shield_dp26_dp41_tri_i_15(15), T => shield_dp26_dp41_tri_t_15(15) ); shield_dp26_dp41_tri_iobuf_2: component IOBUF port map ( I => shield_dp26_dp41_tri_o_2(2), IO => shield_dp26_dp41_tri_io(2), O => shield_dp26_dp41_tri_i_2(2), T => shield_dp26_dp41_tri_t_2(2) ); shield_dp26_dp41_tri_iobuf_3: component IOBUF port map ( I => shield_dp26_dp41_tri_o_3(3), IO => shield_dp26_dp41_tri_io(3), O => shield_dp26_dp41_tri_i_3(3), T => shield_dp26_dp41_tri_t_3(3) ); shield_dp26_dp41_tri_iobuf_4: component IOBUF port map ( I => shield_dp26_dp41_tri_o_4(4), IO => shield_dp26_dp41_tri_io(4), O => shield_dp26_dp41_tri_i_4(4), T => shield_dp26_dp41_tri_t_4(4) ); shield_dp26_dp41_tri_iobuf_5: component IOBUF port map ( I => shield_dp26_dp41_tri_o_5(5), IO => shield_dp26_dp41_tri_io(5), O => shield_dp26_dp41_tri_i_5(5), T => shield_dp26_dp41_tri_t_5(5) ); shield_dp26_dp41_tri_iobuf_6: component IOBUF port map ( I => shield_dp26_dp41_tri_o_6(6), IO => shield_dp26_dp41_tri_io(6), O => shield_dp26_dp41_tri_i_6(6), T => shield_dp26_dp41_tri_t_6(6) ); shield_dp26_dp41_tri_iobuf_7: component IOBUF port map ( I => shield_dp26_dp41_tri_o_7(7), IO => shield_dp26_dp41_tri_io(7), O => shield_dp26_dp41_tri_i_7(7), T => shield_dp26_dp41_tri_t_7(7) ); shield_dp26_dp41_tri_iobuf_8: component IOBUF port map ( I => shield_dp26_dp41_tri_o_8(8), IO => shield_dp26_dp41_tri_io(8), O => shield_dp26_dp41_tri_i_8(8), T => shield_dp26_dp41_tri_t_8(8) ); shield_dp26_dp41_tri_iobuf_9: component IOBUF port map ( I => shield_dp26_dp41_tri_o_9(9), IO => shield_dp26_dp41_tri_io(9), O => shield_dp26_dp41_tri_i_9(9), T => shield_dp26_dp41_tri_t_9(9) ); spi_io0_iobuf: component IOBUF port map ( I => spi_io0_o, IO => spi_io0_io, O => spi_io0_i, T => spi_io0_t ); spi_io1_iobuf: component IOBUF port map ( I => spi_io1_o, IO => spi_io1_io, O => spi_io1_i, T => spi_io1_t ); spi_sck_iobuf: component IOBUF port map ( I => spi_sck_o, IO => spi_sck_io, O => spi_sck_i, T => spi_sck_t ); spi_ss_iobuf: component IOBUF port map ( I => spi_ss_o, IO => spi_ss_io, O => spi_ss_i, T => spi_ss_t ); system_i: component system port map ( DDR3_addr(13 downto 0) => DDR3_addr(13 downto 0), DDR3_ba(2 downto 0) => DDR3_ba(2 downto 0), DDR3_cas_n => DDR3_cas_n, DDR3_ck_n(0) => DDR3_ck_n(0), DDR3_ck_p(0) => DDR3_ck_p(0), DDR3_cke(0) => DDR3_cke(0), DDR3_cs_n(0) => DDR3_cs_n(0), DDR3_dm(1 downto 0) => DDR3_dm(1 downto 0), DDR3_dq(15 downto 0) => DDR3_dq(15 downto 0), DDR3_dqs_n(1 downto 0) => DDR3_dqs_n(1 downto 0), DDR3_dqs_p(1 downto 0) => DDR3_dqs_p(1 downto 0), DDR3_odt(0) => DDR3_odt(0), DDR3_ras_n => DDR3_ras_n, DDR3_reset_n => DDR3_reset_n, DDR3_we_n => DDR3_we_n, Vaux0_v_n => Vaux0_v_n, Vaux0_v_p => Vaux0_v_p, Vaux10_v_n => Vaux10_v_n, Vaux10_v_p => Vaux10_v_p, Vaux12_v_n => Vaux12_v_n, Vaux12_v_p => Vaux12_v_p, Vaux13_v_n => Vaux13_v_n, Vaux13_v_p => Vaux13_v_p, Vaux14_v_n => Vaux14_v_n, Vaux14_v_p => Vaux14_v_p, Vaux15_v_n => Vaux15_v_n, Vaux15_v_p => Vaux15_v_p, Vaux1_v_n => Vaux1_v_n, Vaux1_v_p => Vaux1_v_p, Vaux2_v_n => Vaux2_v_n, Vaux2_v_p => Vaux2_v_p, Vaux4_v_n => Vaux4_v_n, Vaux4_v_p => Vaux4_v_p, Vaux5_v_n => Vaux5_v_n, Vaux5_v_p => Vaux5_v_p, Vaux6_v_n => Vaux6_v_n, Vaux6_v_p => Vaux6_v_p, Vaux7_v_n => Vaux7_v_n, Vaux7_v_p => Vaux7_v_p, Vaux9_v_n => Vaux9_v_n, Vaux9_v_p => Vaux9_v_p, Vp_Vn_v_n => Vp_Vn_v_n, Vp_Vn_v_p => Vp_Vn_v_p, dip_switches_4bits_tri_i(3 downto 0) => dip_switches_4bits_tri_i(3 downto 0), eth_mdio_mdc_mdc => eth_mdio_mdc_mdc, eth_mdio_mdc_mdio_i => eth_mdio_mdc_mdio_i, eth_mdio_mdc_mdio_o => eth_mdio_mdc_mdio_o, eth_mdio_mdc_mdio_t => eth_mdio_mdc_mdio_t, eth_mii_col => eth_mii_col, eth_mii_crs => eth_mii_crs, eth_mii_rst_n => eth_mii_rst_n, eth_mii_rx_clk => eth_mii_rx_clk, eth_mii_rx_dv => eth_mii_rx_dv, eth_mii_rx_er => eth_mii_rx_er, eth_mii_rxd(3 downto 0) => eth_mii_rxd(3 downto 0), eth_mii_tx_clk => eth_mii_tx_clk, eth_mii_tx_en => eth_mii_tx_en, eth_mii_txd(3 downto 0) => eth_mii_txd(3 downto 0), eth_ref_clk => eth_ref_clk, i2c_pullups_tri_i(1) => i2c_pullups_tri_i_1(1), i2c_pullups_tri_i(0) => i2c_pullups_tri_i_0(0), i2c_pullups_tri_o(1) => i2c_pullups_tri_o_1(1), i2c_pullups_tri_o(0) => i2c_pullups_tri_o_0(0), i2c_pullups_tri_t(1) => i2c_pullups_tri_t_1(1), i2c_pullups_tri_t(0) => i2c_pullups_tri_t_0(0), i2c_scl_i => i2c_scl_i, i2c_scl_o => i2c_scl_o, i2c_scl_t => i2c_scl_t, i2c_sda_i => i2c_sda_i, i2c_sda_o => i2c_sda_o, i2c_sda_t => i2c_sda_t, led_4bits_tri_i(3) => led_4bits_tri_i_3(3), led_4bits_tri_i(2) => led_4bits_tri_i_2(2), led_4bits_tri_i(1) => led_4bits_tri_i_1(1), led_4bits_tri_i(0) => led_4bits_tri_i_0(0), led_4bits_tri_o(3) => led_4bits_tri_o_3(3), led_4bits_tri_o(2) => led_4bits_tri_o_2(2), led_4bits_tri_o(1) => led_4bits_tri_o_1(1), led_4bits_tri_o(0) => led_4bits_tri_o_0(0), led_4bits_tri_t(3) => led_4bits_tri_t_3(3), led_4bits_tri_t(2) => led_4bits_tri_t_2(2), led_4bits_tri_t(1) => led_4bits_tri_t_1(1), led_4bits_tri_t(0) => led_4bits_tri_t_0(0), push_buttons_4bits_tri_i(3 downto 0) => push_buttons_4bits_tri_i(3 downto 0), qspi_flash_io0_i => qspi_flash_io0_i, qspi_flash_io0_o => qspi_flash_io0_o, qspi_flash_io0_t => qspi_flash_io0_t, qspi_flash_io1_i => qspi_flash_io1_i, qspi_flash_io1_o => qspi_flash_io1_o, qspi_flash_io1_t => qspi_flash_io1_t, qspi_flash_io2_i => qspi_flash_io2_i, qspi_flash_io2_o => qspi_flash_io2_o, qspi_flash_io2_t => qspi_flash_io2_t, qspi_flash_io3_i => qspi_flash_io3_i, qspi_flash_io3_o => qspi_flash_io3_o, qspi_flash_io3_t => qspi_flash_io3_t, qspi_flash_sck_i => qspi_flash_sck_i, qspi_flash_sck_o => qspi_flash_sck_o, qspi_flash_sck_t => qspi_flash_sck_t, qspi_flash_ss_i => qspi_flash_ss_i, qspi_flash_ss_o => qspi_flash_ss_o, qspi_flash_ss_t => qspi_flash_ss_t, reset => reset, rgb_led_tri_i(11) => rgb_led_tri_i_11(11), rgb_led_tri_i(10) => rgb_led_tri_i_10(10), rgb_led_tri_i(9) => rgb_led_tri_i_9(9), rgb_led_tri_i(8) => rgb_led_tri_i_8(8), rgb_led_tri_i(7) => rgb_led_tri_i_7(7), rgb_led_tri_i(6) => rgb_led_tri_i_6(6), rgb_led_tri_i(5) => rgb_led_tri_i_5(5), rgb_led_tri_i(4) => rgb_led_tri_i_4(4), rgb_led_tri_i(3) => rgb_led_tri_i_3(3), rgb_led_tri_i(2) => rgb_led_tri_i_2(2), rgb_led_tri_i(1) => rgb_led_tri_i_1(1), rgb_led_tri_i(0) => rgb_led_tri_i_0(0), rgb_led_tri_o(11) => rgb_led_tri_o_11(11), rgb_led_tri_o(10) => rgb_led_tri_o_10(10), rgb_led_tri_o(9) => rgb_led_tri_o_9(9), rgb_led_tri_o(8) => rgb_led_tri_o_8(8), rgb_led_tri_o(7) => rgb_led_tri_o_7(7), rgb_led_tri_o(6) => rgb_led_tri_o_6(6), rgb_led_tri_o(5) => rgb_led_tri_o_5(5), rgb_led_tri_o(4) => rgb_led_tri_o_4(4), rgb_led_tri_o(3) => rgb_led_tri_o_3(3), rgb_led_tri_o(2) => rgb_led_tri_o_2(2), rgb_led_tri_o(1) => rgb_led_tri_o_1(1), rgb_led_tri_o(0) => rgb_led_tri_o_0(0), rgb_led_tri_t(11) => rgb_led_tri_t_11(11), rgb_led_tri_t(10) => rgb_led_tri_t_10(10), rgb_led_tri_t(9) => rgb_led_tri_t_9(9), rgb_led_tri_t(8) => rgb_led_tri_t_8(8), rgb_led_tri_t(7) => rgb_led_tri_t_7(7), rgb_led_tri_t(6) => rgb_led_tri_t_6(6), rgb_led_tri_t(5) => rgb_led_tri_t_5(5), rgb_led_tri_t(4) => rgb_led_tri_t_4(4), rgb_led_tri_t(3) => rgb_led_tri_t_3(3), rgb_led_tri_t(2) => rgb_led_tri_t_2(2), rgb_led_tri_t(1) => rgb_led_tri_t_1(1), rgb_led_tri_t(0) => rgb_led_tri_t_0(0), shield_dp0_dp19_tri_i(19) => shield_dp0_dp19_tri_i_19(19), shield_dp0_dp19_tri_i(18) => shield_dp0_dp19_tri_i_18(18), shield_dp0_dp19_tri_i(17) => shield_dp0_dp19_tri_i_17(17), shield_dp0_dp19_tri_i(16) => shield_dp0_dp19_tri_i_16(16), shield_dp0_dp19_tri_i(15) => shield_dp0_dp19_tri_i_15(15), shield_dp0_dp19_tri_i(14) => shield_dp0_dp19_tri_i_14(14), shield_dp0_dp19_tri_i(13) => shield_dp0_dp19_tri_i_13(13), shield_dp0_dp19_tri_i(12) => shield_dp0_dp19_tri_i_12(12), shield_dp0_dp19_tri_i(11) => shield_dp0_dp19_tri_i_11(11), shield_dp0_dp19_tri_i(10) => shield_dp0_dp19_tri_i_10(10), shield_dp0_dp19_tri_i(9) => shield_dp0_dp19_tri_i_9(9), shield_dp0_dp19_tri_i(8) => shield_dp0_dp19_tri_i_8(8), shield_dp0_dp19_tri_i(7) => shield_dp0_dp19_tri_i_7(7), shield_dp0_dp19_tri_i(6) => shield_dp0_dp19_tri_i_6(6), shield_dp0_dp19_tri_i(5) => shield_dp0_dp19_tri_i_5(5), shield_dp0_dp19_tri_i(4) => shield_dp0_dp19_tri_i_4(4), shield_dp0_dp19_tri_i(3) => shield_dp0_dp19_tri_i_3(3), shield_dp0_dp19_tri_i(2) => shield_dp0_dp19_tri_i_2(2), shield_dp0_dp19_tri_i(1) => shield_dp0_dp19_tri_i_1(1), shield_dp0_dp19_tri_i(0) => shield_dp0_dp19_tri_i_0(0), shield_dp0_dp19_tri_o(19) => shield_dp0_dp19_tri_o_19(19), shield_dp0_dp19_tri_o(18) => shield_dp0_dp19_tri_o_18(18), shield_dp0_dp19_tri_o(17) => shield_dp0_dp19_tri_o_17(17), shield_dp0_dp19_tri_o(16) => shield_dp0_dp19_tri_o_16(16), shield_dp0_dp19_tri_o(15) => shield_dp0_dp19_tri_o_15(15), shield_dp0_dp19_tri_o(14) => shield_dp0_dp19_tri_o_14(14), shield_dp0_dp19_tri_o(13) => shield_dp0_dp19_tri_o_13(13), shield_dp0_dp19_tri_o(12) => shield_dp0_dp19_tri_o_12(12), shield_dp0_dp19_tri_o(11) => shield_dp0_dp19_tri_o_11(11), shield_dp0_dp19_tri_o(10) => shield_dp0_dp19_tri_o_10(10), shield_dp0_dp19_tri_o(9) => shield_dp0_dp19_tri_o_9(9), shield_dp0_dp19_tri_o(8) => shield_dp0_dp19_tri_o_8(8), shield_dp0_dp19_tri_o(7) => shield_dp0_dp19_tri_o_7(7), shield_dp0_dp19_tri_o(6) => shield_dp0_dp19_tri_o_6(6), shield_dp0_dp19_tri_o(5) => shield_dp0_dp19_tri_o_5(5), shield_dp0_dp19_tri_o(4) => shield_dp0_dp19_tri_o_4(4), shield_dp0_dp19_tri_o(3) => shield_dp0_dp19_tri_o_3(3), shield_dp0_dp19_tri_o(2) => shield_dp0_dp19_tri_o_2(2), shield_dp0_dp19_tri_o(1) => shield_dp0_dp19_tri_o_1(1), shield_dp0_dp19_tri_o(0) => shield_dp0_dp19_tri_o_0(0), shield_dp0_dp19_tri_t(19) => shield_dp0_dp19_tri_t_19(19), shield_dp0_dp19_tri_t(18) => shield_dp0_dp19_tri_t_18(18), shield_dp0_dp19_tri_t(17) => shield_dp0_dp19_tri_t_17(17), shield_dp0_dp19_tri_t(16) => shield_dp0_dp19_tri_t_16(16), shield_dp0_dp19_tri_t(15) => shield_dp0_dp19_tri_t_15(15), shield_dp0_dp19_tri_t(14) => shield_dp0_dp19_tri_t_14(14), shield_dp0_dp19_tri_t(13) => shield_dp0_dp19_tri_t_13(13), shield_dp0_dp19_tri_t(12) => shield_dp0_dp19_tri_t_12(12), shield_dp0_dp19_tri_t(11) => shield_dp0_dp19_tri_t_11(11), shield_dp0_dp19_tri_t(10) => shield_dp0_dp19_tri_t_10(10), shield_dp0_dp19_tri_t(9) => shield_dp0_dp19_tri_t_9(9), shield_dp0_dp19_tri_t(8) => shield_dp0_dp19_tri_t_8(8), shield_dp0_dp19_tri_t(7) => shield_dp0_dp19_tri_t_7(7), shield_dp0_dp19_tri_t(6) => shield_dp0_dp19_tri_t_6(6), shield_dp0_dp19_tri_t(5) => shield_dp0_dp19_tri_t_5(5), shield_dp0_dp19_tri_t(4) => shield_dp0_dp19_tri_t_4(4), shield_dp0_dp19_tri_t(3) => shield_dp0_dp19_tri_t_3(3), shield_dp0_dp19_tri_t(2) => shield_dp0_dp19_tri_t_2(2), shield_dp0_dp19_tri_t(1) => shield_dp0_dp19_tri_t_1(1), shield_dp0_dp19_tri_t(0) => shield_dp0_dp19_tri_t_0(0), shield_dp26_dp41_tri_i(15) => shield_dp26_dp41_tri_i_15(15), shield_dp26_dp41_tri_i(14) => shield_dp26_dp41_tri_i_14(14), shield_dp26_dp41_tri_i(13) => shield_dp26_dp41_tri_i_13(13), shield_dp26_dp41_tri_i(12) => shield_dp26_dp41_tri_i_12(12), shield_dp26_dp41_tri_i(11) => shield_dp26_dp41_tri_i_11(11), shield_dp26_dp41_tri_i(10) => shield_dp26_dp41_tri_i_10(10), shield_dp26_dp41_tri_i(9) => shield_dp26_dp41_tri_i_9(9), shield_dp26_dp41_tri_i(8) => shield_dp26_dp41_tri_i_8(8), shield_dp26_dp41_tri_i(7) => shield_dp26_dp41_tri_i_7(7), shield_dp26_dp41_tri_i(6) => shield_dp26_dp41_tri_i_6(6), shield_dp26_dp41_tri_i(5) => shield_dp26_dp41_tri_i_5(5), shield_dp26_dp41_tri_i(4) => shield_dp26_dp41_tri_i_4(4), shield_dp26_dp41_tri_i(3) => shield_dp26_dp41_tri_i_3(3), shield_dp26_dp41_tri_i(2) => shield_dp26_dp41_tri_i_2(2), shield_dp26_dp41_tri_i(1) => shield_dp26_dp41_tri_i_1(1), shield_dp26_dp41_tri_i(0) => shield_dp26_dp41_tri_i_0(0), shield_dp26_dp41_tri_o(15) => shield_dp26_dp41_tri_o_15(15), shield_dp26_dp41_tri_o(14) => shield_dp26_dp41_tri_o_14(14), shield_dp26_dp41_tri_o(13) => shield_dp26_dp41_tri_o_13(13), shield_dp26_dp41_tri_o(12) => shield_dp26_dp41_tri_o_12(12), shield_dp26_dp41_tri_o(11) => shield_dp26_dp41_tri_o_11(11), shield_dp26_dp41_tri_o(10) => shield_dp26_dp41_tri_o_10(10), shield_dp26_dp41_tri_o(9) => shield_dp26_dp41_tri_o_9(9), shield_dp26_dp41_tri_o(8) => shield_dp26_dp41_tri_o_8(8), shield_dp26_dp41_tri_o(7) => shield_dp26_dp41_tri_o_7(7), shield_dp26_dp41_tri_o(6) => shield_dp26_dp41_tri_o_6(6), shield_dp26_dp41_tri_o(5) => shield_dp26_dp41_tri_o_5(5), shield_dp26_dp41_tri_o(4) => shield_dp26_dp41_tri_o_4(4), shield_dp26_dp41_tri_o(3) => shield_dp26_dp41_tri_o_3(3), shield_dp26_dp41_tri_o(2) => shield_dp26_dp41_tri_o_2(2), shield_dp26_dp41_tri_o(1) => shield_dp26_dp41_tri_o_1(1), shield_dp26_dp41_tri_o(0) => shield_dp26_dp41_tri_o_0(0), shield_dp26_dp41_tri_t(15) => shield_dp26_dp41_tri_t_15(15), shield_dp26_dp41_tri_t(14) => shield_dp26_dp41_tri_t_14(14), shield_dp26_dp41_tri_t(13) => shield_dp26_dp41_tri_t_13(13), shield_dp26_dp41_tri_t(12) => shield_dp26_dp41_tri_t_12(12), shield_dp26_dp41_tri_t(11) => shield_dp26_dp41_tri_t_11(11), shield_dp26_dp41_tri_t(10) => shield_dp26_dp41_tri_t_10(10), shield_dp26_dp41_tri_t(9) => shield_dp26_dp41_tri_t_9(9), shield_dp26_dp41_tri_t(8) => shield_dp26_dp41_tri_t_8(8), shield_dp26_dp41_tri_t(7) => shield_dp26_dp41_tri_t_7(7), shield_dp26_dp41_tri_t(6) => shield_dp26_dp41_tri_t_6(6), shield_dp26_dp41_tri_t(5) => shield_dp26_dp41_tri_t_5(5), shield_dp26_dp41_tri_t(4) => shield_dp26_dp41_tri_t_4(4), shield_dp26_dp41_tri_t(3) => shield_dp26_dp41_tri_t_3(3), shield_dp26_dp41_tri_t(2) => shield_dp26_dp41_tri_t_2(2), shield_dp26_dp41_tri_t(1) => shield_dp26_dp41_tri_t_1(1), shield_dp26_dp41_tri_t(0) => shield_dp26_dp41_tri_t_0(0), spi_io0_i => spi_io0_i, spi_io0_o => spi_io0_o, spi_io0_t => spi_io0_t, spi_io1_i => spi_io1_i, spi_io1_o => spi_io1_o, spi_io1_t => spi_io1_t, spi_sck_i => spi_sck_i, spi_sck_o => spi_sck_o, spi_sck_t => spi_sck_t, spi_ss_i => spi_ss_i, spi_ss_o => spi_ss_o, spi_ss_t => spi_ss_t, sys_clock => sys_clock, usb_uart_rxd => usb_uart_rxd, usb_uart_txd => usb_uart_txd ); end STRUCTURE;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: jtagcom -- File: jtagcom.vhd -- Author: Magnus Hjorth - Aeroflex Gaisler -- Description: JTAG Debug Interface with AHB master interface -- Redesigned to work for TCK both slower and faster than AHB ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.libjtagcom.all; use gaisler.misc.all; entity jtagcom2 is generic ( gatetech: integer := 0; isel : integer range 0 to 1 := 0; ainst : integer range 0 to 255 := 2; dinst : integer range 0 to 255 := 3); port ( rst : in std_ulogic; clk : in std_ulogic; tapo : in tap_out_type; tapi : out tap_in_type; dmao : in ahb_dma_out_type; dmai : out ahb_dma_in_type; tckp : in std_ulogic; tckn : in std_ulogic; trst : in std_ulogic ); attribute sync_set_reset of rst : signal is "true"; end; architecture rtl of jtagcom2 is constant ADDBITS : integer := 10; constant NOCMP : boolean := (isel /= 0); type tckpreg_type is record addr : std_logic_vector(34 downto 0); datashft : std_logic_vector(32 downto 0); done_sync : std_ulogic; prun : std_ulogic; inshift : std_ulogic; holdn : std_ulogic; end record; type tcknreg_type is record run: std_ulogic; done_sync1: std_ulogic; qual_rdata: std_ulogic; addrlo : std_logic_vector(ADDBITS-1 downto 2); data : std_logic_vector(32 downto 0); end record; type ahbreg_type is record run_sync: std_logic_vector(1 downto 0); qual_dreg: std_ulogic; qual_areg: std_ulogic; areg: std_logic_vector(34 downto 0); dreg: std_logic_vector(31 downto 0); done: std_ulogic; dmastart: std_ulogic; wdone: std_ulogic; end record; signal ar, arin : ahbreg_type; signal tpr, tprin: tckpreg_type; signal tnr, tnrin: tcknreg_type; signal qual_rdata, rdataq: std_logic_vector(31 downto 0); signal qual_dreg, dregq: std_logic_vector(31 downto 0); signal qual_areg, aregqin, aregq: std_logic_vector(34 downto 0); attribute syn_keep: boolean; attribute syn_keep of rdataq : signal is true; attribute syn_keep of dregq : signal is true; attribute syn_keep of aregq : signal is true; begin rdqgen: for x in 31 downto 0 generate rdq: grnand2 generic map (tech => gatetech) port map (ar.dreg(x), qual_rdata(x), rdataq(x)); end generate; dqgen: for x in 31 downto 0 generate dq: grnand2 generic map (tech => gatetech) port map (tnr.data(x), qual_dreg(x), dregq(x)); end generate; aregqin <= tpr.addr(34 downto ADDBITS) & tnr.addrlo(ADDBITS-1 downto 2) & tpr.addr(1 downto 0); aqgen: for x in 34 downto 0 generate aq: grnand2 generic map (tech => gatetech) port map (aregqin(x), qual_areg(x), aregq(x)); end generate; comb : process (rst, ar, tapo, dmao, tpr, tnr, aregq, dregq, rdataq) variable av : ahbreg_type; variable tpv : tckpreg_type; variable tnv : tcknreg_type; variable vdmai : ahb_dma_in_type; variable asel, dsel : std_ulogic; variable vtapi : tap_in_type; variable write, seq : std_ulogic; begin av := ar; tpv := tpr; tnv := tnr; --------------------------------------------------------------------------- -- TCK side logic --------------------------------------------------------------------------- if NOCMP then asel := tapo.asel; dsel := tapo.dsel; else if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if; if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if; end if; vtapi.en := asel or dsel; vtapi.tdo:=tpr.addr(0); if dsel='1' then vtapi.tdo:=tpr.datashft(0) and tpr.holdn; end if; write := tpr.addr(34); seq := tpr.datashft(32); -- Sync regs using alternating phases tnv.done_sync1 := ar.done; tpv.done_sync := tnr.done_sync1; -- Data CDC qual_rdata <= (others => tnr.qual_rdata); if tnr.qual_rdata='1' then tpv.datashft(32 downto 0) := '1' & (not rdataq); end if; if tapo.capt='1' then tpv.addr(ADDBITS-1 downto 2) := tnr.addrlo; end if; -- Track whether we're in the middle of shifting if tapo.shift='1' then tpv.inshift:='1'; end if; if tapo.upd='1' then tpv.inshift:='0'; end if; if tapo.shift='1' then if asel = '1' and tpr.prun='0' then tpv.addr(34 downto 0) := tapo.tdi & tpr.addr(34 downto 1); end if; if dsel = '1' and tpr.holdn='1' then tpv.datashft(32 downto 0) := tapo.tdi & tpr.datashft(32 downto 1); end if; end if; if tnr.run='0' then tpv.holdn:='1'; end if; tpv.prun := tnr.run; if tpr.prun='0' then tnv.qual_rdata := '0'; if tapo.shift='0' and tapo.upd = '1' then if asel='1' then tnv.addrlo := tpr.addr(ADDBITS-1 downto 2); end if; if dsel='1' then tnv.data := tpr.datashft; end if; if (asel and not write) = '1' then tpv.holdn := '0'; tnv.run := '1'; end if; if (dsel and (write or (not write and seq))) = '1' then tnv.run := '1'; if (seq and not write) = '1' then tnv.addrlo := tnr.addrlo + 1; tpv.holdn := '0'; end if; end if; end if; else if tpr.done_sync='1' and (tpv.inshift='0' or write='1') then tnv.run := '0'; if write='0' then tnv.qual_rdata := '1'; end if; if (write and tnr.data(32)) = '1' then tnv.addrlo := tnr.addrlo + 1; end if; end if; end if; if tapo.reset='1' then tpv.inshift := '0'; tnv.run := '0'; end if; --------------------------------------------------------------------------- -- AHB side logic --------------------------------------------------------------------------- -- Sync regs and CDC transfer av.run_sync := tnr.run & ar.run_sync(1); qual_dreg <= (others => ar.qual_dreg); if ar.qual_dreg='1' then av.dreg:=not dregq; end if; qual_areg <= (others => ar.qual_areg); if ar.qual_areg='1' then av.areg:=not aregq; end if; vdmai.address := ar.areg(31 downto 0); vdmai.wdata := ahbdrivedata(ar.dreg(31 downto 0)); vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := ar.areg(34); vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := '0' & ar.areg(33 downto 32); av.qual_dreg := '0'; av.qual_areg := '0'; vdmai.start := '0'; if ar.dmastart='1' then if dmao.active='1' then if dmao.ready='1' then av.dreg := ahbreadword(dmao.rdata); if ar.areg(34)='0' then av.done := '1'; end if; av.dmastart := '0'; end if; else vdmai.start := '1'; if ar.areg(34)='1' and ar.wdone='0' then av.done := '1'; av.wdone := '1'; end if; end if; end if; if ar.qual_areg='1' then av.dmastart := '1'; av.wdone := '0'; end if; if ar.run_sync(0)='1' and ar.qual_areg='0' and ar.dmastart='0' and ar.done='0' then av.qual_dreg := '1'; av.qual_areg := '1'; end if; if ar.run_sync(0)='0' and ar.done='1' then av.done := '0'; end if; if (rst = '0') then av.qual_dreg := '0'; av.qual_areg := '0'; av.done := '0'; av.areg := (others => '0'); av.dreg := (others => '0'); av.dmastart := '0'; end if; tprin <= tpv; tnrin <= tnv; arin <= av; dmai <= vdmai; tapi <= vtapi; end process; ahbreg : process(clk) begin if rising_edge(clk) then ar <= arin; end if; end process; tckpreg: process(tckp,trst) begin if rising_edge(tckp) then tpr <= tprin; end if; if trst='0' then tpr.done_sync <= '0'; tpr.prun <= '0'; tpr.inshift <= '0'; tpr.holdn <= '1'; end if; end process; tcknreg: process(tckn,trst) begin if rising_edge(tckn) then tnr <= tnrin; end if; if trst='0' then tnr.run <= '0'; tnr.done_sync1 <= '0'; tnr.qual_rdata <= '0'; end if; end process; end;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7.1 Core - Top-level core wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: ram_16x1k_dp_exdes.vhd -- -- Description: -- This is the actual BMG core wrapper. -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: August 31, 2005 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY UNISIM; USE UNISIM.VCOMPONENTS.ALL; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- ENTITY ram_16x1k_dp_exdes IS PORT ( --Inputs - Port A ENA : IN STD_LOGIC; --opt port WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC; --Inputs - Port B ENB : IN STD_LOGIC; --opt port WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKB : IN STD_LOGIC ); END ram_16x1k_dp_exdes; ARCHITECTURE xilinx OF ram_16x1k_dp_exdes IS COMPONENT BUFG IS PORT ( I : IN STD_ULOGIC; O : OUT STD_ULOGIC ); END COMPONENT; COMPONENT ram_16x1k_dp IS PORT ( --Port A ENA : IN STD_LOGIC; --opt port WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKA : IN STD_LOGIC; --Port B ENB : IN STD_LOGIC; --opt port WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0); ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); CLKB : IN STD_LOGIC ); END COMPONENT; SIGNAL CLKA_buf : STD_LOGIC; SIGNAL CLKB_buf : STD_LOGIC; SIGNAL S_ACLK_buf : STD_LOGIC; BEGIN bufg_A : BUFG PORT MAP ( I => CLKA, O => CLKA_buf ); bufg_B : BUFG PORT MAP ( I => CLKB, O => CLKB_buf ); bmg0 : ram_16x1k_dp PORT MAP ( --Port A ENA => ENA, WEA => WEA, ADDRA => ADDRA, DINA => DINA, DOUTA => DOUTA, CLKA => CLKA_buf, --Port B ENB => ENB, WEB => WEB, ADDRB => ADDRB, DINB => DINB, DOUTB => DOUTB, CLKB => CLKB_buf ); END xilinx;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity sub is port ( result : out std_ulogic_vector(3 downto 0); in1 : in std_ulogic_vector(3 downto 0) ); end entity; architecture test of sub is signal in2 : std_ulogic_vector(2 downto 0); begin assert in1(1 downto 0) = "00"; in2 <= "001"; result <= std_ulogic_vector(unsigned(in1) + unsigned(in2)); end architecture; ------------------------------------------------------------------------------- entity ieee6 is end entity; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; architecture test of ieee6 is signal result : std_ulogic_vector(3 downto 0); signal in1 : std_ulogic_vector(1 downto 0); begin uut: entity work.sub port map ( result => result, in1(3 downto 2) => std_ulogic_vector(in1), in1(1 downto 0) => "00" ); stim: process is begin in1 <= "01"; wait for 1 ns; assert result = X"5"; wait; end process; end architecture;
-- Nothing should fail in this entity entity ENT1 is generic ( G_GENERIC1 : std_logic_vector(3 downto 0); G_GENERIC2 : std_logic_vector(0 to 256) ); port ( P_PORT1 : std_logic_vector(15 downto 6); -- DOWNTO P_PORT2 : std_logic_vector(56 to 132) ); end entity ENT1; -- Everything should fail in this entity entity ENT1 is generic ( G_GENERIC1 : std_logic_vector(3 downTo 0); G_GENERIC2 : std_logic_vector(0 TO 256) ); port ( P_PORT1 : std_logic_vector(15 Downto 6); P_PORT2 : std_logic_vector(56 tO 132) ); end entity ENT1; architecture ARCH of ENT1 is constant c_const1 : std_logic_vector(3 DOWNTO 0); -- downto constant c_const2 : std_logic_vector(3 downto 0); constant c_const3 : std_logic_vector(345 To 670); constant c_const4 : std_logic_vector(345 to 670); signal w_sig1 : std_logic_vector(50 dOWnto 45); signal w_sig2 : std_logic_vector(50 downto 45); signal w_sig3 : std_logic_vector(46 TO 345); signal w_sig4 : std_logic_vector(46 to 345); begin end architecture ARCH;
-- Nothing should fail in this entity entity ENT1 is generic ( G_GENERIC1 : std_logic_vector(3 downto 0); G_GENERIC2 : std_logic_vector(0 to 256) ); port ( P_PORT1 : std_logic_vector(15 downto 6); -- DOWNTO P_PORT2 : std_logic_vector(56 to 132) ); end entity ENT1; -- Everything should fail in this entity entity ENT1 is generic ( G_GENERIC1 : std_logic_vector(3 downTo 0); G_GENERIC2 : std_logic_vector(0 TO 256) ); port ( P_PORT1 : std_logic_vector(15 Downto 6); P_PORT2 : std_logic_vector(56 tO 132) ); end entity ENT1; architecture ARCH of ENT1 is constant c_const1 : std_logic_vector(3 DOWNTO 0); -- downto constant c_const2 : std_logic_vector(3 downto 0); constant c_const3 : std_logic_vector(345 To 670); constant c_const4 : std_logic_vector(345 to 670); signal w_sig1 : std_logic_vector(50 dOWnto 45); signal w_sig2 : std_logic_vector(50 downto 45); signal w_sig3 : std_logic_vector(46 TO 345); signal w_sig4 : std_logic_vector(46 to 345); begin end architecture ARCH;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- Thomas B. Preusser -- -- Package: Simulation constants, functions and utilities. -- -- Description: -- ------------------------------------- -- .. TODO:: No documentation available. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany -- Chair of VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.utils.all; -- use PoC.strings.all; use PoC.vectors.all; use PoC.physical.all; use PoC.sim_global.all; use PoC.sim_types.all; use PoC.sim_protected.all; package simulation is -- Legacy interface for pre VHDL-2002 -- =========================================================================== -- prepared aliases, if GHDL gets the aliases fixed. Reported on 08.02.2015 as Issue #38 -- alias simmInitialize is globalSimulationStatus.initialize[NATURAL, TIME]; -- alias simmFinalize is globalSimulationStatus.finalize[]; -- alias simmCreateTest is globalSimulationStatus.createTest[STRING return T_SIM_TEST_ID]; -- alias simmFinalizeTest is globalSimulationStatus.finalizeTest[T_SIM_TEST_ID]; -- alias simmRegisterProcess is globalSimulationStatus.registerProcess[T_SIM_TEST_ID, STRING, BOOLEAN return T_SIM_PROCESS_ID]; -- alias simmRegisterProcess is globalSimulationStatus.registerProcess[STRING, BOOLEAN return T_SIM_PROCESS_ID]; -- alias simmDeactivateProcess is globalSimulationStatus.deactivateProcess[T_SIM_PROCESS_ID]; -- alias simmIsStopped is globalSimulationStatus.isStopped[T_SIM_TEST_ID return BOOLEAN]; -- alias simmIsFinalized is globalSimulationStatus.isFinalized[T_SIM_TEST_ID return BOOLEAN]; -- alias simmIsAllFinalized is globalSimulationStatus.isAllFinalized [return BOOLEAN]; -- alias simmAssertion is globalSimulationStatus.assertion[BOOLEAN, STRING]; -- alias simmFail is globalSimulationStatus.fail[STRING]; -- alias simmWriteMessage is globalSimulationStatus.writeMessage[STRING]; procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high); procedure simFinalize; impure function simCreateTest(Name : string) return T_SIM_TEST_ID; procedure simFinalizeTest(constant TestID : T_SIM_TEST_ID); impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID; procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID); impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean; impure function simIsAllFinalized return boolean; procedure simAssertion(cond : in boolean; Message : in string := ""); procedure simFail(Message : in string := ""); procedure simWriteMessage(Message : in string := ""); -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here -- checksum functions -- =========================================================================== -- TODO: move checksum functions here end package; package body simulation is -- legacy procedures -- =========================================================================== -- TODO: undocumented group procedure simInitialize(MaxAssertFailures : natural := natural'high; MaxSimulationRuntime : TIME := TIME'high) is begin globalSimulationStatus.initialize(MaxAssertFailures, MaxSimulationRuntime); if C_SIM_VERBOSE then report "simInitialize:" severity NOTE; end if; if (MaxSimulationRuntime /= time'high) then wait for MaxSimulationRuntime; report "simInitialize: TIMEOUT" severity ERROR; globalSimulationStatus.finalize; end if; end procedure; procedure simFinalize is begin globalSimulationStatus.finalize; end procedure; impure function simCreateTest(Name : string) return T_SIM_TEST_ID is begin return globalSimulationStatus.createTest(Name); end function; procedure simFinalizeTest(constant TestID : T_SIM_TEST_ID) is begin globalSimulationStatus.finalizeTest(TestID); end procedure; impure function simRegisterProcess(Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is begin return globalSimulationStatus.registerProcess(Name, IsLowPriority); end function; impure function simRegisterProcess(constant TestID : T_SIM_TEST_ID; Name : string; constant IsLowPriority : boolean := FALSE) return T_SIM_PROCESS_ID is begin return globalSimulationStatus.registerProcess(TestID, Name, IsLowPriority); end function; procedure simDeactivateProcess(ProcID : T_SIM_PROCESS_ID) is begin globalSimulationStatus.deactivateProcess(ProcID); end procedure; impure function simIsStopped(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return globalSimulationStatus.isStopped(TestID); end function; impure function simIsFinalized(constant TestID : T_SIM_TEST_ID := C_SIM_DEFAULT_TEST_ID) return boolean is begin return globalSimulationStatus.isFinalized(TestID); end function; impure function simIsAllFinalized return boolean is begin return globalSimulationStatus.isAllFinalized; end function; -- TODO: undocumented group procedure simWriteMessage(Message : in string := "") is begin globalSimulationStatus.writeMessage(Message); end procedure; procedure simFail(Message : in string := "") is begin globalSimulationStatus.fail(Message); end procedure; procedure simAssertion(cond : in boolean; Message : in string := "") is begin globalSimulationStatus.assertion(cond, Message); end procedure; -- checksum functions -- =========================================================================== -- TODO: move checksum functions here end package body;
----------------------------------------------------------------------------- -- LEON3 Demonstration design -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.can.all; use gaisler.net.all; use gaisler.jtag.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW ); port ( pb_sw : in std_logic_vector (4 downto 1); -- push buttons pll_clk : in std_ulogic; -- PLL clock led : out std_logic_vector(8 downto 1); flash_a : out std_logic_vector(20 downto 0); flash_d : inout std_logic_vector(15 downto 0); sdram_a : out std_logic_vector(11 downto 0); sdram_d : inout std_logic_vector(31 downto 0); sdram_ba : out std_logic_vector(3 downto 0); sdram_dqm : out std_logic_vector(3 downto 0); sdram_clk : inout std_ulogic; sdram_cke : out std_ulogic; -- sdram clock enable sdram_csn : out std_ulogic; -- sdram chip select sdram_wen : out std_ulogic; -- sdram write enable sdram_rasn : out std_ulogic; -- sdram ras sdram_casn : out std_ulogic; -- sdram cas uart1_txd : out std_ulogic; uart1_rxd : in std_ulogic; uart1_rts : out std_ulogic; uart1_cts : in std_ulogic; uart2_txd : out std_ulogic; uart2_rxd : in std_ulogic; uart2_rts : out std_ulogic; uart2_cts : in std_ulogic; flash_oen : out std_ulogic; flash_wen : out std_ulogic; flash_cen : out std_ulogic; flash_byte : out std_ulogic; flash_ready : in std_ulogic; flash_rpn : out std_ulogic; flash_wpn : out std_ulogic; phy_mii_data: inout std_logic; -- ethernet PHY interface phy_tx_clk : in std_ulogic; phy_rx_clk : in std_ulogic; phy_rx_data : in std_logic_vector(3 downto 0); phy_dv : in std_ulogic; phy_rx_er : in std_ulogic; phy_col : in std_ulogic; phy_crs : in std_ulogic; phy_tx_data : out std_logic_vector(3 downto 0); phy_tx_en : out std_ulogic; phy_mii_clk : out std_ulogic; phy_100 : in std_ulogic; -- 100 Mbit indicator phy_rst_n : out std_ulogic; gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- lcd_data : inout std_logic_vector(7 downto 0); -- lcd_rs : out std_ulogic; -- lcd_rw : out std_ulogic; -- lcd_en : out std_ulogic; -- lcd_backl : out std_ulogic; can_txd : out std_ulogic; can_rxd : in std_ulogic; smsc_addr : out std_logic_vector(14 downto 0); smsc_data : inout std_logic_vector(31 downto 0); smsc_nbe : out std_logic_vector(3 downto 0); smsc_resetn : out std_ulogic; smsc_ardy : in std_ulogic; -- smsc_intr : in std_ulogic; smsc_nldev : in std_ulogic; smsc_nrd : out std_ulogic; smsc_nwr : out std_ulogic; smsc_ncs : out std_ulogic; smsc_aen : out std_ulogic; smsc_lclk : out std_ulogic; smsc_wnr : out std_ulogic; smsc_rdyrtn : out std_ulogic; smsc_cycle : out std_ulogic; smsc_nads : out std_ulogic ); end; architecture rtl of leon3mp is signal vcc, gnd : std_logic_vector(7 downto 0); signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdram_out_type; signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, rstraw, pciclk, sdclkl : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, u2i, dui : uart_in_type; signal u1o, u2o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal ethi, ethi1, ethi2 : eth_in_type; signal etho, etho1, etho2 : eth_out_type; signal gpti : gptimer_in_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; signal can_lrx, can_ltx : std_ulogic; signal lclk, pci_lclk, sdfb : std_ulogic; signal tck, tms, tdi, tdo : std_ulogic; signal resetn : std_ulogic; signal pbsw : std_logic_vector(4 downto 1); signal ledo : std_logic_vector(8 downto 1); signal memi : memory_in_type; signal memo : memory_out_type; --for smc lan chip signal s_eth_aen : std_logic; signal s_eth_readn : std_logic; signal s_eth_writen: std_logic; signal s_eth_nbe : std_logic_vector(3 downto 0); signal s_eth_din : std_logic_vector(31 downto 0); constant ahbmmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+ CFG_GRETH; constant BOARD_FREQ : integer := 50000; -- board frequency in KHz constant CPU_FREQ : integer := (BOARD_FREQ*CFG_CLKMUL)/CFG_CLKDIV; -- cpu frequency in KHz begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); sdram_clk_pad : skew_outpad generic map (tech => padtech, slew => 1, strength => 24, skew => -60) port map (sdram_clk, sdclkl, rstn); cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; resetn <= pbsw(4); ledo(2) <= not cgo.clklock; ledo(3) <= pbsw(3); clk_pad : clkpad generic map (tech => padtech) port map (pll_clk, lclk); clkgen0 : clkgen -- clock generator generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ) port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo); rst0 : rstgen -- reset generator port map (resetn, clkm, cgo.clklock, rstn, rstraw); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, nahbm => ahbmmax, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; ledo(8) <= dbgo(0).error; dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsui.break <= pbsw(1); ledo(1) <= not dsuo.active; end generate; end generate; nodcom : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0: ahbuart -- Debug UART generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); dui.rxd <= u2i.rxd; u2o.txd <= duo.txd; u2o.rtsn <= gnd(0); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- PROM/SDRAM Memory controller ------------------------------------ ---------------------------------------------------------------------- memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00" when CFG_MCTRL_RAM16BIT = 0 else "01"; mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 : entity work.smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0, srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo, s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe, s_eth_din); addr_pad : outpadv generic map (width => 21, tech => padtech) port map (flash_a(20 downto 0), memo.address(21 downto 1)); roms_pad : outpad generic map (tech => padtech) port map (flash_cen, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (flash_oen, memo.oen); wri_pad : outpad generic map (tech => padtech) port map (flash_wen, memo.writen); rom8 : if CFG_MCTRL_RAM16BIT = 0 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (flash_d(7 downto 0), memo.data(31 downto 24), memo.bdrive(0), memi.data(31 downto 24)); data15_pad : iopad generic map (tech => padtech) port map (flash_d(15), memo.address(0), gnd(0), open); end generate; rom16 : if CFG_MCTRL_RAM16BIT = 1 generate data_pad : iopadv generic map (tech => padtech, width => 16) port map (flash_d(15 downto 0), memo.data(31 downto 16), memo.bdrive(0), memi.data(31 downto 16)); end generate; sa_pad : outpadv generic map (width => 12, tech => padtech) port map (sdram_a, memo.sa(11 downto 0)); sba1_pad : outpadv generic map (width => 2, tech => padtech) port map (sdram_ba(1 downto 0), memo.sa(14 downto 13)); sba2_pad : outpadv generic map (width => 2, tech => padtech) port map (sdram_ba(3 downto 2), memo.sa(14 downto 13)); bdr : for i in 0 to 3 generate sd_pad : iopadv generic map (tech => padtech, width => 8) port map (sdram_d(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8)); end generate; sdcke_pad : outpad generic map (tech => padtech) port map (sdram_cke, sdo.sdcke(0)); sdwen_pad : outpad generic map (tech => padtech) port map (sdram_wen, sdo.sdwen); sdcsn_pad : outpad generic map (tech => padtech) port map (sdram_csn, sdo.sdcsn(0)); sdras_pad : outpad generic map (tech => padtech) port map (sdram_rasn, sdo.rasn); sdcas_pad : outpad generic map (tech => padtech) port map (sdram_casn, sdo.casn); sddqm_pad : outpadv generic map (width => 4, tech => padtech) port map (sdram_dqm, sdo.dqm(3 downto 0)); end generate; nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller sdcke_pad : outpad generic map (tech => padtech) port map (sdram_cke, gnd(0)); sdcsn_pad : outpad generic map (tech => padtech) port map (sdram_csn, vcc(0)); end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(4)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(4) <= ahbs_none; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.extclk <= '0'; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd); ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd); ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts, u1i.ctsn); ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts, u1o.rtsn); ua2 : if (CFG_UART2_ENABLE /= 0) and (CFG_AHB_UART = 0) generate uart2 : apbuart -- UART 2 generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO) port map (rstn, clkm, apbi, apbo(9), u2i, u2o); u2i.extclk <= '0'; end generate; noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate; ua2rx_pad : inpad generic map (tech => padtech) port map (uart2_rxd, u2i.rxd); ua2tx_pad : outpad generic map (tech => padtech) port map (uart2_txd, u2o.txd); ua2cts_pad : inpad generic map (tech => padtech) port map (uart2_cts, u2i.ctsn); ua2rts_pad : outpad generic map (tech => padtech) port map (uart2_rts, u2o.rtsn); irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5), gpioi => gpioi, gpioo => gpioo); pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate pio_pad : iopad generic map (tech => padtech) port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, pindex => 15, paddr => 15, pirq => 12, memtech => memtech, mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho); end generate; ethpads : if CFG_GRETH = 0 generate -- no eth etho <= eth_out_none; end generate; emdio_pad : iopad generic map (tech => padtech) port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i); etxc_pad : clkpad generic map (tech => padtech, arch => 0) port map (phy_tx_clk, ethi.tx_clk); erxc_pad : clkpad generic map (tech => padtech, arch => 0) port map (phy_rx_clk, ethi.rx_clk); erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (phy_rx_data, ethi.rxd(3 downto 0)); erxdv_pad : inpad generic map (tech => padtech) port map (phy_dv, ethi.rx_dv); erxer_pad : inpad generic map (tech => padtech) port map (phy_rx_er, ethi.rx_er); erxco_pad : inpad generic map (tech => padtech) port map (phy_col, ethi.rx_col); erxcr_pad : inpad generic map (tech => padtech) port map (phy_crs, ethi.rx_crs); etxd_pad : outpadv generic map (tech => padtech, width => 4) port map (phy_tx_data, etho.txd(3 downto 0)); etxen_pad : outpad generic map (tech => padtech) port map ( phy_tx_en, etho.tx_en); emdc_pad : outpad generic map (tech => padtech) port map (phy_mii_clk, etho.mdc); ereset_pad : outpad generic map (tech => padtech) port map (phy_rst_n, rstn); ----------------------------------------------------------------------- --- CAN -------------------------------------------------------------- ----------------------------------------------------------------------- can0 : if CFG_CAN = 1 generate can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO, iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech) port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx ); end generate; ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate; can_loopback : if CFG_CANLOOP = 1 generate can_lrx <= can_ltx; end generate; can_pads : if CFG_CANLOOP = 0 generate can_tx_pad : outpad generic map (tech => padtech) port map (can_txd, can_ltx); can_rx_pad : inpad generic map (tech => padtech) port map (can_rxd, can_lrx); end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ocram : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map ( rstn, clkm, ahbsi, ahbso(7)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- I/O interface --------------------------------------------------- ----------------------------------------------------------------------- pb_sw_pad : inpadv generic map (width => 4, tech => padtech) port map (pb_sw, pbsw); led_pad : outpadv generic map (width => 8, tech => padtech) port map (led, ledo); rom8 : if CFG_MCTRL_RAM16BIT = 0 generate byte_pad : outpad generic map (tech => padtech) port map (flash_byte, gnd(0)); end generate; rom16 : if CFG_MCTRL_RAM16BIT = 1 generate byte_pad : outpad generic map (tech => padtech) port map (flash_byte, vcc(0)); end generate; rpn_pad : outpad generic map (tech => padtech) port map (flash_rpn, rstn); wpn_pad : outpad generic map (tech => padtech) port map (flash_wpn, vcc(0)); ready_pad : inpad generic map (tech => padtech) port map (flash_ready, open); smsc_data_pads : for i in 0 to 3 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (smsc_data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), s_eth_din(31-i*8 downto 24-i*8)); end generate; smsc_addr_pad : outpadv generic map (tech => padtech, width => 15) port map (smsc_addr, memo.address(15 downto 1)); smsc_nbe_pad : outpadv generic map (tech => padtech, width => 4) port map (smsc_nbe, s_eth_nbe); smsc_reset_pad : outpad generic map (tech => padtech) port map (smsc_resetn, rstn); smsc_nrd_pad : outpad generic map (tech => padtech) port map (smsc_nrd, s_eth_readn); smsc_nwr_pad : outpad generic map (tech => padtech) port map (smsc_nwr, s_eth_writen); smsc_ncs_pad : outpad generic map (tech => padtech) port map (smsc_ncs, memo.iosn); smsc_aen_pad : outpad generic map (tech => padtech) port map (smsc_aen, s_eth_aen); smsc_lclk_pad : outpad generic map (tech => padtech) port map (smsc_lclk, vcc(0)); smsc_wnr_pad : outpad generic map (tech => padtech) port map (smsc_wnr, vcc(0)); smsc_rdyrtn_pad : outpad generic map (tech => padtech) port map (smsc_rdyrtn, vcc(0)); smsc_cycle_pad : outpad generic map (tech => padtech) port map (smsc_cycle, vcc(0)); smsc_nads_pad : outpad generic map (tech => padtech) port map (smsc_nads, gnd(0)); -- lcd_data_pad : iopadv generic map (width => 8, tech => padtech) -- port map (lcd_data, nuo.lcd_data, nuo.lcd_ben, nui.lcd_data); -- lcd_rs_pad : outpad generic map (tech => padtech) -- port map (lcd_rs, nuo.lcd_rs); -- lcd_rw_pad : outpad generic map (tech => padtech) -- port map (lcd_rw, nuo.lcd_rw ); -- lcd_en_pad : outpad generic map (tech => padtech) -- port map (lcd_en, nuo.lcd_en); -- lcd_backl_pad : outpad generic map (tech => padtech) -- port map (lcd_backl, nuo.lcd_backl); ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- -- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate -- ahbmo(i) <= ahbm_none; -- end generate; -- nap0 : for i in 11 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate; apbo(6) <= apb_none; ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 Demonstration design for Nuhorizon SP3 board", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;
--LIBRARY xtek; -- USE xtek.XHDL_std_logic.all; LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; --***************************************************************************** -- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- --***************************************************************************** -- ____ ____ -- / /\/ / -- /___/ \ / Vendor : Xilinx -- \ \ \/ Version : 3.92 -- \ \ Application : MIG -- / / Filename : ui_top.v -- /___/ /\ Date Last Modified : $date$ -- \ \ / \ Date Created : Tue Jun 30 2009 -- \___\/\___\ -- --Device : Virtex-6 --Design Name : DDR3 SDRAM --Purpose : --Reference : --Revision History : --***************************************************************************** -- Top level of simple user interface. ENTITY ui_top IS GENERIC ( TCQ : INTEGER := 100; APP_DATA_WIDTH : INTEGER := 256; APP_MASK_WIDTH : INTEGER := 32; BANK_WIDTH : INTEGER := 3; COL_WIDTH : INTEGER := 12; CWL : INTEGER := 5; ECC : STRING := "OFF"; ECC_TEST : STRING := "OFF"; ORDERING : STRING := "NORM"; RANKS : INTEGER := 4; RANK_WIDTH : INTEGER := 2; ROW_WIDTH : INTEGER := 16; MEM_ADDR_ORDER : STRING := "BANK_ROW_COLUMN" ); PORT ( -- Outputs -- Inputs -- Beginning of automatic inputs (from unused autoinst inputs) -- To ui_cmd0 of ui_cmd.v -- To ui_cmd0 of ui_cmd.v -- To ui_cmd0 of ui_cmd.v -- To ui_cmd0 of ui_cmd.v -- To ui_cmd0 of ui_cmd.v -- To ui_wr_data0 of ui_wr_data.v -- To ui_cmd0 of ui_cmd.v -- To ui_wr_data0 of ui_wr_data.v -- To ui_wr_data0 of ui_wr_data.v -- To ui_wr_data0 of ui_wr_data.v -- To ui_wr_data0 of ui_wr_data.v -- To ui_cmd0 of ui_cmd.v, ... -- To ui_rd_data0 of ui_rd_data.v -- To ui_rd_data0 of ui_rd_data.v -- To ui_rd_data0 of ui_rd_data.v -- To ui_rd_data0 of ui_rd_data.v -- To ui_rd_data0 of ui_rd_data.v -- To ui_rd_data0 of ui_rd_data.v -- To ui_cmd0 of ui_cmd.v, ... -- To ui_wr_data0 of ui_wr_data.v -- To ui_wr_data0 of ui_wr_data.v -- To ui_wr_data0 of ui_wr_data.v -- End of automatics -- Beginning of automatic outputs (from unused autoinst outputs) -- From ui_rd_data0 of ui_rd_data.v -- From ui_rd_data0 of ui_rd_data.v -- From ui_rd_data0 of ui_rd_data.v -- From ui_rd_data0 of ui_rd_data.v -- From ui_cmd0 of ui_cmd.v -- From ui_wr_data0 of ui_wr_data.v -- From ui_cmd0 of ui_cmd.v -- From ui_cmd0 of ui_cmd.v -- From ui_cmd0 of ui_cmd.v -- From ui_cmd0 of ui_cmd.v -- From ui_cmd0 of ui_cmd.v -- From ui_cmd0 of ui_cmd.v -- From ui_wr_data0 of ui_wr_data.v -- From ui_cmd0 of ui_cmd.v -- From ui_cmd0 of ui_cmd.v -- From ui_cmd0 of ui_cmd.v -- From ui_wr_data0 of ui_wr_data.v wr_data_mask : OUT STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0); -- From ui_wr_data0 of ui_wr_data.v wr_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); use_addr : OUT STD_LOGIC; size : OUT STD_LOGIC; row : OUT STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0); raw_not_ecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); rank : OUT STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0); hi_priority : OUT STD_LOGIC; data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); col : OUT STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0); cmd : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); bank : OUT STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0); app_wdf_rdy : OUT STD_LOGIC; app_rdy : OUT STD_LOGIC; app_rd_data_valid : OUT STD_LOGIC; app_rd_data_end : OUT STD_LOGIC; app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); correct_en : OUT STD_LOGIC; wr_data_offset : IN STD_LOGIC; wr_data_en : IN STD_LOGIC; wr_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rst : IN STD_LOGIC; rd_data_offset : IN STD_LOGIC; rd_data_end : IN STD_LOGIC; rd_data_en : IN STD_LOGIC; rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0); clk : IN STD_LOGIC; app_wdf_wren : IN STD_LOGIC; app_wdf_mask : IN STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0); app_wdf_end : IN STD_LOGIC; app_wdf_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); app_sz : IN STD_LOGIC; app_raw_not_ecc : IN STD_LOGIC_VECTOR(3 DOWNTO 0); app_hi_pri : IN STD_LOGIC; app_en : IN STD_LOGIC; app_cmd : IN STD_LOGIC_VECTOR(2 DOWNTO 0); app_addr : IN STD_LOGIC_VECTOR(RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH - 1 DOWNTO 0); accept_ns : IN STD_LOGIC; accept : IN STD_LOGIC; app_correct_en : IN STD_LOGIC ); END ENTITY ui_top; ARCHITECTURE trans OF ui_top IS constant ADDR_WIDTH :integer := RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH; COMPONENT ui_cmd IS GENERIC ( TCQ : INTEGER := 100; ADDR_WIDTH : INTEGER := 33; BANK_WIDTH : INTEGER := 3; COL_WIDTH : INTEGER := 12; RANK_WIDTH : INTEGER := 2; ROW_WIDTH : INTEGER := 16; RANKS : INTEGER := 4; MEM_ADDR_ORDER : STRING := "BANK_ROW_COLUMN" ); PORT ( app_rdy : OUT STD_LOGIC; use_addr : OUT STD_LOGIC; rank : OUT STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0); bank : OUT STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0); row : OUT STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0); col : OUT STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0); size : OUT STD_LOGIC; cmd : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); hi_priority : OUT STD_LOGIC; rd_accepted : OUT STD_LOGIC; wr_accepted : OUT STD_LOGIC; data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); rst : IN STD_LOGIC; clk : IN STD_LOGIC; accept_ns : IN STD_LOGIC; rd_buf_full : IN STD_LOGIC; wr_req_16 : IN STD_LOGIC; app_addr : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); app_cmd : IN STD_LOGIC_VECTOR(2 DOWNTO 0); app_sz : IN STD_LOGIC; app_hi_pri : IN STD_LOGIC; app_en : IN STD_LOGIC; wr_data_buf_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rd_data_buf_addr_r : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT; COMPONENT ui_wr_data IS GENERIC ( TCQ : INTEGER := 100; APP_DATA_WIDTH : INTEGER := 256; APP_MASK_WIDTH : INTEGER := 32; ECC : STRING := "OFF"; ECC_TEST : STRING := "OFF"; CWL : INTEGER := 5 ); PORT ( app_wdf_rdy : OUT STD_LOGIC; wr_req_16 : OUT STD_LOGIC; wr_data_buf_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); wr_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); wr_data_mask : OUT STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0); raw_not_ecc : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); rst : IN STD_LOGIC; clk : IN STD_LOGIC; app_wdf_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); app_wdf_mask : IN STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0); app_raw_not_ecc : IN STD_LOGIC_VECTOR(3 DOWNTO 0); app_wdf_wren : IN STD_LOGIC; app_wdf_end : IN STD_LOGIC; wr_data_offset : IN STD_LOGIC; wr_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0); wr_data_en : IN STD_LOGIC; wr_accepted : IN STD_LOGIC; ram_init_done_r : IN STD_LOGIC; ram_init_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT; COMPONENT ui_rd_data IS GENERIC ( TCQ : INTEGER := 100; APP_DATA_WIDTH : INTEGER := 256; ECC : STRING := "OFF"; ORDERING : STRING := "NORM" ); PORT ( ram_init_done_r : OUT STD_LOGIC; ram_init_addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); app_rd_data_valid : OUT STD_LOGIC; app_rd_data_end : OUT STD_LOGIC; app_rd_data : OUT STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); app_ecc_multiple_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); rd_buf_full : OUT STD_LOGIC; rd_data_buf_addr_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); rst : IN STD_LOGIC; clk : IN STD_LOGIC; rd_data_en : IN STD_LOGIC; rd_data_addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rd_data_offset : IN STD_LOGIC; rd_data_end : IN STD_LOGIC; rd_data : IN STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); ecc_multiple : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rd_accepted : IN STD_LOGIC ); END COMPONENT; -- End of automatics -- Beginning of automatic wires (for undeclared instantiated-module outputs) SIGNAL ram_init_addr : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_rd_data0 of ui_rd_data.v SIGNAL ram_init_done_r : STD_LOGIC; -- From ui_rd_data0 of ui_rd_data.v SIGNAL rd_accepted : STD_LOGIC; -- From ui_cmd0 of ui_cmd.v SIGNAL rd_buf_full : STD_LOGIC; -- From ui_rd_data0 of ui_rd_data.v SIGNAL rd_data_buf_addr_r : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_rd_data0 of ui_rd_data.v SIGNAL wr_accepted : STD_LOGIC; -- From ui_cmd0 of ui_cmd.v SIGNAL wr_data_buf_addr : STD_LOGIC_VECTOR(3 DOWNTO 0); -- From ui_wr_data0 of ui_wr_data.v SIGNAL wr_req_16 : STD_LOGIC; -- From ui_wr_data0 of ui_wr_data.v -- Declare intermediate signals for referenced outputs SIGNAL wr_data_mask_xhdl17 : STD_LOGIC_VECTOR(APP_MASK_WIDTH - 1 DOWNTO 0); SIGNAL wr_data_xhdl16 : STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); SIGNAL use_addr_xhdl15 : STD_LOGIC; SIGNAL size_xhdl14 : STD_LOGIC; SIGNAL row_xhdl13 : STD_LOGIC_VECTOR(ROW_WIDTH - 1 DOWNTO 0); SIGNAL raw_not_ecc_xhdl12 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL rank_xhdl11 : STD_LOGIC_VECTOR(RANK_WIDTH - 1 DOWNTO 0); SIGNAL hi_priority_xhdl10 : STD_LOGIC; SIGNAL data_buf_addr_xhdl9 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL col_xhdl8 : STD_LOGIC_VECTOR(COL_WIDTH - 1 DOWNTO 0); SIGNAL cmd_xhdl7 : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL bank_xhdl6 : STD_LOGIC_VECTOR(BANK_WIDTH - 1 DOWNTO 0); SIGNAL app_wdf_rdy_xhdl5 : STD_LOGIC; SIGNAL app_rdy_xhdl4 : STD_LOGIC; SIGNAL app_rd_data_valid_xhdl3 : STD_LOGIC; SIGNAL app_rd_data_end_xhdl2 : STD_LOGIC; SIGNAL app_rd_data_xhdl1 : STD_LOGIC_VECTOR(APP_DATA_WIDTH - 1 DOWNTO 0); SIGNAL app_ecc_multiple_err_xhdl0 : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL rst_reg : STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL rst_final : STD_LOGIC; SIGNAL app_addr_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0); ATTRIBUTE max_fanout : STRING; ATTRIBUTE max_fanout OF rst_final : SIGNAL IS "10"; BEGIN -- Drive referenced outputs wr_data_mask <= wr_data_mask_xhdl17; wr_data <= wr_data_xhdl16; use_addr <= use_addr_xhdl15; size <= size_xhdl14; row <= row_xhdl13; raw_not_ecc <= raw_not_ecc_xhdl12; rank <= rank_xhdl11; hi_priority <= hi_priority_xhdl10; data_buf_addr <= data_buf_addr_xhdl9; col <= col_xhdl8; cmd <= cmd_xhdl7; bank <= bank_xhdl6; app_wdf_rdy <= app_wdf_rdy_xhdl5; app_rdy <= app_rdy_xhdl4; app_rd_data_valid <= app_rd_data_valid_xhdl3; app_rd_data_end <= app_rd_data_end_xhdl2; app_rd_data <= app_rd_data_xhdl1; app_ecc_multiple_err <= app_ecc_multiple_err_xhdl0; correct_en <= app_correct_en; -- End of automatics rank_add_correction1: IF ( RANKS > 1 ) GENERATE app_addr_temp <= app_addr; END GENERATE; rank_add_correction2: IF ( RANKS = 1 ) GENERATE app_addr_temp <= ('0' & app_addr ( ADDR_WIDTH - 2 DOWNTO 0)); END GENERATE; -- Parameters PROCESS (clk) BEGIN IF ( clk'EVENT AND clk = '1') THEN rst_reg <= (rst_reg(8 DOWNTO 0) & rst); END IF; END PROCESS; PROCESS (clk) BEGIN IF ( clk'EVENT AND clk = '1') THEN rst_final <= rst_reg(9); END IF; END PROCESS; ui_cmd0 : ui_cmd GENERIC MAP ( TCQ => TCQ, ADDR_WIDTH => ADDR_WIDTH, BANK_WIDTH => BANK_WIDTH, COL_WIDTH => COL_WIDTH, RANK_WIDTH => RANK_WIDTH, ROW_WIDTH => ROW_WIDTH, RANKS => RANKS, MEM_ADDR_ORDER => MEM_ADDR_ORDER ) PORT MAP ( -- Outputs app_rdy => app_rdy_xhdl4, use_addr => use_addr_xhdl15, rank => rank_xhdl11(RANK_WIDTH - 1 DOWNTO 0), bank => bank_xhdl6(BANK_WIDTH - 1 DOWNTO 0), row => row_xhdl13(ROW_WIDTH - 1 DOWNTO 0), col => col_xhdl8(COL_WIDTH - 1 DOWNTO 0), size => size_xhdl14, cmd => cmd_xhdl7(2 DOWNTO 0), hi_priority => hi_priority_xhdl10, rd_accepted => rd_accepted, wr_accepted => wr_accepted, data_buf_addr => data_buf_addr_xhdl9(3 DOWNTO 0), -- Inputs rst => rst_final, clk => clk, accept_ns => accept_ns, rd_buf_full => rd_buf_full, wr_req_16 => wr_req_16, app_addr => app_addr_temp(ADDR_WIDTH - 1 DOWNTO 0), app_cmd => app_cmd(2 DOWNTO 0), app_sz => app_sz, app_hi_pri => app_hi_pri, app_en => app_en, wr_data_buf_addr => wr_data_buf_addr(3 DOWNTO 0), rd_data_buf_addr_r => rd_data_buf_addr_r(3 DOWNTO 0) ); -- Parameters ui_wr_data0 : ui_wr_data GENERIC MAP ( TCQ => TCQ, APP_DATA_WIDTH => APP_DATA_WIDTH, APP_MASK_WIDTH => APP_MASK_WIDTH, ECC => ECC, ECC_TEST => ECC_TEST, CWL => CWL ) PORT MAP ( -- Outputs app_wdf_rdy => app_wdf_rdy_xhdl5, wr_req_16 => wr_req_16, wr_data_buf_addr => wr_data_buf_addr(3 DOWNTO 0), wr_data => wr_data_xhdl16(APP_DATA_WIDTH - 1 DOWNTO 0), wr_data_mask => wr_data_mask_xhdl17(APP_MASK_WIDTH - 1 DOWNTO 0), raw_not_ecc => raw_not_ecc_xhdl12(3 DOWNTO 0), -- Inputs rst => rst_final, clk => clk, app_wdf_data => app_wdf_data(APP_DATA_WIDTH - 1 DOWNTO 0), app_wdf_mask => app_wdf_mask(APP_MASK_WIDTH - 1 DOWNTO 0), app_raw_not_ecc => app_raw_not_ecc(3 DOWNTO 0), app_wdf_wren => app_wdf_wren, app_wdf_end => app_wdf_end, wr_data_offset => wr_data_offset, wr_data_addr => wr_data_addr(3 DOWNTO 0), wr_data_en => wr_data_en, wr_accepted => wr_accepted, ram_init_done_r => ram_init_done_r, ram_init_addr => ram_init_addr(3 DOWNTO 0) ); -- Parameters ui_rd_data0 : ui_rd_data GENERIC MAP ( TCQ => TCQ, APP_DATA_WIDTH => APP_DATA_WIDTH, ECC => ECC, ORDERING => ORDERING ) PORT MAP ( -- Outputs ram_init_done_r => ram_init_done_r, ram_init_addr => ram_init_addr(3 DOWNTO 0), app_rd_data_valid => app_rd_data_valid_xhdl3, app_rd_data_end => app_rd_data_end_xhdl2, app_rd_data => app_rd_data_xhdl1(APP_DATA_WIDTH - 1 DOWNTO 0), app_ecc_multiple_err => app_ecc_multiple_err_xhdl0(3 DOWNTO 0), rd_buf_full => rd_buf_full, rd_data_buf_addr_r => rd_data_buf_addr_r(3 DOWNTO 0), -- Inputs rst => rst_final, clk => clk, rd_data_en => rd_data_en, rd_data_addr => rd_data_addr(3 DOWNTO 0), rd_data_offset => rd_data_offset, rd_data_end => rd_data_end, rd_data => rd_data(APP_DATA_WIDTH - 1 DOWNTO 0), ecc_multiple => ecc_multiple(3 DOWNTO 0), rd_accepted => rd_accepted ); END ARCHITECTURE trans; -- ui_top
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity CLOCK_SINGLE_RUN_SRC is Port ( CLK: in std_logic; -- (System) Takt SINGLE: in std_logic; -- 1: Einzeltakt RUN_R: in std_logic; -- 1: Dauerbetrieb -- mit Eingangsregister RESET: in std_logic; -- 1: Initialzustand soll angenommen werden OUT_NEXT_STATE: out std_logic); -- 1: nächster Zustand end CLOCK_SINGLE_RUN_SRC; architecture Behavioral of CLOCK_SINGLE_RUN_SRC is type TYPE_STATE is (CSR_0, CSR_1, CSR_2); -- Zustände signal SV: TYPE_STATE; --Zustangsvariable signal n_SV: TYPE_STATE; --Zustangsvariable, neuer Wert signal SV_M: TYPE_STATE; --Zustangsvariable, Ausgang Master signal RUN_S: std_logic; signal not_CLK : std_logic; begin NOT_CLK_PROC: process (CLK) begin not_CLK <= not CLK; end process; IREG_PROC: process (RUN_R, not_CLK) begin if (not_CLK'event and not_CLK = '1') then RUN_S <= RUN_R; end if; end process; IL_OL_PROC: process (SINGLE, RUN_S, SV) begin case SV is when CSR_0 => if (SINGLE = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_2; else if (RUN_S = '1') then OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; end if; when CSR_1 => OUT_NEXT_STATE <= '0'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '1'; n_SV <= CSR_1; end if; when CSR_2 => OUT_NEXT_STATE <= '1'; if (SINGLE = '1') then OUT_NEXT_STATE <= '0'; n_SV <= CSR_2; else OUT_NEXT_STATE <= '0'; n_SV <= CSR_0; end if; when others => OUT_NEXT_STATE <= '0'; end case; end process; SREG_M_PROC: process (RESET, n_SV, CLK) -- Master begin if(RESET = '1') then SV_M <= CSR_0; else if (CLK'event and CLK = '1') then SV_M <= n_SV; end if; end if; end process; SREG_S_PROC: process (RESET, SV_M, not_CLK) -- Slave begin if(RESET = '1') then SV <= CSR_0; else if (not_CLK'event and not_CLK = '1') then SV <= SV_M; end if; end if; end process; end Behavioral;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PS2KEYBOARD is port ( CLK : in std_logic; RST : in std_logic; PS2_KBCLK, PS2_KBDAT : in std_logic; KEYCODE : out std_logic_vector(7 downto 0); CODE_ENABLE : out std_logic ); end PS2KEYBOARD; architecture RTL of PS2KEYBOARD is type STATE_SET is (START_BIT, DATA0, DATA1, DATA2, DATA3, DATA4, DATA5, DATA6, DATA7, PARITY_BIT, STOP_BIT); signal PS2CLK : std_logic_vector(1 downto 0); signal KEYCODE_BUF : std_logic_vector(7 downto 0); signal STATE : STATE_SET; signal PARITY : std_logic; begin KEYCODE <= KEYCODE_BUF; PARITY <= KEYCODE_BUF(0) xor KEYCODE_BUF(1) xor KEYCODE_BUF(2) xor KEYCODE_BUF(3) xor KEYCODE_BUF(4) xor KEYCODE_BUF(5) xor KEYCODE_BUF(6) xor KEYCODE_BUF(7) xor '1'; process (CLK, RST) begin if (RST = '0') then PS2CLK <= "00"; STATE <= START_BIT; KEYCODE_BUF <= (others => '0'); CODE_ENABLE <= '0'; elsif (CLK'event and CLK = '1') then PS2CLK <= PS2CLK(0) & PS2_KBCLK; if (PS2CLK = "10") then case STATE is when START_BIT => if (PS2_KBDAT = '0') then STATE <= DATA0; CODE_ENABLE <= '0'; else STATE <= START_BIT; end if; when DATA0 => STATE <= DATA1; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when DATA1 => STATE <= DATA2; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when DATA2 => STATE <= DATA3; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when DATA3 => STATE <= DATA4; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when DATA4 => STATE <= DATA5; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when DATA5 => STATE <= DATA6; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when DATA6 => STATE <= DATA7; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when DATA7 => STATE <= PARITY_BIT; KEYCODE_BUF <= PS2_KBDAT & KEYCODE_BUF(7 downto 1); when PARITY_BIT => if (PS2_KBDAT = PARITY) then STATE <= STOP_BIT; else STATE <= START_BIT; end if; when STOP_BIT => if (PS2_KBDAT = '1') then STATE <= START_BIT; CODE_ENABLE <= '1'; else STATE <= START_BIT; end if; end case; end if; end if; end process; end RTL;
-- NEED RESULT: ENT00703: Open composite buffer ports with static subtypes passed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00703 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (3) -- -- DESIGN UNIT ORDERING: -- -- ENT00703(ARCH00703) -- ENT00703_Test_Bench(ARCH00703_Test_Bench) -- -- REVISION HISTORY: -- -- 25-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00703 is port ( toggle : buffer switch ; i_st_rec1_1, i_st_rec1_2 : buffer st_rec1 := c_st_rec1_1 ; i_st_rec2_1, i_st_rec2_2 : buffer st_rec2 := c_st_rec2_1 ; i_st_rec3_1, i_st_rec3_2 : buffer st_rec3 := c_st_rec3_1 ; i_st_arr1_1, i_st_arr1_2 : buffer st_arr1 := c_st_arr1_1 ; i_st_arr2_1, i_st_arr2_2 : buffer st_arr2 := c_st_arr2_1 ; i_st_arr3_1, i_st_arr3_2 : buffer st_arr3 := c_st_arr3_1 ) ; begin end ENT00703 ; -- architecture ARCH00703 of ENT00703 is begin process variable correct : boolean := true ; begin -- toggle <= up ; i_st_rec1_1 <= c_st_rec1_2 ; i_st_rec1_2 <= c_st_rec1_2 ; i_st_rec2_1 <= c_st_rec2_2 ; i_st_rec2_2 <= c_st_rec2_2 ; i_st_rec3_1 <= c_st_rec3_2 ; i_st_rec3_2 <= c_st_rec3_2 ; i_st_arr1_1 <= c_st_arr1_2 ; i_st_arr1_2 <= c_st_arr1_2 ; i_st_arr2_1 <= c_st_arr2_2 ; i_st_arr2_2 <= c_st_arr2_2 ; i_st_arr3_1 <= c_st_arr3_2 ; i_st_arr3_2 <= c_st_arr3_2 ; test_report ( "ENT00703" , "Open composite buffer ports with static subtypes" , correct) ; wait ; end process ; end ARCH00703 ; -- use WORK.STANDARD_TYPES.all ; entity ENT00703_Test_Bench is end ENT00703_Test_Bench ; -- architecture ARCH00703_Test_Bench of ENT00703_Test_Bench is begin L1: block -- signal toggle : switch ; -- component UUT end component ; -- for CIS1 : UUT use entity WORK.ENT00703 ( ARCH00703 ) port map ( toggle , open, open, open, open, open, open, open, open, open, open, open, open ) ; -- begin CIS1 : UUT ; end block L1 ; end ARCH00703_Test_Bench ;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --library synplify; --use synplify.attributes.all; entity disdram is generic( depth: integer; Dwidth: integer; Awidth: integer ); port( A: IN std_logic_VECTOR(Awidth-1 downto 0); CLK: IN std_logic; D: IN std_logic_VECTOR(Dwidth-1 downto 0); WE: IN std_logic; DPRA: IN std_logic_VECTOR(Awidth-1 downto 0); DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0); QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0) ); end disdram; architecture arch_disdram of disdram is type ram_memtype is array (depth-1 downto 0) of std_logic_vector (Dwidth-1 downto 0); signal mem : ram_memtype := (others => (others => '0')); -- attribute syn_ramstyle of mem : signal is "select_ram"; begin wr: process( clk ) begin if rising_edge(clk) then if WE = '1' then mem(conv_integer(A)) <= D; end if; end if; end process wr; DPO <= mem(conv_integer(DPRA)); rd : process(clk) begin if rising_edge(clk) then QDPO <= mem(conv_integer(DPRA)); end if; end process; end arch_disdram;
library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; entity bbsse_jed is port( clock: in std_logic; input: in std_logic_vector(6 downto 0); output: out std_logic_vector(6 downto 0) ); end bbsse_jed; architecture behaviour of bbsse_jed is constant st0: std_logic_vector(3 downto 0) := "0010"; constant st1: std_logic_vector(3 downto 0) := "0011"; constant st11: std_logic_vector(3 downto 0) := "1011"; constant st4: std_logic_vector(3 downto 0) := "1001"; constant st2: std_logic_vector(3 downto 0) := "0001"; constant st3: std_logic_vector(3 downto 0) := "0000"; constant st5: std_logic_vector(3 downto 0) := "1000"; constant st6: std_logic_vector(3 downto 0) := "1111"; constant st7: std_logic_vector(3 downto 0) := "1110"; constant st8: std_logic_vector(3 downto 0) := "1101"; constant st9: std_logic_vector(3 downto 0) := "0101"; constant st10: std_logic_vector(3 downto 0) := "0111"; constant st12: std_logic_vector(3 downto 0) := "1010"; constant st13: std_logic_vector(3 downto 0) := "1100"; constant st14: std_logic_vector(3 downto 0) := "0100"; constant st15: std_logic_vector(3 downto 0) := "0110"; signal current_state, next_state: std_logic_vector(3 downto 0); begin process(clock) begin if rising_edge(clock) then current_state <= next_state; end if; end process; process(input, current_state) begin next_state <= "----"; output <= "-------"; case current_state is when st0 => if std_match(input, "0------") then next_state <= st0; output <= "0000000"; elsif std_match(input, "10----0") then next_state <= st1; output <= "00110-0"; elsif std_match(input, "10----1") then next_state <= st1; output <= "00010-0"; elsif std_match(input, "11----0") then next_state <= st11; output <= "0011010"; elsif std_match(input, "11----1") then next_state <= st11; output <= "0001010"; end if; when st1 => if std_match(input, "100----") then next_state <= st1; output <= "00000-0"; elsif std_match(input, "101-1--") then next_state <= st4; output <= "10000-0"; elsif std_match(input, "101-0--") then next_state <= st2; output <= "10000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st2 => if std_match(input, "10-----") then next_state <= st3; output <= "00000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st3 => if std_match(input, "10--0--") then next_state <= st2; output <= "10000-0"; elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st4 => if std_match(input, "10-----") then next_state <= st5; output <= "00000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st5 => if std_match(input, "10-1---") then next_state <= st4; output <= "10000-0"; elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0"; elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st6 => if std_match(input, "10---0-") then next_state <= st6; output <= "0100000"; elsif std_match(input, "10---1-") then next_state <= st7; output <= "01000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st7 => if std_match(input, "10-----") then next_state <= st8; output <= "0000010"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st8 => if std_match(input, "10---0-") then next_state <= st8; output <= "0000000"; elsif std_match(input, "10---1-") then next_state <= st9; output <= "10000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st9 => if std_match(input, "10-----") then next_state <= st10; output <= "00000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st10 => if std_match(input, "1001---") then next_state <= st10; output <= "00000-0"; elsif std_match(input, "10-01--") then next_state <= st1; output <= "00010-0"; elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010"; elsif std_match(input, "1011---") then next_state <= st9; output <= "10000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010"; end if; when st11 => if std_match(input, "0----0-") then next_state <= st11; output <= "000--00"; elsif std_match(input, "11---0-") then next_state <= st11; output <= "0000000"; elsif std_match(input, "0----1-") then next_state <= st0; output <= "000---1"; elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0"; elsif std_match(input, "11---1-") then next_state <= st12; output <= "00001-0"; end if; when st12 => if std_match(input, "11-----") then next_state <= st12; output <= "00001-0"; elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0"; elsif std_match(input, "0------") then next_state <= st11; output <= "000--10"; end if; when st13 => if std_match(input, "0------") then next_state <= st11; output <= "000--10"; end if; when st14 => if std_match(input, "0------") then next_state <= st11; output <= "000--10"; end if; when st15 => if std_match(input, "0------") then next_state <= st11; output <= "000--10"; end if; when others => next_state <= "----"; output <= "-------"; end case; end process; end behaviour;
library verilog; use verilog.vl_types.all; entity full_adder_vlg_vec_tst is end full_adder_vlg_vec_tst;
-- Copyright (C) 2016 by Spallina Ind. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sedici_bit is port ( din : in std_logic_vector(15 downto 0); start, clk : in std_logic; res : out std_logic_vector(15 downto 0); fine : out std_logic ); end sedici_bit; architecture beh of sedici_bit is type stati is (idle, getOP, getD0, getD1, exe1, exe2, exe4); signal st : stati; signal OP : std_logic_vector(1 downto 0); signal counter : integer range 3 downto 0; signal D0, D1 : std_logic_vector(15 downto 0); signal enOP, enD0, enD1, enEXE1, enEXE2, enexe4 : std_logic; function next_state (st : stati; start : std_logic; op : std_logic_vector(1 downto 0); counter : integer range 3 downto 0) return stati is variable nxt : stati; begin case st is when idle => if start = '1' then nxt := getOP; else nxt := idle; end if; when getOP => nxt := getD0; when getD0 => if op = "00" then nxt := exe1; else nxt := getD1; end if; when getD1 => case op is when "01" => nxt := exe1; when "10" => nxt := exe2; when "11" => nxt := exe4; when others => nxt := idle; end case; when exe1 => nxt := idle; when exe2 => if counter = 1 then nxt := idle; else nxt := exe2; end if; when exe4 => if counter = 3 then nxt := idle; else nxt := exe4; end if; when others => nxt := idle; end case; return nxt; end next_state; begin -- cu process (clk) begin if clk'event and clk = '0' then st <= next_state(st, start, op, counter); end if; end process; enOP <= '1' when st = getOP else '0'; enD0 <= '1' when st = getD0 else '0'; enD1 <= '1' when st = getD1 else '0'; enEXE1 <= '1' when st = exe1 else '0'; enEXE2 <= '1' when st = exe2 else '0'; enEXE4 <= '1' when st = exe4 else '0'; -- datapath process (clk) begin if clk'event and clk = '0' then if enOP = '1' then op <= din(1 downto 0); counter <= 0; end if; if enD0 = '1' then D0 <= din; end if; if enD1 = '1' then D1 <= din; end if; if enEXE1 = '1' then if op = "00" then -- NOT res <= not D0; else res <= D0 or D1; -- OR end if; end if; if enEXE2 = '1' then -- ADD if counter = 1 then res <= D0 + D1; else counter <= counter + 1; end if; end if; if enEXE4 = '1' then -- MAC if counter = 3 then res <= D0+(D1(15 downto 8)*D1(7 downto 0)); else counter <= counter + 1; end if; end if; if enEXE1 = '1' or (enEXE2 = '1' and counter = 1) or (enEXE4 = '1' and counter = 3) then fine <= '1'; else fine <= '0'; end if; end if; end process; end beh;
-- Copyright (C) 2016 by Spallina Ind. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sedici_bit is port ( din : in std_logic_vector(15 downto 0); start, clk : in std_logic; res : out std_logic_vector(15 downto 0); fine : out std_logic ); end sedici_bit; architecture beh of sedici_bit is type stati is (idle, getOP, getD0, getD1, exe1, exe2, exe4); signal st : stati; signal OP : std_logic_vector(1 downto 0); signal counter : integer range 3 downto 0; signal D0, D1 : std_logic_vector(15 downto 0); signal enOP, enD0, enD1, enEXE1, enEXE2, enexe4 : std_logic; function next_state (st : stati; start : std_logic; op : std_logic_vector(1 downto 0); counter : integer range 3 downto 0) return stati is variable nxt : stati; begin case st is when idle => if start = '1' then nxt := getOP; else nxt := idle; end if; when getOP => nxt := getD0; when getD0 => if op = "00" then nxt := exe1; else nxt := getD1; end if; when getD1 => case op is when "01" => nxt := exe1; when "10" => nxt := exe2; when "11" => nxt := exe4; when others => nxt := idle; end case; when exe1 => nxt := idle; when exe2 => if counter = 1 then nxt := idle; else nxt := exe2; end if; when exe4 => if counter = 3 then nxt := idle; else nxt := exe4; end if; when others => nxt := idle; end case; return nxt; end next_state; begin -- cu process (clk) begin if clk'event and clk = '0' then st <= next_state(st, start, op, counter); end if; end process; enOP <= '1' when st = getOP else '0'; enD0 <= '1' when st = getD0 else '0'; enD1 <= '1' when st = getD1 else '0'; enEXE1 <= '1' when st = exe1 else '0'; enEXE2 <= '1' when st = exe2 else '0'; enEXE4 <= '1' when st = exe4 else '0'; -- datapath process (clk) begin if clk'event and clk = '0' then if enOP = '1' then op <= din(1 downto 0); counter <= 0; end if; if enD0 = '1' then D0 <= din; end if; if enD1 = '1' then D1 <= din; end if; if enEXE1 = '1' then if op = "00" then -- NOT res <= not D0; else res <= D0 or D1; -- OR end if; end if; if enEXE2 = '1' then -- ADD if counter = 1 then res <= D0 + D1; else counter <= counter + 1; end if; end if; if enEXE4 = '1' then -- MAC if counter = 3 then res <= D0+(D1(15 downto 8)*D1(7 downto 0)); else counter <= counter + 1; end if; end if; if enEXE1 = '1' or (enEXE2 = '1' and counter = 1) or (enEXE4 = '1' and counter = 3) then fine <= '1'; else fine <= '0'; end if; end if; end process; end beh;
-- megafunction wizard: %LPM_COMPARE% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_COMPARE -- ============================================================ -- File Name: lpm_compare4.vhd -- Megafunction Name(s): -- LPM_COMPARE -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 13.1.0 Build 162 10/23/2013 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_compare4 IS PORT ( dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0); ageb : OUT STD_LOGIC ); END lpm_compare4; ARCHITECTURE SYN OF lpm_compare4 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0); COMPONENT lpm_compare GENERIC ( lpm_hint : STRING; lpm_representation : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( ageb : OUT STD_LOGIC ; dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire1_bv(8 DOWNTO 0) <= "000001100"; sub_wire1 <= To_stdlogicvector(sub_wire1_bv); ageb <= sub_wire0; LPM_COMPARE_component : LPM_COMPARE GENERIC MAP ( lpm_hint => "ONE_INPUT_IS_CONSTANT=YES", lpm_representation => "UNSIGNED", lpm_type => "LPM_COMPARE", lpm_width => 9 ) PORT MAP ( dataa => dataa, datab => sub_wire1, ageb => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: AeqB NUMERIC "0" -- Retrieval info: PRIVATE: AgeB NUMERIC "1" -- Retrieval info: PRIVATE: AgtB NUMERIC "0" -- Retrieval info: PRIVATE: AleB NUMERIC "0" -- Retrieval info: PRIVATE: AltB NUMERIC "0" -- Retrieval info: PRIVATE: AneB NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" -- Retrieval info: PRIVATE: Latency NUMERIC "0" -- Retrieval info: PRIVATE: PortBValue NUMERIC "12" -- Retrieval info: PRIVATE: Radix NUMERIC "10" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SignedCompare NUMERIC "0" -- Retrieval info: PRIVATE: aclr NUMERIC "0" -- Retrieval info: PRIVATE: clken NUMERIC "0" -- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1" -- Retrieval info: PRIVATE: nBit NUMERIC "9" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES" -- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9" -- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb" -- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]" -- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0 -- Retrieval info: CONNECT: @datab 0 0 9 0 12 0 0 9 0 -- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
-- megafunction wizard: %LPM_COMPARE% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: LPM_COMPARE -- ============================================================ -- File Name: lpm_compare4.vhd -- Megafunction Name(s): -- LPM_COMPARE -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 13.1.0 Build 162 10/23/2013 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2013 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_compare4 IS PORT ( dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0); ageb : OUT STD_LOGIC ); END lpm_compare4; ARCHITECTURE SYN OF lpm_compare4 IS SIGNAL sub_wire0 : STD_LOGIC ; SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0); COMPONENT lpm_compare GENERIC ( lpm_hint : STRING; lpm_representation : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( ageb : OUT STD_LOGIC ; dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire1_bv(8 DOWNTO 0) <= "000001100"; sub_wire1 <= To_stdlogicvector(sub_wire1_bv); ageb <= sub_wire0; LPM_COMPARE_component : LPM_COMPARE GENERIC MAP ( lpm_hint => "ONE_INPUT_IS_CONSTANT=YES", lpm_representation => "UNSIGNED", lpm_type => "LPM_COMPARE", lpm_width => 9 ) PORT MAP ( dataa => dataa, datab => sub_wire1, ageb => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: AeqB NUMERIC "0" -- Retrieval info: PRIVATE: AgeB NUMERIC "1" -- Retrieval info: PRIVATE: AgtB NUMERIC "0" -- Retrieval info: PRIVATE: AleB NUMERIC "0" -- Retrieval info: PRIVATE: AltB NUMERIC "0" -- Retrieval info: PRIVATE: AneB NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" -- Retrieval info: PRIVATE: Latency NUMERIC "0" -- Retrieval info: PRIVATE: PortBValue NUMERIC "12" -- Retrieval info: PRIVATE: Radix NUMERIC "10" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SignedCompare NUMERIC "0" -- Retrieval info: PRIVATE: aclr NUMERIC "0" -- Retrieval info: PRIVATE: clken NUMERIC "0" -- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1" -- Retrieval info: PRIVATE: nBit NUMERIC "9" -- Retrieval info: PRIVATE: new_diagram STRING "1" -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES" -- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9" -- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb" -- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]" -- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0 -- Retrieval info: CONNECT: @datab 0 0 9 0 12 0 0 9 0 -- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare4_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm
-- Copyright (C) 1991-2011 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. -- Quartus II 11.0 Build 157 04/27/2011 LIBRARY IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Timing.all; use work.stratixiii_atom_pack.all; package stratixiii_components is -- -- stratixiii_jtag -- COMPONENT stratixiii_jtag generic ( lpm_type : string := "stratixiii_jtag" ); port ( tms : in std_logic := '0'; tck : in std_logic := '0'; tdi : in std_logic := '0'; ntrst : in std_logic := '0'; tdoutap : in std_logic := '0'; tdouser : in std_logic := '0'; tdo: out std_logic; tmsutap: out std_logic; tckutap: out std_logic; tdiutap: out std_logic; shiftuser: out std_logic; clkdruser: out std_logic; updateuser: out std_logic; runidleuser: out std_logic; usr1user: out std_logic ); END COMPONENT; -- -- stratixiii_crcblock -- COMPONENT stratixiii_crcblock generic ( oscillator_divider : integer := 1; crc_deld_disable : string := "off"; error_delay : integer := 0 ; error_dra_dl_bypass : string := "off"; lpm_type : string := "stratixiii_crcblock" ); port ( clk : in std_logic := '0'; shiftnld : in std_logic := '0'; crcerror : out std_logic; regout : out std_logic ); END COMPONENT; -- -- stratixiii_lcell_comb -- COMPONENT stratixiii_lcell_comb generic ( lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1'); shared_arith : string := "off"; extended_lut : string := "off"; dont_touch : string := "off"; lpm_type : string := "stratixiii_lcell_comb"; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*"; tpd_dataa_combout : VitalDelayType01 := DefPropDelay01; tpd_datab_combout : VitalDelayType01 := DefPropDelay01; tpd_datac_combout : VitalDelayType01 := DefPropDelay01; tpd_datad_combout : VitalDelayType01 := DefPropDelay01; tpd_datae_combout : VitalDelayType01 := DefPropDelay01; tpd_dataf_combout : VitalDelayType01 := DefPropDelay01; tpd_datag_combout : VitalDelayType01 := DefPropDelay01; tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01; tpd_datab_sumout : VitalDelayType01 := DefPropDelay01; tpd_datac_sumout : VitalDelayType01 := DefPropDelay01; tpd_datad_sumout : VitalDelayType01 := DefPropDelay01; tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01; tpd_cin_sumout : VitalDelayType01 := DefPropDelay01; tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01; tpd_dataa_cout : VitalDelayType01 := DefPropDelay01; tpd_datab_cout : VitalDelayType01 := DefPropDelay01; tpd_datac_cout : VitalDelayType01 := DefPropDelay01; tpd_datad_cout : VitalDelayType01 := DefPropDelay01; tpd_dataf_cout : VitalDelayType01 := DefPropDelay01; tpd_cin_cout : VitalDelayType01 := DefPropDelay01; tpd_sharein_cout : VitalDelayType01 := DefPropDelay01; tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01; tpd_datab_shareout : VitalDelayType01 := DefPropDelay01; tpd_datac_shareout : VitalDelayType01 := DefPropDelay01; tpd_datad_shareout : VitalDelayType01 := DefPropDelay01; tipd_dataa : VitalDelayType01 := DefPropDelay01; tipd_datab : VitalDelayType01 := DefPropDelay01; tipd_datac : VitalDelayType01 := DefPropDelay01; tipd_datad : VitalDelayType01 := DefPropDelay01; tipd_datae : VitalDelayType01 := DefPropDelay01; tipd_dataf : VitalDelayType01 := DefPropDelay01; tipd_datag : VitalDelayType01 := DefPropDelay01; tipd_cin : VitalDelayType01 := DefPropDelay01; tipd_sharein : VitalDelayType01 := DefPropDelay01 ); port ( dataa : in std_logic := '0'; datab : in std_logic := '0'; datac : in std_logic := '0'; datad : in std_logic := '0'; datae : in std_logic := '0'; dataf : in std_logic := '0'; datag : in std_logic := '0'; cin : in std_logic := '0'; sharein : in std_logic := '0'; combout : out std_logic; sumout : out std_logic; cout : out std_logic; shareout : out std_logic ); END COMPONENT; -- -- stratixiii_routing_wire -- COMPONENT stratixiii_routing_wire generic ( MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01; tipd_datain : VitalDelayType01 := DefPropDelay01 ); PORT ( datain : in std_logic; dataout : out std_logic ); END COMPONENT; -- -- stratixiii_lvds_transmitter -- COMPONENT stratixiii_lvds_transmitter GENERIC ( channel_width : integer := 10; bypass_serializer : String := "false"; invert_clock : String := "false"; use_falling_clock_edge : String := "false"; use_serial_data_input : String := "false"; use_post_dpa_serial_data_input : String := "false"; is_used_as_outclk : String := "false"; tx_output_path_delay_engineering_bits : Integer := -1; enable_dpaclk_to_lvdsout : string := "off"; preemphasis_setting : integer := 0; vod_setting : integer := 0; differential_drive : integer := 0; lpm_type : string := "stratixiii_lvds_transmitter"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01; tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01; tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01; tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01; tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01; tipd_clk0 : VitalDelayType01 := DefpropDelay01; tipd_enable0 : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01); tipd_serialdatain : VitalDelayType01 := DefpropDelay01; tipd_dpaclkin : VitalDelayType01 := DefpropDelay01; tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01 ); PORT ( clk0 : in std_logic; enable0 : in std_logic := '0'; datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0'); serialdatain : in std_logic := '0'; postdpaserialdatain : in std_logic := '0'; dpaclkin : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; dataout : out std_logic; serialfdbkout : out std_logic ); END COMPONENT; -- -- stratixiii_rublock -- COMPONENT stratixiii_rublock generic ( sim_init_config : string := "factory"; sim_init_watchdog_value : integer := 0; sim_init_status : integer := 0; lpm_type : string := "stratixiii_rublock" ); port ( clk : in std_logic; shiftnld : in std_logic; captnupdt : in std_logic; regin : in std_logic; rsttimer : in std_logic; rconfig : in std_logic; regout : out std_logic ); END COMPONENT; -- -- stratixiii_ram_block -- COMPONENT stratixiii_ram_block GENERIC ( operation_mode : STRING := "single_port"; mixed_port_feed_through_mode : STRING := "dont_care"; ram_block_type : STRING := "auto"; logical_ram_name : STRING := "ram_name"; init_file : STRING := "init_file.hex"; init_file_layout : STRING := "none"; enable_ecc : STRING := "false"; width_eccstatus : INTEGER := 3; data_interleave_width_in_bits : INTEGER := 1; data_interleave_offset_in_bits : INTEGER := 1; port_a_logical_ram_depth : INTEGER := 0; port_a_logical_ram_width : INTEGER := 0; port_a_first_address : INTEGER := 0; port_a_last_address : INTEGER := 0; port_a_first_bit_number : INTEGER := 0; port_a_address_clear : STRING := "none"; port_a_data_out_clear : STRING := "none"; port_a_data_in_clock : STRING := "clock0"; port_a_address_clock : STRING := "clock0"; port_a_write_enable_clock : STRING := "clock0"; port_a_read_enable_clock : STRING := "clock0"; port_a_byte_enable_clock : STRING := "clock0"; port_a_data_out_clock : STRING := "none"; port_a_data_width : INTEGER := 1; port_a_address_width : INTEGER := 1; port_a_byte_enable_mask_width : INTEGER := 1; port_b_logical_ram_depth : INTEGER := 0; port_b_logical_ram_width : INTEGER := 0; port_b_first_address : INTEGER := 0; port_b_last_address : INTEGER := 0; port_b_first_bit_number : INTEGER := 0; port_b_address_clear : STRING := "none"; port_b_data_out_clear : STRING := "none"; port_b_data_in_clock : STRING := "clock1"; port_b_address_clock : STRING := "clock1"; port_b_write_enable_clock: STRING := "clock1"; port_b_read_enable_clock: STRING := "clock1"; port_b_byte_enable_clock : STRING := "clock1"; port_b_data_out_clock : STRING := "none"; port_b_data_width : INTEGER := 1; port_b_address_width : INTEGER := 1; port_b_byte_enable_mask_width : INTEGER := 1; port_a_read_during_write_mode : STRING := "new_data_no_nbe_read"; port_b_read_during_write_mode : STRING := "new_data_no_nbe_read"; power_up_uninitialized : STRING := "false"; port_b_byte_size : INTEGER := 0; port_a_byte_size : INTEGER := 0; lpm_type : string := "stratixiii_ram_block"; lpm_hint : string := "true"; clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none clk0_output_clock_enable : STRING := "none"; -- ena0,none clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none clk1_output_clock_enable : STRING := "none"; -- ena1,none clock_duty_cycle_dependence : STRING := "Auto"; mem_init0 : BIT_VECTOR := X"0"; mem_init1 : BIT_VECTOR := X"0"; mem_init2 : BIT_VECTOR := X"0"; mem_init3 : BIT_VECTOR := X"0"; mem_init4 : BIT_VECTOR := X"0"; mem_init5 : BIT_VECTOR := X"0"; mem_init6 : BIT_VECTOR := X"0"; mem_init7 : BIT_VECTOR := X"0"; mem_init8 : BIT_VECTOR := X"0"; mem_init9 : BIT_VECTOR := X"0"; mem_init10 : BIT_VECTOR := X"0"; mem_init11 : BIT_VECTOR := X"0"; mem_init12 : BIT_VECTOR := X"0"; mem_init13 : BIT_VECTOR := X"0"; mem_init14 : BIT_VECTOR := X"0"; mem_init15 : BIT_VECTOR := X"0"; mem_init16 : BIT_VECTOR := X"0"; mem_init17 : BIT_VECTOR := X"0"; mem_init18 : BIT_VECTOR := X"0"; mem_init19 : BIT_VECTOR := X"0"; mem_init20 : BIT_VECTOR := X"0"; mem_init21 : BIT_VECTOR := X"0"; mem_init22 : BIT_VECTOR := X"0"; mem_init23 : BIT_VECTOR := X"0"; mem_init24 : BIT_VECTOR := X"0"; mem_init25 : BIT_VECTOR := X"0"; mem_init26 : BIT_VECTOR := X"0"; mem_init27 : BIT_VECTOR := X"0"; mem_init28 : BIT_VECTOR := X"0"; mem_init29 : BIT_VECTOR := X"0"; mem_init30 : BIT_VECTOR := X"0"; mem_init31 : BIT_VECTOR := X"0"; mem_init32 : BIT_VECTOR := X"0"; mem_init33 : BIT_VECTOR := X"0"; mem_init34 : BIT_VECTOR := X"0"; mem_init35 : BIT_VECTOR := X"0"; mem_init36 : BIT_VECTOR := X"0"; mem_init37 : BIT_VECTOR := X"0"; mem_init38 : BIT_VECTOR := X"0"; mem_init39 : BIT_VECTOR := X"0"; mem_init40 : BIT_VECTOR := X"0"; mem_init41 : BIT_VECTOR := X"0"; mem_init42 : BIT_VECTOR := X"0"; mem_init43 : BIT_VECTOR := X"0"; mem_init44 : BIT_VECTOR := X"0"; mem_init45 : BIT_VECTOR := X"0"; mem_init46 : BIT_VECTOR := X"0"; mem_init47 : BIT_VECTOR := X"0"; mem_init48 : BIT_VECTOR := X"0"; mem_init49 : BIT_VECTOR := X"0"; mem_init50 : BIT_VECTOR := X"0"; mem_init51 : BIT_VECTOR := X"0"; mem_init52 : BIT_VECTOR := X"0"; mem_init53 : BIT_VECTOR := X"0"; mem_init54 : BIT_VECTOR := X"0"; mem_init55 : BIT_VECTOR := X"0"; mem_init56 : BIT_VECTOR := X"0"; mem_init57 : BIT_VECTOR := X"0"; mem_init58 : BIT_VECTOR := X"0"; mem_init59 : BIT_VECTOR := X"0"; mem_init60 : BIT_VECTOR := X"0"; mem_init61 : BIT_VECTOR := X"0"; mem_init62 : BIT_VECTOR := X"0"; mem_init63 : BIT_VECTOR := X"0"; mem_init64 : BIT_VECTOR := X"0"; mem_init65 : BIT_VECTOR := X"0"; mem_init66 : BIT_VECTOR := X"0"; mem_init67 : BIT_VECTOR := X"0"; mem_init68 : BIT_VECTOR := X"0"; mem_init69 : BIT_VECTOR := X"0"; mem_init70 : BIT_VECTOR := X"0"; mem_init71 : BIT_VECTOR := X"0"; connectivity_checking : string := "off" ); PORT ( portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0'); portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0'); portawe : IN STD_LOGIC := '0'; portare : IN STD_LOGIC := '1'; portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0'); portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0'); portbwe : IN STD_LOGIC := '0'; portbre : IN STD_LOGIC := '1'; clk0 : IN STD_LOGIC := '0'; clk1 : IN STD_LOGIC := '0'; ena0 : IN STD_LOGIC := '1'; ena1 : IN STD_LOGIC := '1'; ena2 : IN STD_LOGIC := '1'; ena3 : IN STD_LOGIC := '1'; clr0 : IN STD_LOGIC := '0'; clr1 : IN STD_LOGIC := '0'; portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); devclrn : IN STD_LOGIC := '1'; devpor : IN STD_LOGIC := '1'; portaaddrstall : IN STD_LOGIC := '0'; portbaddrstall : IN STD_LOGIC := '0'; eccstatus : OUT STD_LOGIC_VECTOR(width_eccstatus - 1 DOWNTO 0) := (OTHERS => '0'); dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000"; portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0); portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) ); END COMPONENT; -- -- stratixiii_ff -- COMPONENT stratixiii_ff generic ( power_up : string := "low"; x_on_violation : string := "on"; lpm_type : string := "stratixiii_ff"; tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01; tpd_asdata_q: VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_d : VitalDelayType01 := DefPropDelay01; tipd_asdata : VitalDelayType01 := DefPropDelay01; tipd_sclr : VitalDelayType01 := DefPropDelay01; tipd_sload : VitalDelayType01 := DefPropDelay01; tipd_clrn : VitalDelayType01 := DefPropDelay01; tipd_aload : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; TimingChecksOn: Boolean := True; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks; InstancePath: STRING := "*" ); port ( d : in std_logic := '0'; clk : in std_logic := '0'; clrn : in std_logic := '1'; aload : in std_logic := '0'; sclr : in std_logic := '0'; sload : in std_logic := '0'; ena : in std_logic := '1'; asdata : in std_logic := '0'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; q : out std_logic ); END COMPONENT; -- -- stratixiii_clkselect -- COMPONENT stratixiii_clkselect generic ( lpm_type : STRING := "stratixiii_clkselect"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : STRING := "*"; tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01) ); port ( inclk : in std_logic_vector(3 downto 0) := "0000"; clkselect : in std_logic_vector(1 downto 0) := "00"; outclk : out std_logic ); END COMPONENT; -- -- stratixiii_clkena -- COMPONENT stratixiii_clkena generic ( clock_type : STRING := "Auto"; lpm_type : STRING := "stratixiii_clkena"; ena_register_mode : STRING := "Falling Edge"; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : STRING := "*"; tipd_inclk : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01 ); port ( inclk : in std_logic := '0'; ena : in std_logic := '1'; devclrn : in std_logic := '1'; devpor : in std_logic := '1'; enaout : out std_logic; outclk : out std_logic ); END COMPONENT; -- -- stratixiii_mlab_cell -- COMPONENT stratixiii_mlab_cell GENERIC ( logical_ram_name : STRING := "lutram"; init_file : STRING := "UNUSED"; data_interleave_offset_in_bits : INTEGER := 1; logical_ram_depth : INTEGER := 0; logical_ram_width : INTEGER := 0; first_address : INTEGER := 0; last_address : INTEGER := 0; first_bit_number : INTEGER := 0; data_width : INTEGER := 1; address_width : INTEGER := 1; byte_enable_mask_width : INTEGER := 1; byte_size : INTEGER := 1; lpm_type : string := "stratixiii_mlab_cell"; lpm_hint : string := "true"; mixed_port_feed_through_mode : string := "dont_care"; mem_init0 : BIT_VECTOR := X"0"; tipd_clk0 : VitalDelayType01 := DefPropDelay01; tipd_ena0 : VitalDelayType01 := DefPropDelay01; tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01); tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst; tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst; tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01 ); PORT ( portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0'); portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0'); portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1'); portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0'); clk0 : IN STD_LOGIC := '0'; ena0 : IN STD_LOGIC := '1'; portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) ); END COMPONENT; -- -- stratixiii_io_ibuf -- COMPONENT stratixiii_io_ibuf GENERIC ( tipd_i : VitalDelayType01 := DefPropDelay01; tipd_ibar : VitalDelayType01 := DefPropDelay01; tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; tpd_i_o : VitalDelayType01 := DefPropDelay01; tpd_ibar_o : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; differential_mode : string := "false"; bus_hold : string := "false"; simulate_z_as : string := "Z"; lpm_type : string := "stratixiii_io_ibuf" ); PORT ( i : IN std_logic := '0'; ibar : IN std_logic := '0'; dynamicterminationcontrol : IN std_logic := '0'; o : OUT std_logic ); END COMPONENT; -- -- stratixiii_io_obuf -- COMPONENT stratixiii_io_obuf GENERIC ( tipd_i : VitalDelayType01 := DefPropDelay01; tipd_oe : VitalDelayType01 := DefPropDelay01; tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01; tipd_seriesterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01); tipd_parallelterminationcontrol : VitalDelayArrayType01(13 DOWNTO 0) := (others => DefPropDelay01 ); tpd_i_o : VitalDelayType01 := DefPropDelay01; tpd_oe_o : VitalDelayType01 := DefPropDelay01; tpd_i_obar : VitalDelayType01 := DefPropDelay01; tpd_oe_obar : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; open_drain_output : string := "false"; shift_series_termination_control : string := "false"; sim_dynamic_termination_control_is_connected : string := "false"; bus_hold : string := "false"; lpm_type : string := "stratixiii_io_obuf" ); PORT ( i : IN std_logic := '0'; oe : IN std_logic := '1'; dynamicterminationcontrol : IN std_logic := '0'; seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0'); parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0'); devoe : IN std_logic := '1'; o : OUT std_logic; obar : OUT std_logic ); END COMPONENT; -- -- stratixiii_ddio_in -- COMPONENT stratixiii_ddio_in generic( tipd_datain : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_clkn : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_sreset : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; use_clkn : string := "false"; lpm_type : string := "stratixiii_ddio_in" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; clkn : IN std_logic := '0'; ena : IN std_logic := '1'; areset : IN std_logic := '0'; sreset : IN std_logic := '0'; regoutlo : OUT std_logic; regouthi : OUT std_logic; dfflo : OUT std_logic; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END COMPONENT; -- -- stratixiii_ddio_oe -- COMPONENT stratixiii_ddio_oe generic( tipd_oe : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_sreset : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; lpm_type : string := "stratixiii_ddio_oe" ); PORT ( oe : IN std_logic := '1'; clk : IN std_logic := '0'; ena : IN std_logic := '1'; areset : IN std_logic := '0'; sreset : IN std_logic := '0'; dataout : OUT std_logic; dfflo : OUT std_logic; dffhi : OUT std_logic; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END COMPONENT; -- -- stratixiii_ddio_out -- COMPONENT stratixiii_ddio_out generic( tipd_datainlo : VitalDelayType01 := DefPropDelay01; tipd_datainhi : VitalDelayType01 := DefPropDelay01; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_clkhi : VitalDelayType01 := DefPropDelay01; tipd_clklo : VitalDelayType01 := DefPropDelay01; tipd_muxsel : VitalDelayType01 := DefPropDelay01; tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_sreset : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; half_rate_mode : string := "false"; use_new_clocking_model : string := "false"; lpm_type : string := "stratixiii_ddio_out" ); PORT ( datainlo : IN std_logic := '0'; datainhi : IN std_logic := '0'; clk : IN std_logic := '0'; clkhi : IN std_logic := '0'; clklo : IN std_logic := '0'; muxsel : IN std_logic := '0'; ena : IN std_logic := '1'; areset : IN std_logic := '0'; sreset : IN std_logic := '0'; dataout : OUT std_logic; dfflo : OUT std_logic; dffhi : OUT std_logic_vector(1 downto 0) ; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END COMPONENT; -- -- stratixiii_termination -- COMPONENT stratixiii_termination GENERIC ( runtime_control : STRING := "false"; allow_serial_data_from_core : STRING := "false"; power_down : STRING := "true"; enable_parallel_termination : STRING := "false"; test_mode : STRING := "false"; enable_calclk_divider : STRING := "false"; -- replaced by below clock_divider_enable : STRING := "false"; enable_pwrupmode_enser_for_usrmode : STRING := "false"; bypass_enser_logic : STRING := "false"; bypass_rt_calclk : STRING := "false"; enable_rt_scan_mode : STRING := "false"; enable_loopback : STRING := "false"; force_rtcalen_for_pllbiasen : STRING := "false"; enable_rt_sm_loopback : STRING := "false"; select_vrefl_values : integer := 0; select_vrefh_values : integer := 0; divide_intosc_by : integer := 2; use_usrmode_clear_for_configmode : STRING := "false"; tipd_rup : VitalDelayType01 := DefpropDelay01; tipd_rdn : VitalDelayType01 := DefpropDelay01; tipd_terminationclock : VitalDelayType01 := DefpropDelay01; tipd_terminationclear : VitalDelayType01 := DefpropDelay01; tipd_terminationenable : VitalDelayType01 := DefpropDelay01; tipd_serializerenable : VitalDelayType01 := DefpropDelay01; tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01; tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01); lpm_type : STRING := "stratixiii_termination"); PORT ( rup : IN std_logic := '0'; rdn : IN std_logic := '0'; terminationclock : IN std_logic := '0'; terminationclear : IN std_logic := '0'; terminationenable : IN std_logic := '1'; serializerenable : IN std_logic := '0'; terminationcontrolin : IN std_logic := '0'; scanin : IN std_logic := '0'; scanen : IN std_logic := '0'; otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0'); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; incrup : OUT std_logic; incrdn : OUT std_logic; serializerenableout : OUT std_logic; terminationcontrol : OUT std_logic; terminationcontrolprobe : OUT std_logic; scanout : OUT std_logic; shiftregisterprobe : OUT std_logic); END COMPONENT; -- -- stratixiii_termination_logic -- COMPONENT stratixiii_termination_logic GENERIC ( tipd_serialloadenable : VitalDelayType01 := DefpropDelay01; tipd_terminationclock : VitalDelayType01 := DefpropDelay01; tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01; tipd_terminationdata : VitalDelayType01 := DefpropDelay01; test_mode : string := "false"; lpm_type : string := "stratixiii_termination_logic"); PORT ( serialloadenable : IN std_logic := '0'; terminationclock : IN std_logic := '0'; parallelloadenable : IN std_logic := '0'; terminationdata : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0); parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0)); END COMPONENT; -- -- stratixiii_dll -- COMPONENT stratixiii_dll GENERIC ( input_frequency : string := "0 ps"; delay_buffer_mode : string := "low"; delay_chain_length : integer := 12; delayctrlout_mode : string := "normal"; jitter_reduction : string := "false"; use_upndnin : string := "false"; use_upndninclkena : string := "false"; dual_phase_comparators : string := "true"; sim_valid_lock : integer := 16; sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; static_delay_ctrl : integer := 0; lpm_type : string := "stratixiii_dll"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_aload : VitalDelayType01 := DefpropDelay01; tipd_upndnin : VitalDelayType01 := DefpropDelay01; tipd_upndninclkena : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01; tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01) ); PORT ( clk : IN std_logic := '0'; aload : IN std_logic := '0'; upndnin : IN std_logic := '1'; upndninclkena : IN std_logic := '1'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '0'; delayctrlout : OUT std_logic_vector(5 DOWNTO 0); dqsupdate : OUT std_logic; offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0); offsetdelayctrlclkout : OUT std_logic; upndnout : OUT std_logic ); END COMPONENT; -- -- stratixiii_dll_offset_ctrl -- COMPONENT stratixiii_dll_offset_ctrl GENERIC ( use_offset : string := "false"; static_offset : string := "0"; delay_buffer_mode : string := "low"; lpm_type : string := "stratixiii_dll_offset_ctrl"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_aload : VitalDelayType01 := DefpropDelay01; tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_addnsub : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01) ); PORT ( clk : IN std_logic := '0'; aload : IN std_logic := '0'; offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000"; offset : IN std_logic_vector(5 DOWNTO 0) := "000000"; addnsub : IN std_logic := '1'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '0'; offsettestout : OUT std_logic_vector(5 DOWNTO 0); offsetctrlout : OUT std_logic_vector(5 DOWNTO 0) ); END COMPONENT; -- -- stratixiii_dqs_delay_chain -- COMPONENT stratixiii_dqs_delay_chain GENERIC ( dqs_input_frequency : string := "unused" ; use_phasectrlin : string := "false"; phase_setting : integer := 0; delay_buffer_mode : string := "low"; dqs_phase_shift : integer := 0; dqs_offsetctrl_enable : string := "false"; dqs_ctrl_latches_enable : string := "false"; test_enable : string := "false"; test_select : integer := 0; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "stratixiii_dqs_delay_chain"; tipd_dqsin : VitalDelayType01 := DefpropDelay01; tipd_aload : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01; tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01); tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01; tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst); TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( dqsin : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); dqsupdateen : IN std_logic := '1'; phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0'); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsbusout : OUT std_logic; dffin : OUT std_logic ); END COMPONENT; -- -- stratixiii_dqs_enable -- COMPONENT stratixiii_dqs_enable GENERIC ( lpm_type : string := "stratixiii_dqs_enable"; tipd_dqsin : VitalDelayType01 := DefpropDelay01; tipd_dqsenable : VitalDelayType01 := DefpropDelay01; tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01; tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( dqsin : IN std_logic := '0'; dqsenable : IN std_logic := '1'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsbusout : OUT std_logic ); END COMPONENT; -- -- stratixiii_dqs_enable_ctrl -- COMPONENT stratixiii_dqs_enable_ctrl GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; level_dqs_enable : string := "false"; delay_dqs_enable_by_half_cycle : string := "false"; add_phase_transfer_reg : string := "false"; invert_phase : string := "false"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "stratixiii_dqs_enable_ctrl"; tipd_dqsenablein : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01; tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( dqsenablein : IN std_logic := '1'; clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); enaphasetransferreg : IN std_logic := '0'; phaseinvertctrl : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsenableout : OUT std_logic; dffin : OUT std_logic; dffextenddqsenable : OUT std_logic ); END COMPONENT; -- -- stratixiii_delay_chain -- COMPONENT stratixiii_delay_chain GENERIC ( sim_delayctrlin_rising_delay_0 : integer := 0; sim_delayctrlin_rising_delay_1 : integer := 50; sim_delayctrlin_rising_delay_2 : integer := 100; sim_delayctrlin_rising_delay_3 : integer := 150; sim_delayctrlin_rising_delay_4 : integer := 200; sim_delayctrlin_rising_delay_5 : integer := 250; sim_delayctrlin_rising_delay_6 : integer := 300; sim_delayctrlin_rising_delay_7 : integer := 350; sim_delayctrlin_rising_delay_8 : integer := 400; sim_delayctrlin_rising_delay_9 : integer := 450; sim_delayctrlin_rising_delay_10 : integer := 500; sim_delayctrlin_rising_delay_11 : integer := 550; sim_delayctrlin_rising_delay_12 : integer := 600; sim_delayctrlin_rising_delay_13 : integer := 650; sim_delayctrlin_rising_delay_14 : integer := 700; sim_delayctrlin_rising_delay_15 : integer := 750; sim_delayctrlin_falling_delay_0 : integer := 0; sim_delayctrlin_falling_delay_1 : integer := 50; sim_delayctrlin_falling_delay_2 : integer := 100; sim_delayctrlin_falling_delay_3 : integer := 150; sim_delayctrlin_falling_delay_4 : integer := 200; sim_delayctrlin_falling_delay_5 : integer := 250; sim_delayctrlin_falling_delay_6 : integer := 300; sim_delayctrlin_falling_delay_7 : integer := 350; sim_delayctrlin_falling_delay_8 : integer := 400; sim_delayctrlin_falling_delay_9 : integer := 450; sim_delayctrlin_falling_delay_10 : integer := 500; sim_delayctrlin_falling_delay_11 : integer := 550; sim_delayctrlin_falling_delay_12 : integer := 600; sim_delayctrlin_falling_delay_13 : integer := 650; sim_delayctrlin_falling_delay_14 : integer := 700; sim_delayctrlin_falling_delay_15 : integer := 750; use_delayctrlin : string := "true"; delay_setting : integer := 0; sim_finedelayctrlin_falling_delay_0 : integer := 0; sim_finedelayctrlin_falling_delay_1 : integer := 25; sim_finedelayctrlin_rising_delay_0 : integer := 0; sim_finedelayctrlin_rising_delay_1 : integer := 25; use_finedelayctrlin : string := "false"; lpm_type : string := "stratixiii_delay_chain"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tpd_datain_dataout : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); finedelayctrlin : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dataout : OUT std_logic ); END COMPONENT; -- -- stratixiii_io_clock_divider -- COMPONENT stratixiii_io_clock_divider GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; use_masterin : string := "false"; invert_phase : string := "false"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "stratixiii_io_clock_divider"; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_phaseselect : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; tipd_masterin : VitalDelayType01 := DefpropDelay01; tpd_clk_clkout : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( clk : IN std_logic := '0'; phaseselect : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); phaseinvertctrl : IN std_logic := '0'; masterin : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; clkout : OUT std_logic; slaveout : OUT std_logic ); END COMPONENT; -- -- stratixiii_output_phase_alignment -- COMPONENT stratixiii_output_phase_alignment GENERIC ( operation_mode : string := "ddio_out"; use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; power_up : string := "low"; async_mode : string := "none"; sync_mode : string := "none"; add_output_cycle_delay : string := "false"; use_delayed_clock : string := "false"; add_phase_transfer_reg : string := "false"; use_phasectrl_clock : string := "true"; use_primary_clock : string := "true"; invert_phase : string := "false"; bypass_input_register : string := "false"; phase_setting_for_delayed_clock : integer := 2; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; duty_cycle_delay_mode : string := "none"; sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ; sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ; sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ; sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ; sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ; sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ; sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ; sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ; sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ; sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ; sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ; sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ; sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ; sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ; sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ; sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ; sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ; sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ; sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ; sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ; sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ; sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ; sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ; sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ; sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ; sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ; sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ; sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ; sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ; sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ; sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ; sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ; lpm_type : string := "stratixiii_output_phase_alignment"; tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_areset : VitalDelayType01 := DefpropDelay01; tipd_sreset : VitalDelayType01 := DefpropDelay01; tipd_clkena : VitalDelayType01 := DefpropDelay01; tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01; tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01; tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0'); clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); areset : IN std_logic := '0'; sreset : IN std_logic := '0'; clkena : IN std_logic := '1'; enaoutputcycledelay : IN std_logic := '0'; enaphasetransferreg : IN std_logic := '0'; phaseinvertctrl : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008 dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0'); dataout : OUT std_logic; dffin : OUT std_logic_vector(1 downto 0); dff1t : OUT std_logic_vector(1 downto 0); dffddiodataout : OUT std_logic ); END COMPONENT; -- -- stratixiii_input_phase_alignment -- COMPONENT stratixiii_input_phase_alignment GENERIC ( use_phasectrlin : string := "true"; phase_setting : integer := 0; delay_buffer_mode : string := "high"; power_up : string := "low"; async_mode : string := "none"; add_input_cycle_delay : string := "false"; bypass_output_register : string := "false"; add_phase_transfer_reg : string := "false"; invert_phase : string := "false"; sim_low_buffer_intrinsic_delay : integer := 350; sim_high_buffer_intrinsic_delay : integer := 175; sim_buffer_delay_increment : integer := 10; lpm_type : string := "stratixiii_input_phase_alignment"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01); tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01); tipd_areset : VitalDelayType01 := DefpropDelay01; tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01; tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01; tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0'); phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0'); areset : IN std_logic := '0'; enainputcycledelay : IN std_logic := '0'; enaphasetransferreg : IN std_logic := '0'; phaseinvertctrl : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dataout : OUT std_logic; dffin : OUT std_logic; dff1t : OUT std_logic ); END COMPONENT; -- -- stratixiii_half_rate_input -- COMPONENT stratixiii_half_rate_input GENERIC ( power_up : string := "low"; async_mode : string := "none"; use_dataoutbypass : string := "false"; lpm_type : string := "stratixiii_half_rate_input"; tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tipd_directin : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_areset : VitalDelayType01 := DefpropDelay01; tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0'); directin : IN std_logic := '0'; clk : IN std_logic := '0'; areset : IN std_logic := '0'; dataoutbypass: IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dataout : OUT std_logic_vector(3 downto 0); dffin : OUT std_logic ); END COMPONENT; -- -- stratixiii_io_config -- COMPONENT stratixiii_io_config GENERIC ( enhanced_mode : string := "false"; lpm_type : string := "stratixiii_io_config"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_update : VitalDelayType01 := DefpropDelay01; tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; ena : IN std_logic := '1'; update : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dutycycledelaymode : OUT std_logic; dutycycledelaysettings : OUT std_logic_vector(3 downto 0); outputfinedelaysetting1 : OUT std_logic; outputfinedelaysetting2 : OUT std_logic; outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0); outputonlyfinedelaysetting2 : OUT std_logic; padtoinputregisterfinedelaysetting : OUT std_logic; padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0); outputdelaysetting1 : OUT std_logic_vector(3 downto 0); outputdelaysetting2 : OUT std_logic_vector(2 downto 0); dataout : OUT std_logic ); END COMPONENT; -- -- stratixiii_dqs_config -- COMPONENT stratixiii_dqs_config GENERIC ( enhanced_mode : string := "false"; lpm_type : string := "stratixiii_dqs_config"; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_clk : VitalDelayType01 := DefpropDelay01; tipd_ena : VitalDelayType01 := DefpropDelay01; tipd_update : VitalDelayType01 := DefpropDelay01; tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01; TimingChecksOn : Boolean := True; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*" ); PORT ( datain : IN std_logic := '0'; clk : IN std_logic := '0'; ena : IN std_logic := '0'; update : IN std_logic := '0'; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1'; dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0); dqsinputphasesetting : OUT std_logic_vector(2 downto 0); dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0); dqsoutputphasesetting : OUT std_logic_vector(3 downto 0); dqoutputphasesetting : OUT std_logic_vector(3 downto 0); resyncinputphasesetting : OUT std_logic_vector(3 downto 0); dividerphasesetting : OUT std_logic; enaoctcycledelaysetting : OUT std_logic; enainputcycledelaysetting : OUT std_logic; enaoutputcycledelaysetting: OUT std_logic; dqsenabledelaysetting : OUT std_logic_vector(2 downto 0); octdelaysetting1 : OUT std_logic_vector(3 downto 0); octdelaysetting2 : OUT std_logic_vector(2 downto 0); enadataoutbypass : OUT std_logic; enadqsenablephasetransferreg : OUT std_logic; enaoctphasetransferreg : OUT std_logic; enaoutputphasetransferreg : OUT std_logic; enainputphasetransferreg : OUT std_logic; resyncinputphaseinvert : OUT std_logic; dqsenablectrlphaseinvert : OUT std_logic; dqoutputphaseinvert : OUT std_logic; dqsoutputphaseinvert : OUT std_logic; dataout : OUT std_logic ); END COMPONENT; -- -- stratixiii_mac_mult -- COMPONENT stratixiii_mac_mult GENERIC ( dataa_width : integer := 18; datab_width : integer := 18; dataa_clock : string := "none"; datab_clock : string := "none"; signa_clock : string := "none"; signb_clock : string := "none"; scanouta_clock : string := "none"; dataa_clear : string := "none"; datab_clear : string := "none"; signa_clear : string := "none"; signb_clear : string := "none"; scanouta_clear : string := "none"; signa_internally_grounded : string := "false"; signb_internally_grounded : string := "false"; lpm_type : string := "stratixiii_mac_mult" ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1'); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1'); signa : IN std_logic := '1'; signb : IN std_logic := '1'; clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1'); dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0); scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0); devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END COMPONENT; -- -- stratixiii_mac_out -- COMPONENT stratixiii_mac_out GENERIC ( operation_mode : string := "output_only"; dataa_width : integer := 1; datab_width : integer := 1; datac_width : integer := 1; datad_width : integer := 1; chainin_width : integer := 1; round_width : integer := 15; round_chain_out_width : integer := 15; saturate_width : integer := 15; saturate_chain_out_width : integer := 15; first_adder0_clock : string := "none"; first_adder0_clear : string := "none"; first_adder1_clock : string := "none"; first_adder1_clear : string := "none"; second_adder_clock : string := "none"; second_adder_clear : string := "none"; output_clock : string := "none"; output_clear : string := "none"; signa_clock : string := "none"; signa_clear : string := "none"; signb_clock : string := "none"; signb_clear : string := "none"; round_clock : string := "none"; round_clear : string := "none"; roundchainout_clock : string := "none"; roundchainout_clear : string := "none"; saturate_clock : string := "none"; saturate_clear : string := "none"; saturatechainout_clock : string := "none"; saturatechainout_clear : string := "none"; zeroacc_clock : string := "none"; zeroacc_clear : string := "none"; zeroloopback_clock : string := "none"; zeroloopback_clear : string := "none"; rotate_clock : string := "none"; rotate_clear : string := "none"; shiftright_clock : string := "none"; shiftright_clear : string := "none"; signa_pipeline_clock : string := "none"; signa_pipeline_clear : string := "none"; signb_pipeline_clock : string := "none"; signb_pipeline_clear : string := "none"; round_pipeline_clock : string := "none"; round_pipeline_clear : string := "none"; roundchainout_pipeline_clock : string := "none"; roundchainout_pipeline_clear : string := "none"; saturate_pipeline_clock : string := "none"; saturate_pipeline_clear : string := "none"; saturatechainout_pipeline_clock: string := "none"; saturatechainout_pipeline_clear: string := "none"; zeroacc_pipeline_clock : string := "none"; zeroacc_pipeline_clear : string := "none"; zeroloopback_pipeline_clock : string := "none"; zeroloopback_pipeline_clear : string := "none"; rotate_pipeline_clock : string := "none"; rotate_pipeline_clear : string := "none"; shiftright_pipeline_clock : string := "none"; shiftright_pipeline_clear : string := "none"; roundchainout_output_clock : string := "none"; roundchainout_output_clear : string := "none"; saturatechainout_output_clock : string := "none"; saturatechainout_output_clear : string := "none"; zerochainout_output_clock : string := "none"; zerochainout_output_clear : string := "none"; zeroloopback_output_clock : string := "none"; zeroloopback_output_clear : string := "none"; rotate_output_clock : string := "none"; rotate_output_clear : string := "none"; shiftright_output_clock : string := "none"; shiftright_output_clear : string := "none"; first_adder0_mode : string := "add"; first_adder1_mode : string := "add"; acc_adder_operation : string := "add"; round_mode : string := "nearest_integer"; round_chain_out_mode : string := "nearest_integer"; saturate_mode : string := "asymmetric"; saturate_chain_out_mode : string := "asymmetric"; multa_signa_internally_grounded : string := "false"; multa_signb_internally_grounded : string := "false"; multb_signa_internally_grounded : string := "false"; multb_signb_internally_grounded : string := "false"; multc_signa_internally_grounded : string := "false"; multc_signb_internally_grounded : string := "false"; multd_signa_internally_grounded : string := "false"; multd_signb_internally_grounded : string := "false"; lpm_type : string := "stratixiii_mac_out"; dataout_width : integer:=72 ); PORT ( dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1'); datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1'); datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1'); datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1'); signa : IN std_logic := '1'; signb : IN std_logic := '1'; chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0'); round : IN std_logic := '0'; saturate : IN std_logic := '0'; zeroacc : IN std_logic := '0'; roundchainout : IN std_logic := '0'; saturatechainout : IN std_logic := '0'; zerochainout : IN std_logic := '0'; zeroloopback : IN std_logic := '0'; rotate : IN std_logic := '0'; shiftright : IN std_logic := '0'; clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1'); aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0'); loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0'); dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0'); overflow : OUT std_logic := '0'; saturatechainoutoverflow: OUT std_logic := '0'; dftout : OUT std_logic := '0'; devpor : IN std_logic := '1'; devclrn : IN std_logic := '1' ); END COMPONENT; -- -- stratixiii_io_pad -- COMPONENT stratixiii_io_pad GENERIC ( lpm_type : string := "stratixiii_io_pad"); PORT ( padin : IN std_logic := '0'; -- Input Pad padout : OUT std_logic); -- Output Pad END COMPONENT; -- -- stratixiii_pll -- COMPONENT stratixiii_pll GENERIC ( operation_mode : string := "normal"; pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM compensate_clock : string := "clock0"; inclk0_input_frequency : integer := 0; inclk1_input_frequency : integer := 0; self_reset_on_loss_lock : string := "off"; switch_over_type : string := "auto"; switch_over_counter : integer := 1; enable_switch_over_counter : string := "off"; dpa_multiply_by : integer := 0; dpa_divide_by : integer := 0; dpa_divider : integer := 0; bandwidth : integer := 0; bandwidth_type : string := "auto"; use_dc_coupling : string := "false"; lock_c : integer := 4; sim_gate_lock_device_behavior : string := "off"; lock_high : integer := 0; lock_low : integer := 0; lock_window_ui : string := "0.05"; lock_window : time := 5 ps; test_bypass_lock_detect : string := "off"; clk0_output_frequency : integer := 0; clk0_multiply_by : integer := 0; clk0_divide_by : integer := 0; clk0_phase_shift : string := "0"; clk0_duty_cycle : integer := 50; clk1_output_frequency : integer := 0; clk1_multiply_by : integer := 0; clk1_divide_by : integer := 0; clk1_phase_shift : string := "0"; clk1_duty_cycle : integer := 50; clk2_output_frequency : integer := 0; clk2_multiply_by : integer := 0; clk2_divide_by : integer := 0; clk2_phase_shift : string := "0"; clk2_duty_cycle : integer := 50; clk3_output_frequency : integer := 0; clk3_multiply_by : integer := 0; clk3_divide_by : integer := 0; clk3_phase_shift : string := "0"; clk3_duty_cycle : integer := 50; clk4_output_frequency : integer := 0; clk4_multiply_by : integer := 0; clk4_divide_by : integer := 0; clk4_phase_shift : string := "0"; clk4_duty_cycle : integer := 50; clk5_output_frequency : integer := 0; clk5_multiply_by : integer := 0; clk5_divide_by : integer := 0; clk5_phase_shift : string := "0"; clk5_duty_cycle : integer := 50; clk6_output_frequency : integer := 0; clk6_multiply_by : integer := 0; clk6_divide_by : integer := 0; clk6_phase_shift : string := "0"; clk6_duty_cycle : integer := 50; clk7_output_frequency : integer := 0; clk7_multiply_by : integer := 0; clk7_divide_by : integer := 0; clk7_phase_shift : string := "0"; clk7_duty_cycle : integer := 50; clk8_output_frequency : integer := 0; clk8_multiply_by : integer := 0; clk8_divide_by : integer := 0; clk8_phase_shift : string := "0"; clk8_duty_cycle : integer := 50; clk9_output_frequency : integer := 0; clk9_multiply_by : integer := 0; clk9_divide_by : integer := 0; clk9_phase_shift : string := "0"; clk9_duty_cycle : integer := 50; pfd_min : integer := 0; pfd_max : integer := 0; vco_min : integer := 0; vco_max : integer := 0; vco_center : integer := 0; m_initial : integer := 1; m : integer := 0; n : integer := 1; c0_high : integer := 1; c0_low : integer := 1; c0_initial : integer := 1; c0_mode : string := "bypass"; c0_ph : integer := 0; c1_high : integer := 1; c1_low : integer := 1; c1_initial : integer := 1; c1_mode : string := "bypass"; c1_ph : integer := 0; c2_high : integer := 1; c2_low : integer := 1; c2_initial : integer := 1; c2_mode : string := "bypass"; c2_ph : integer := 0; c3_high : integer := 1; c3_low : integer := 1; c3_initial : integer := 1; c3_mode : string := "bypass"; c3_ph : integer := 0; c4_high : integer := 1; c4_low : integer := 1; c4_initial : integer := 1; c4_mode : string := "bypass"; c4_ph : integer := 0; c5_high : integer := 1; c5_low : integer := 1; c5_initial : integer := 1; c5_mode : string := "bypass"; c5_ph : integer := 0; c6_high : integer := 1; c6_low : integer := 1; c6_initial : integer := 1; c6_mode : string := "bypass"; c6_ph : integer := 0; c7_high : integer := 1; c7_low : integer := 1; c7_initial : integer := 1; c7_mode : string := "bypass"; c7_ph : integer := 0; c8_high : integer := 1; c8_low : integer := 1; c8_initial : integer := 1; c8_mode : string := "bypass"; c8_ph : integer := 0; c9_high : integer := 1; c9_low : integer := 1; c9_initial : integer := 1; c9_mode : string := "bypass"; c9_ph : integer := 0; m_ph : integer := 0; clk0_counter : string := "unused"; clk1_counter : string := "unused"; clk2_counter : string := "unused"; clk3_counter : string := "unused"; clk4_counter : string := "unused"; clk5_counter : string := "unused"; clk6_counter : string := "unused"; clk7_counter : string := "unused"; clk8_counter : string := "unused"; clk9_counter : string := "unused"; c1_use_casc_in : string := "off"; c2_use_casc_in : string := "off"; c3_use_casc_in : string := "off"; c4_use_casc_in : string := "off"; c5_use_casc_in : string := "off"; c6_use_casc_in : string := "off"; c7_use_casc_in : string := "off"; c8_use_casc_in : string := "off"; c9_use_casc_in : string := "off"; m_test_source : integer := -1; c0_test_source : integer := -1; c1_test_source : integer := -1; c2_test_source : integer := -1; c3_test_source : integer := -1; c4_test_source : integer := -1; c5_test_source : integer := -1; c6_test_source : integer := -1; c7_test_source : integer := -1; c8_test_source : integer := -1; c9_test_source : integer := -1; vco_multiply_by : integer := 0; vco_divide_by : integer := 0; vco_post_scale : integer := 1; vco_frequency_control : string := "auto"; vco_phase_shift_step : integer := 0; charge_pump_current : integer := 10; loop_filter_r : string := " 1.0"; loop_filter_c : integer := 0; pll_compensation_delay : integer := 0; simulation_type : string := "functional"; lpm_type : string := "stratixiii_pll"; clk0_use_even_counter_mode : string := "off"; clk1_use_even_counter_mode : string := "off"; clk2_use_even_counter_mode : string := "off"; clk3_use_even_counter_mode : string := "off"; clk4_use_even_counter_mode : string := "off"; clk5_use_even_counter_mode : string := "off"; clk6_use_even_counter_mode : string := "off"; clk7_use_even_counter_mode : string := "off"; clk8_use_even_counter_mode : string := "off"; clk9_use_even_counter_mode : string := "off"; clk0_use_even_counter_value : string := "off"; clk1_use_even_counter_value : string := "off"; clk2_use_even_counter_value : string := "off"; clk3_use_even_counter_value : string := "off"; clk4_use_even_counter_value : string := "off"; clk5_use_even_counter_value : string := "off"; clk6_use_even_counter_value : string := "off"; clk7_use_even_counter_value : string := "off"; clk8_use_even_counter_value : string := "off"; clk9_use_even_counter_value : string := "off"; init_block_reset_a_count : integer := 1; init_block_reset_b_count : integer := 1; charge_pump_current_bits : integer := 0; lock_window_ui_bits : integer := 0; loop_filter_c_bits : integer := 0; loop_filter_r_bits : integer := 0; test_counter_c0_delay_chain_bits : integer := 0; test_counter_c1_delay_chain_bits : integer := 0; test_counter_c2_delay_chain_bits : integer := 0; test_counter_c3_delay_chain_bits : integer := 0; test_counter_c4_delay_chain_bits : integer := 0; test_counter_c5_delay_chain_bits : integer := 0; test_counter_c6_delay_chain_bits : integer := 0; test_counter_c7_delay_chain_bits : integer := 0; test_counter_c8_delay_chain_bits : integer := 0; test_counter_c9_delay_chain_bits : integer := 0; test_counter_m_delay_chain_bits : integer := 0; test_counter_n_delay_chain_bits : integer := 0; test_feedback_comp_delay_chain_bits : integer := 0; test_input_comp_delay_chain_bits : integer := 0; test_volt_reg_output_mode_bits : integer := 0; test_volt_reg_output_voltage_bits : integer := 0; test_volt_reg_test_mode : string := "false"; vco_range_detector_high_bits : integer := -1; vco_range_detector_low_bits : integer := -1; scan_chain_mif_file : string := ""; dpa_output_clock_phase_shift : integer := 0; test_counter_c3_sclk_delay_chain_bits : integer := -1; test_counter_c4_sclk_delay_chain_bits : integer := -1; test_counter_c5_lden_delay_chain_bits : integer := -1; test_counter_c6_lden_delay_chain_bits : integer := -1; auto_settings : string := "true"; family_name : string := "StratixIII"; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; TimingChecksOn : Boolean := true; InstancePath : STRING := "*"; tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01); tipd_ena : VitalDelayType01 := DefPropDelay01; tipd_pfdena : VitalDelayType01 := DefPropDelay01; tipd_areset : VitalDelayType01 := DefPropDelay01; tipd_fbin : VitalDelayType01 := DefPropDelay01; tipd_scanclk : VitalDelayType01 := DefPropDelay01; tipd_scanclkena : VitalDelayType01 := DefPropDelay01; tipd_scandata : VitalDelayType01 := DefPropDelay01; tipd_configupdate : VitalDelayType01 := DefPropDelay01; tipd_clkswitch : VitalDelayType01 := DefPropDelay01; tipd_phaseupdown : VitalDelayType01 := DefPropDelay01; tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01); tipd_phasestep : VitalDelayType01 := DefPropDelay01; tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst; use_vco_bypass : string := "false" ); PORT ( inclk : in std_logic_vector(1 downto 0); fbin : in std_logic := '0'; fbout : out std_logic; clkswitch : in std_logic := '0'; areset : in std_logic := '0'; pfdena : in std_logic := '1'; scandata : in std_logic := '0'; scanclk : in std_logic := '0'; scanclkena : in std_logic := '1'; configupdate : in std_logic := '0'; clk : out std_logic_vector(9 downto 0); phasecounterselect : in std_logic_vector(3 downto 0) := "0000"; phaseupdown : in std_logic := '0'; phasestep : in std_logic := '0'; clkbad : out std_logic_vector(1 downto 0); activeclock : out std_logic; locked : out std_logic; scandataout : out std_logic; scandone : out std_logic; phasedone : out std_logic; vcooverrange : out std_logic; vcounderrange : out std_logic ); END COMPONENT; -- -- stratixiii_asmiblock -- COMPONENT stratixiii_asmiblock generic ( lpm_type : string := "stratixiii_asmiblock" ); port ( dclkin : in std_logic := '0'; scein : in std_logic := '0'; sdoin : in std_logic := '0'; data0in : in std_logic := '0'; oe : in std_logic := '0'; dclkout : out std_logic; sceout : out std_logic; sdoout : out std_logic; data0out: out std_logic ); END COMPONENT; -- -- stratixiii_lvds_receiver -- COMPONENT stratixiii_lvds_receiver GENERIC ( channel_width : integer := 10; data_align_rollover : integer := 2; enable_dpa : string := "off"; lose_lock_on_one_change : string := "off"; reset_fifo_at_first_lock : string := "on"; align_to_rising_edge_only : string := "on"; use_serial_feedback_input : string := "off"; dpa_debug : string := "off"; enable_soft_cdr : string := "off"; dpa_output_clock_phase_shift : INTEGER := 0 ; enable_dpa_initial_phase_selection : string := "off"; dpa_initial_phase_value : INTEGER := 0; enable_dpa_align_to_rising_edge_only : string := "off"; net_ppm_variation : INTEGER := 0; is_negative_ppm_drift : string := "off"; rx_input_path_delay_engineering_bits : INTEGER := -1; x_on_bitslip : string := "on"; lpm_type : string := "stratixiii_lvds_receiver"; MsgOn : Boolean := DefGlitchMsgOn; XOn : Boolean := DefGlitchXOn; MsgOnChecks : Boolean := DefMsgOnChecks; XOnChecks : Boolean := DefXOnChecks; InstancePath : String := "*"; tipd_clk0 : VitalDelayType01 := DefpropDelay01; tipd_datain : VitalDelayType01 := DefpropDelay01; tipd_enable0 : VitalDelayType01 := DefpropDelay01; tipd_dpareset : VitalDelayType01 := DefpropDelay01; tipd_dpahold : VitalDelayType01 := DefpropDelay01; tipd_dpaswitch : VitalDelayType01 := DefpropDelay01; tipd_fiforeset : VitalDelayType01 := DefpropDelay01; tipd_bitslip : VitalDelayType01 := DefpropDelay01; tipd_bitslipreset : VitalDelayType01 := DefpropDelay01; tipd_serialfbk : VitalDelayType01 := DefpropDelay01; tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01 ); PORT ( clk0 : IN std_logic; datain : IN std_logic := '0'; enable0 : IN std_logic := '0'; dpareset : IN std_logic := '0'; dpahold : IN std_logic := '0'; dpaswitch : IN std_logic := '0'; fiforeset : IN std_logic := '0'; bitslip : IN std_logic := '0'; bitslipreset : IN std_logic := '0'; serialfbk : IN std_logic := '0'; dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0); dpalock : OUT std_logic:= '0'; bitslipmax : OUT std_logic; serialdataout : OUT std_logic; postdpaserialdataout : OUT std_logic; divfwdclk : OUT std_logic; dpaclkout : OUT std_logic; devclrn : IN std_logic := '1'; devpor : IN std_logic := '1' ); END COMPONENT; -- -- stratixiii_pseudo_diff_out -- COMPONENT stratixiii_pseudo_diff_out GENERIC ( tipd_i : VitalDelayType01 := DefPropDelay01; tpd_i_o : VitalDelayType01 := DefPropDelay01; tpd_i_obar : VitalDelayType01 := DefPropDelay01; XOn : Boolean := DefGlitchXOn; MsgOn : Boolean := DefGlitchMsgOn; lpm_type : string := "stratixiii_pseudo_diff_out" ); PORT ( i : IN std_logic := '0'; o : OUT std_logic; obar : OUT std_logic ); END COMPONENT; -- -- stratixiii_bias_block -- COMPONENT stratixiii_bias_block GENERIC ( lpm_type : string := "stratixiii_bias_block"; tipd_clk : VitalDelayType01 := DefPropDelay01; tipd_shiftnld : VitalDelayType01 := DefPropDelay01; tipd_captnupdt : VitalDelayType01 := DefPropDelay01; tipd_din : VitalDelayType01 := DefPropDelay01; tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst; tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01; MsgOn: Boolean := DefGlitchMsgOn; XOn: Boolean := DefGlitchXOn; MsgOnChecks: Boolean := DefMsgOnChecks; XOnChecks: Boolean := DefXOnChecks ); PORT ( clk : in std_logic := '0'; shiftnld : in std_logic := '0'; captnupdt : in std_logic := '0'; din : in std_logic := '0'; dout : out std_logic := '0' ); END COMPONENT; -- -- stratixiii_tsdblock -- COMPONENT stratixiii_tsdblock generic ( poi_cal_temperature : integer := 85; clock_divider_enable : string := "on"; clock_divider_value : integer := 40; sim_tsdcalo : integer := 0; user_offset_enable : string := "off"; lpm_type : string := "stratixiii_tsdblock" ); port ( offset : in std_logic_vector(5 downto 0) := (OTHERS => '0'); clk : in std_logic := '0'; ce : in std_logic := '0'; clr : in std_logic := '0'; testin : in std_logic_vector(7 downto 0) := (OTHERS => '0'); tsdcalo : out std_logic_vector(7 downto 0); tsdcaldone : out std_logic; fdbkctrlfromcore : in std_logic := '0'; compouttest : in std_logic := '0'; tsdcompout : out std_logic; offsetout : out std_logic_vector(5 downto 0) ); END COMPONENT; end stratixiii_components;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015 - 2016, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Entity: techmult -- File: techmult.vhd -- Author: Jiri Gaisler - Gaisler Research -- Description: Multiplier with tech mapping ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.stdlib.all; use grlib.multlib.all; library techmap; use techmap.allmul.all; use techmap.gencomp.all; entity techmult is generic ( tech : integer := 0; arch : integer := 0; a_width : positive := 2; -- multiplier word width b_width : positive := 2; -- multiplicand word width num_stages : natural := 2; -- number of pipeline stages stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable ); port(a : in std_logic_vector(a_width-1 downto 0); b : in std_logic_vector(b_width-1 downto 0); clk : in std_logic; en : in std_logic; sign : in std_logic; product : out std_logic_vector(a_width+b_width-1 downto 0)); end; architecture rtl of techmult is signal gnd, vcc : std_ulogic; -- pragma translate_off signal pres : std_ulogic := '0'; signal sonly : std_ulogic := '0'; -- pragma translate_on begin gnd <= '0'; vcc <= '1'; np : if num_stages = 1 generate arch0 : if (arch = 0) generate --inferred product <= mixed_mul(a, b, sign); -- pragma translate_off pres <= '1'; -- pragma translate_on end generate; arch1 : if (arch = 1) generate -- modgen m1717 : if (a_width = 17) and (b_width = 17) generate m17 : mul_17_17 generic map (mulpipe => 0) port map (clk, vcc, a, b, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; m3317 : if (a_width = 33) and (b_width = 17) generate m33 : mul_33_17 port map (a, b, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; m339 : if (a_width = 33) and (b_width = 9) generate m33 : mul_33_9 port map (a, b, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; m3333 : if (a_width = 33) and (b_width = 33) generate m33 : mul_33_33 generic map (mulpipe => 0) port map (clk, vcc, a, b, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; mgen : if not(((a_width = 17) and (b_width = 17)) or ((a_width = 33) and (b_width = 33)) or ((a_width = 33) and (b_width = 17)) or ((a_width = 33) and (b_width = 9))) generate product <= mixed_mul(a, b, sign); -- pragma translate_off pres <= '1'; -- pragma translate_on end generate; end generate; arch2 : if (arch = 2) generate --techspec axd : if (tech = axdsp) and (a_width = 33) and (b_width = 33) generate m33 : axcel_mul_33x33_signed generic map (pipe => 0) port map (a, b, vcc, clk, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; end generate; arch3 : if (arch = 3) generate -- designware dwm : mul_dw generic map (a_width => a_width, b_width => b_width, num_stages => 1, stall_mode => 0) port map (a => a, b => b, clk => clk, en => en, sign => sign, product => product); -- pragma translate_off pres <= '1'; -- pragma translate_on end generate; end generate; pipe2 : if num_stages = 2 generate arch0 : if (arch = 0) generate -- inferred dwm : gen_mult_pipe generic map (a_width => a_width, b_width => b_width, num_stages => num_stages, stall_mode => stall_mode) port map (a => a, b => b, clk => clk, en => en, tc => sign, product => product); -- pragma translate_off pres <= '1'; -- pragma translate_on end generate; arch1 : if (arch = 1) generate -- modgen m1717 : if (a_width = 17) and (b_width = 17) generate m17 : mul_17_17 generic map (mulpipe => 1) port map (clk, en, a, b, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; m3333 : if (a_width = 33) and (b_width = 33) generate m33 : mul_33_33 generic map (mulpipe => 1) port map (clk, en, a, b, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; end generate; arch2 : if (arch = 2) generate --techspec axd : if (tech = axdsp) and (a_width = 33) and (b_width = 33) generate m33 : axcel_mul_33x33_signed generic map (pipe => 1) port map (a, b, en, clk, product); -- pragma translate_off pres <= '1'; sonly <= '1'; -- pragma translate_on end generate; end generate; arch3 : if (arch = 3) generate -- designware dwm : mul_dw generic map (a_width => a_width, b_width => b_width, num_stages => num_stages, stall_mode => stall_mode) port map (a => a, b => b, clk => clk, en => en, sign => sign, product => product); -- pragma translate_off pres <= '1'; -- pragma translate_on end generate; end generate; pipe3 : if num_stages > 2 generate arch0 : if (arch = 0) generate -- inferred dwm : gen_mult_pipe generic map (a_width => a_width, b_width => b_width, num_stages => num_stages, stall_mode => stall_mode) port map (a => a, b => b, clk => clk, en => en, tc => sign, product => product); -- pragma translate_off pres <= '1'; -- pragma translate_on end generate; arch3 : if (arch = 3) generate -- designware dwm : mul_dw generic map (a_width => a_width, b_width => b_width, num_stages => num_stages, stall_mode => stall_mode) port map (a => a, b => b, clk => clk, en => en, sign => sign, product => product); -- pragma translate_off pres <= '1'; -- pragma translate_on end generate; end generate; -- pragma translate_off process begin wait for 5 ns; assert pres = '1' report "techmult: configuration not supported. (width " & tost(a_width) & "x" & tost(b_width) & ", tech " & tost(tech) & ", arch " & tost(arch) & ")" severity failure; wait; end process; process begin wait for 5 ns; assert not ((sonly = '1') and (sign = '0')) report "techmult: unsinged multiplication for this configuration not supported" severity failure; if sonly = '1' then wait on sign; else wait; end if; end process; -- pragma translate_on end;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book entity example_entity is end entity example_entity; -- end not in book architecture contrived of example_entity is constant sig_width : positive := 16; signal s1, s2, s3 : bit_vector (0 to sig_width - 1); signal sel : bit; -- . . . begin mux : block is generic ( width : positive ); generic map ( width => sig_width ); port ( d0, d1 : in bit_vector(0 to width - 1); y : out bit_vector(0 to width - 1); sel : in bit); port map ( d0 => s1, d1=> s2, y => s3, sel => sel ); constant zero : bit_vector(0 to width - 1) := ( others => '0' ); signal gated_d0, gated_d1 : bit_vector(0 to width - 1); begin gated_d0 <= d0 when sel = '0' else zero; gated_d1 <= d1 when sel = '1' else zero; y <= gated_d0 or gated_d1; end block mux; -- . . . -- not in book stimulus : process is begin s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns; s1 <= X"0101"; wait for 10 ns; s2 <= X"0202"; wait for 10 ns; sel <= '1'; wait for 10 ns; s1 <= X"0001"; wait for 10 ns; s2 <= X"0002"; wait for 10 ns; wait; end process stimulus; -- end not in book end architecture contrived;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book entity example_entity is end entity example_entity; -- end not in book architecture contrived of example_entity is constant sig_width : positive := 16; signal s1, s2, s3 : bit_vector (0 to sig_width - 1); signal sel : bit; -- . . . begin mux : block is generic ( width : positive ); generic map ( width => sig_width ); port ( d0, d1 : in bit_vector(0 to width - 1); y : out bit_vector(0 to width - 1); sel : in bit); port map ( d0 => s1, d1=> s2, y => s3, sel => sel ); constant zero : bit_vector(0 to width - 1) := ( others => '0' ); signal gated_d0, gated_d1 : bit_vector(0 to width - 1); begin gated_d0 <= d0 when sel = '0' else zero; gated_d1 <= d1 when sel = '1' else zero; y <= gated_d0 or gated_d1; end block mux; -- . . . -- not in book stimulus : process is begin s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns; s1 <= X"0101"; wait for 10 ns; s2 <= X"0202"; wait for 10 ns; sel <= '1'; wait for 10 ns; s1 <= X"0001"; wait for 10 ns; s2 <= X"0002"; wait for 10 ns; wait; end process stimulus; -- end not in book end architecture contrived;
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- not in book entity example_entity is end entity example_entity; -- end not in book architecture contrived of example_entity is constant sig_width : positive := 16; signal s1, s2, s3 : bit_vector (0 to sig_width - 1); signal sel : bit; -- . . . begin mux : block is generic ( width : positive ); generic map ( width => sig_width ); port ( d0, d1 : in bit_vector(0 to width - 1); y : out bit_vector(0 to width - 1); sel : in bit); port map ( d0 => s1, d1=> s2, y => s3, sel => sel ); constant zero : bit_vector(0 to width - 1) := ( others => '0' ); signal gated_d0, gated_d1 : bit_vector(0 to width - 1); begin gated_d0 <= d0 when sel = '0' else zero; gated_d1 <= d1 when sel = '1' else zero; y <= gated_d0 or gated_d1; end block mux; -- . . . -- not in book stimulus : process is begin s1 <= X"1111"; s2 <= X"2222"; sel <= '0'; wait for 10 ns; s1 <= X"0101"; wait for 10 ns; s2 <= X"0202"; wait for 10 ns; sel <= '1'; wait for 10 ns; s1 <= X"0001"; wait for 10 ns; s2 <= X"0002"; wait for 10 ns; wait; end process stimulus; -- end not in book end architecture contrived;
entity test_output is port ( output : inout bit_vector( 1 downto 0 ) := "10" ); end test_output; architecture only of test_output is begin -- test_output test: process begin -- process test assert output = "10" report "test failed" severity error; assert output /= "10" report "test passed" severity note; wait; end process test; end only;
entity test_output is port ( output : inout bit_vector( 1 downto 0 ) := "10" ); end test_output; architecture only of test_output is begin -- test_output test: process begin -- process test assert output = "10" report "test failed" severity error; assert output /= "10" report "test passed" severity note; wait; end process test; end only;
entity test_output is port ( output : inout bit_vector( 1 downto 0 ) := "10" ); end test_output; architecture only of test_output is begin -- test_output test: process begin -- process test assert output = "10" report "test failed" severity error; assert output /= "10" report "test passed" severity note; wait; end process test; end only;
------------------------------------------------------------------------------- -- Title : Testbench for design "peripheral_register" ------------------------------------------------------------------------------- -- Author : Calle <calle@Alukiste> -- Standard : VHDL'87 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- Copyright (c) 2011 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library std; use std.textio.all; library work; use work.bus_pkg.all; use work.reg_file_pkg.all; ------------------------------------------------------------------------------- entity peripheral_register_tb is end peripheral_register_tb; ------------------------------------------------------------------------------- architecture tb of peripheral_register_tb is -- component generics constant BASE_ADDRESS : positive := 16#0100#; -- component ports signal reg : std_logic_vector(15 downto 0) := (others => '0'); signal bus_o : busdevice_out_type; signal bus_i : busdevice_in_type := (addr => (others => '0'), data => (others => '0'), we => '0', re => '0'); signal clk : std_logic := '0'; signal reg_readback : std_logic_vector(15 downto 0); -- comments for the wave view of the testbench type comment_type is (idle, read_wrong_addr, read_correct_addr, write_wrong_addr, write_correct_addr, sequential_cycles); signal comment : comment_type := idle; begin reg_readback <= not reg; -- component instantiation DUT : peripheral_register generic map ( BASE_ADDRESS => BASE_ADDRESS) port map ( dout_p => reg, din_p => reg_readback, -- read back the written values bus_o => bus_o, bus_i => bus_i, reset => '0', clk => clk); -- clock generation clk <= not clk after 10 ns; waveform : process begin wait for 20 ns; -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); -- Read from correct address comment <= read_correct_addr; readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk); -- Write to wrong address comment <= write_wrong_addr; writeWord(addr => BASE_ADDRESS + 1, data => 16#affe#, bus_i => bus_i, clk => clk); -- Write to correct address comment <= write_correct_addr; writeWord(addr => BASE_ADDRESS, data => 16#54af#, bus_i => bus_i, clk => clk); -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); -- Read from correct address comment <= read_correct_addr; readWord(addr => BASE_ADDRESS, bus_i => bus_i, clk => clk); -- Read from wrong address comment <= read_wrong_addr; readWord(addr => 16#0020#, bus_i => bus_i, clk => clk); wait until rising_edge(clk); -- generate two read cycles directly following each other comment <= sequential_cycles; bus_i.re <= '1'; wait until rising_edge(clk); wait until rising_edge(clk); bus_i.re <= '0'; wait until rising_edge(clk); bus_i.data <= x"4321"; bus_i.we <= '1'; wait until rising_edge(clk); bus_i.we <= '0'; wait until rising_edge(clk); bus_i.re <= '1'; wait until rising_edge(clk); bus_i.re <= '0'; end process waveform; end tb;
-------------------------------------------------------------------------------- -- -- File: -- DVITransmitter.vhd -- -- Module: -- DVITransmitter -- -- Author: -- Elod Gyorgy -- -- Date: -- 04/06/2011 -- -- Description: -- DVITransmitter takes 24-bit RGB video data with proper sync -- signals and transmits them on a DVI or HDMI port. The encoding and serialization -- is done according to the Digital Visual Interface (DVI) specifications Rev 1.0. -- -- Copyright notice: -- Copyright (C) 2014 Digilent Inc. -- -- License: -- This program is free software; distributed under the terms of -- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License") -- -- Redistribution and use in source and binary forms, with or without modification, -- are permitted provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright notice, this -- list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above copyright notice, -- this list of conditions and the following disclaimer in the documentation -- and/or other materials provided with the distribution. -- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names -- of its contributors may be used to endorse or promote products derived -- from this software without specific prior written permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED -- OF THE POSSIBILITY OF SUCH DAMAGE. -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --library digilent; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. library UNISIM; use UNISIM.VComponents.all; entity DVITransmitter is Generic (FAMILY : STRING := "spartan6"); Port ( RED_I : in STD_LOGIC_VECTOR (7 downto 0); GREEN_I : in STD_LOGIC_VECTOR (7 downto 0); BLUE_I : in STD_LOGIC_VECTOR (7 downto 0); HS_I : in STD_LOGIC; VS_I : in STD_LOGIC; VDE_I : in STD_LOGIC; RST_I : in STD_LOGIC; PCLK_I : in STD_LOGIC; PCLK_X5_I : in STD_LOGIC; TMDS_TX_CLK_P : out STD_LOGIC; TMDS_TX_CLK_N : out STD_LOGIC; TMDS_TX_2_P : out STD_LOGIC; TMDS_TX_2_N : out STD_LOGIC; TMDS_TX_1_P : out STD_LOGIC; TMDS_TX_1_N : out STD_LOGIC; TMDS_TX_0_P : out STD_LOGIC; TMDS_TX_0_N : out STD_LOGIC); end DVITransmitter; architecture Behavioral of DVITransmitter is signal intTmdsRed, intTmdsGreen, intTmdsBlue : std_logic_vector(9 downto 0); signal tmds_p, tmds_n : std_logic_vector(3 downto 0); signal int_rst, SerClk : std_logic; constant CLKIN_PERIOD : REAL := 13.468; --ns = 74.25MHz (maximum supported pixel clock) constant N : NATURAL := 10; --serialization factor constant PLLO0 : NATURAL := 1; -- SERCLK = PCLK * N constant PLLO2 : NATURAL := PLLO0 * N; -- PCLK = PCLK * N / N constant PLLO3 : NATURAL := PLLO0 * N / 2; -- PCLK_X2 = PLCK * N / (N/2) signal intfb, intfb_buf, intpllout_x2, pllout_xs, pllout_x1, pllout_x2: std_logic; signal PClk, PClk_x2, PllLckd, PllRst, intRst, BufPllLckd, SerStb : std_logic; component SerializerN_1 is Generic ( N : NATURAL := 10; FAMILY : STRING := "spartan6"); Port ( DP_I : in STD_LOGIC_VECTOR (N-1 downto 0); CLKDIV_I : in STD_LOGIC; --parallel slow clock CLKDIV_X2_I : in STD_LOGIC; --double parallel slow clock (CLKDIV_I x 2) REQUIRED ONLY FOR Spartan-6 SERCLK_I : in STD_LOGIC; --serial fast clock (CLK_I = CLKDIV_I x N / 2) SERSTB_I : in STD_LOGIC; -- REQUIRED ONLY FOR Spartan-6 RST_I : in STD_LOGIC; --async reset DSP_O : out STD_LOGIC; DSN_O : out STD_LOGIC); end component; component TMDSEncoder is Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0); C0_I : in STD_LOGIC; C1_I : in STD_LOGIC; DE_I : in STD_LOGIC; CLK_I: in STD_LOGIC; RST_I: in STD_LOGIC; D_O : out STD_LOGIC_VECTOR (9 downto 0)); end component; begin PllRst <= RST_I; family_s6: if FAMILY = "spartan6" generate begin ---------------------------------------------------------------------------------- -- Serialization PLL -- This PLL generates the x2 and x10 pixel clock needed for TMDS serialization ---------------------------------------------------------------------------------- Inst_10_1_pll : PLL_BASE generic map( BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized" CLKFBOUT_MULT => N, -- multiplication factor for all output clocks COMPENSATION => "INTERNAL", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM" DIVCLK_DIVIDE => 1, -- division factor for all clocks (1 to 52) CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks CLK_FEEDBACK => "CLKFBOUT", CLKIN_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1 CLKOUT0_DIVIDE => PLLO0, -- division factor for clkout0 (1 to 128) CLKOUT2_DIVIDE => PLLO2, -- division factor for clkout2 (1 to 128) CLKOUT3_DIVIDE => PLLO3, -- division factor for clkout3 (1 to 128) REF_JITTER => 0.025) -- input reference jitter (0.000 to 0.999 ui%) port map ( CLKFBOUT => intfb, -- general output feedback signal CLKFBIN => intfb_buf, -- clock feedback input CLKOUT0 => pllout_xs, -- x10 clock for transmitter CLKOUT1 => open, CLKOUT2 => pllout_x1, -- x1 clock for BUFG CLKOUT3 => pllout_x2, -- x2 clock for BUFG CLKOUT4 => open, -- one of six general clock output signals CLKOUT5 => open, -- one of six general clock output signals LOCKED => PllLckd, -- active high pll lock signal CLKIN => PCLK_I, -- primary clock input RST => PllRst); -- asynchronous pll reset intfb_buf <= intfb; ---------------------------------------------------------------------------------- -- Route the pixel clock and 2x pixel clock through the global clock network ---------------------------------------------------------------------------------- BUFG_inst1 : BUFG port map ( O => PClk, I => pllout_x1 ); BUFG_inst2 : BUFG port map ( O => intpllout_x2, I => pllout_x2 ); PClk_x2 <= intpllout_x2; ---------------------------------------------------------------------------------- -- Route High-Speed serialization clock to OSERDES2 primitives in the whole bank ---------------------------------------------------------------------------------- BUFPLL_inst : BUFPLL generic map ( DIVIDE => N/2, -- DIVCLK divider (1-8) ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE) ) port map ( IOCLK => SerClk, -- 1-bit Output I/O clock LOCK => BufPllLckd, -- 1-bit Synchronized LOCK output SERDESSTROBE => SerStb, -- 1-bit Output SERDES strobe (connect to ISERDES/OSERDES) GCLK => intpllout_x2, -- 1-bit BUFG clock input LOCKED => PllLckd, -- 1-bit LOCKED input from PLL PLLIN => pllout_xs -- 1-bit Clock input from PLL ); intRst <= not BufPllLckd or not PllLckd; end generate family_s6; family_7: if FAMILY = "kintex7" or FAMILY = "artix7" or FAMILY = "virtex7" generate begin ---------------------------------------------------------------------------------- -- Serialization PLL -- This PLL generates the x5 pixel clock needed for TMDS serialization on series-7 -- architectures. ---------------------------------------------------------------------------------- -- PLLE2_BASE_inst : PLLE2_BASE -- generic map ( -- BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) -- STARTUP_WAIT => "FALSE", -- Delays DONE until MMCM is locked (FALSE, TRUE) -- -- CLKFBOUT_MULT => 10, -- Multiply value for all CLKOUT (2.000-64.000). -- CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000). -- DIVCLK_DIVIDE => 1, -- Master division value (1-106) -- CLKIN1_PERIOD => 9.259, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). -- -- CLKOUT0_DIVIDE => 2, -- CLKOUT0_PHASE => 0.000, -- CLKOUT0_DUTY_CYCLE => 0.500, -- CLKOUT1_DIVIDE => 10, -- CLKOUT1_PHASE => 0.000, -- CLKOUT1_DUTY_CYCLE => 0.500, -- -- REF_JITTER1 => 0.010 -- Reference input jitter in UI (0.000-0.999). -- ) -- port map ( -- -- Clock Outputs: 1-bit (each) output: User configurable clock outputs -- CLKOUT0 => pllout_xs, -- Serial Clock = Parallel Clock x 5 (DDR) -- CLKOUT1 => pllout_x1, -- Parallel Clock Buffered, Phase-aligned with Serial Clock -- CLKOUT2 => open, -- 1-bit output: CLKOUT2 -- CLKOUT3 => open, -- 1-bit output: CLKOUT3 -- CLKOUT4 => open, -- 1-bit output: CLKOUT4 -- CLKOUT5 => open, -- 1-bit output: CLKOUT5 -- -- Feedback Clocks: 1-bit (each) output: Clock feedback ports -- CLKFBOUT => intfb, -- 1-bit output: Feedback clock -- -- Status Ports: 1-bit (each) output: MMCM status ports -- LOCKED => PllLckd, -- 1-bit output: LOCK -- -- Clock Inputs: 1-bit (each) input: Clock input -- CLKIN1 => PCLK_I, -- 1-bit input: Clock -- -- Control Ports: 1-bit (each) input: MMCM control ports -- PWRDWN => '0', -- 1-bit input: Power-down -- RST => PllRst, -- 1-bit input: Reset -- -- Feedback Clocks: 1-bit (each) input: Clock feedback ports -- CLKFBIN => intfb_buf -- 1-bit input: Feedback clock -- ); -- -- Output buffering -- ------------------------------------- -- clkf_buf : BUFG -- port map -- (O => intfb_buf, -- I => intfb); -- -- -- clkout0_buf : BUFG -- port map -- (O => SerClk, -- I => pllout_xs); -- -- -- -- clkout1_buf : BUFG -- port map -- (O => PClk, -- I => pllout_x1); -- --intRst <= not PllLckd; PClk <= PCLK_I; SerClk <= PCLK_X5_I; intRst <= RST_I; end generate family_7; ---------------------------------------------------------------------------------- -- DVI Encoder; DVI 1.0 Specifications -- This component encodes 24-bit RGB video frames with sync signals into 10-bit -- TMDS characters. ---------------------------------------------------------------------------------- Inst_TMDSEncoder_red: TMDSEncoder PORT MAP( D_I => RED_I, C0_I => '0', C1_I => '0', DE_I => VDE_I, CLK_I => PClk, RST_I => intRst, D_O => intTmdsRed ); Inst_TMDSEncoder_green: TMDSEncoder PORT MAP( D_I => GREEN_I, C0_I => '0', C1_I => '0', DE_I => VDE_I, CLK_I => PClk, RST_I => intRst, D_O => intTmdsGreen ); Inst_TMDSEncoder_blue: TMDSEncoder PORT MAP( D_I => BLUE_I, C0_I => HS_I, C1_I => VS_I, DE_I => VDE_I, CLK_I => PClk, RST_I => intRst, D_O => intTmdsBlue ); ---------------------------------------------------------------------------------- -- TMDS serializer; ratio of 10:1; 3 data & 1 clock channel -- Since the TMDS clock's period is character-long (10-bit periods), the -- serialization of "1111100000" will result in a 10-bit long clock period. ---------------------------------------------------------------------------------- Inst_clk_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY) PORT MAP( DP_I => "1111100000", CLKDIV_I => PClk, CLKDIV_X2_I => PClk_x2, SERCLK_I => SerClk, SERSTB_I => SerStb, RST_I => intRst, DSP_O => TMDS_TX_CLK_P, DSN_O => TMDS_TX_CLK_N ); Inst_d2_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY) PORT MAP( DP_I => intTmdsRed, CLKDIV_I => PClk, CLKDIV_X2_I => PClk_x2, SERCLK_I => SerClk, SERSTB_I => SerStb, RST_I => intRst, DSP_O => TMDS_TX_2_P, DSN_O => TMDS_TX_2_N ); Inst_d1_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY) PORT MAP( DP_I => intTmdsGreen, CLKDIV_I => PClk, CLKDIV_X2_I => PClk_x2, SERCLK_I => SerClk, SERSTB_I => SerStb, RST_I => intRst, DSP_O => TMDS_TX_1_P, DSN_O => TMDS_TX_1_N ); Inst_d0_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY) PORT MAP( DP_I => intTmdsBlue, CLKDIV_I => PClk, CLKDIV_X2_I => PClk_x2, SERCLK_I => SerClk, SERSTB_I => SerStb, RST_I => intRst, DSP_O => TMDS_TX_0_P, DSN_O => TMDS_TX_0_N ); end Behavioral;
------------------------------------------------------------------------------ -- LEON3 Demonstration design -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use grlib.stdlib.all; library techmap; use techmap.gencomp.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; use gaisler.jtag.all; library esa; use esa.memoryctrl.all; use work.config.all; entity leon3mp is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; ncpu : integer := CFG_NCPU; disas : integer := CFG_DISAS; -- Enable disassembly to console dbguart : integer := CFG_DUART; -- Print UART on console pclow : integer := CFG_PCLOW; freq : integer := 50000 -- frequency of main clock (used for PLLs) ); port ( resetn : in std_ulogic; clk : in std_ulogic; errorn : out std_ulogic; -- Shared bus address : out std_logic_vector(23 downto 0); data : inout std_logic_vector(31 downto 0); -- SRAM ramsn : out std_ulogic; ramoen : out std_ulogic; rwen : out std_ulogic; mben : out std_logic_vector(3 downto 0); -- pragma translate_off iosn : out std_ulogic; -- pragma translate_on -- FLASH romsn : out std_ulogic; oen : out std_ulogic; writen : out std_ulogic; byten : out std_ulogic; wpn : out std_ulogic; sa : out std_logic_vector(11 downto 0); sd : inout std_logic_vector(31 downto 0); sdclk : out std_ulogic; sdcke : out std_logic; -- sdram clock enable sdcsn : out std_logic; -- sdram chip select sdwen : out std_ulogic; -- sdram write enable sdrasn : out std_ulogic; -- sdram ras sdcasn : out std_ulogic; -- sdram cas sddqm : out std_logic_vector (3 downto 0); -- sdram dqm sdba : out std_logic_vector(1 downto 0); -- sdram bank address -- debug support unit dsutx : out std_ulogic; -- DSU tx data dsurx : in std_ulogic; -- DSU rx data dsubren : in std_ulogic; dsuact : out std_ulogic; -- console UART rxd1 : in std_ulogic; txd1 : out std_ulogic; -- for smsc lan chip eth_aen : out std_logic; eth_readn : out std_logic; eth_writen: out std_logic; eth_nbe : out std_logic_vector(3 downto 0); eth_lclk : out std_ulogic; eth_nads : out std_logic; eth_ncycle : out std_logic; eth_wnr : out std_logic; eth_nvlbus : out std_logic; eth_nrdyrtn : out std_logic; eth_ndatacs : out std_logic; gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port ); end; architecture rtl of leon3mp is constant blength : integer := 12; constant fifodepth : integer := 8; constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG; signal vcc, gnd : std_logic_vector(7 downto 0); signal memi : memory_in_type; signal memo : memory_out_type; signal wpo : wprot_out_type; signal sdi : sdctrl_in_type; signal sdo : sdram_out_type; signal sdo2 : sdctrl_out_type; --for smc lan chip signal s_eth_aen : std_logic; signal s_eth_readn : std_logic; signal s_eth_writen: std_logic; signal s_eth_nbe : std_logic_vector(3 downto 0); signal apbi : apb_slv_in_type; signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal clkm, rstn, sdclkl : std_ulogic; signal cgi : clkgen_in_type; signal cgo : clkgen_out_type; signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to NCPU-1); signal irqo : irq_out_vector(0 to NCPU-1); signal dbgi : l3_debug_in_vector(0 to NCPU-1); signal dbgo : l3_debug_out_vector(0 to NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; signal gpti : gptimer_in_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; constant IOAEN : integer := 1; constant CFG_SDEN : integer := CFG_MCTRL_SDEN ; constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK; signal dsubre : std_ulogic; component smc_mctrl generic ( hindex : integer := 0; pindex : integer := 0; romaddr : integer := 16#000#; rommask : integer := 16#E00#; ioaddr : integer := 16#200#; iomask : integer := 16#E00#; ramaddr : integer := 16#400#; rammask : integer := 16#C00#; paddr : integer := 0; pmask : integer := 16#fff#; wprot : integer := 0; invclk : integer := 0; fast : integer := 0; romasel : integer := 28; sdrasel : integer := 29; srbanks : integer := 4; ram8 : integer := 0; ram16 : integer := 0; sden : integer := 0; sepbus : integer := 0; sdbits : integer := 32; sdlsb : integer := 2; oepol : integer := 0; syncrst : integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; memi : in memory_in_type; memo : out memory_out_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; wpo : in wprot_out_type; sdo : out sdram_out_type; eth_aen : out std_ulogic; -- for smsc lan chip eth_readn : out std_ulogic; -- for smsc lan chip eth_writen: out std_ulogic; -- for smsc lan chip eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip ); end component; begin ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- vcc <= (others => '1'); gnd <= (others => '0'); cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0'; clkgen0 : clkgen -- clock generator using toplevel generic 'freq' generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN, noclkfb => CFG_CLK_NOFB, freq => freq) port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => open, clk2x => open, sdclk => sdclkl, pciclk => open, cgi => cgi, cgo => cgo); sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl); rst0 : rstgen -- reset generator port map (resetn, clkm, cgo.clklock, rstn); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, nahbm => maxahbm, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- l3 : if CFG_LEON3 = 1 generate cpu : for i in 0 to NCPU-1 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); end generate; errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error); dsugen : if CFG_DSU = 1 generate dsu0 : dsu3 -- LEON3 Debug Support Unit generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); end generate; end generate; nodsu : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; end generate; dcomgen : if CFG_AHB_UART = 1 generate dcom0 : ahbuart -- Debug UART generic map (hindex => NCPU, pindex => 4, paddr => 7) port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU)); dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd); dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd); end generate; nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate; ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), open, open, open, open, open, open, open, gnd(0)); end generate; ---------------------------------------------------------------------- --- Memory controllers ---------------------------------------------- ---------------------------------------------------------------------- src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS, romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#, prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW) port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2); apbo(0) <= apb_none; end generate; mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0, srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64) port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo, s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe); sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller sd2 : if CFG_MCTRL_SEPBUS = 1 generate sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0)); sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13)); bdr : for i in 0 to 3 generate sd_pad : iopadv generic map (tech => padtech, width => 8) port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8)); sd2 : if CFG_MCTRL_SD64 = 1 generate sd_pad2 : iopadv generic map (tech => padtech, width => 8) port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32)); end generate; end generate; end generate; sdwen_pad : outpad generic map (tech => padtech) port map (sdwen, sdo.sdwen); sdras_pad : outpad generic map (tech => padtech) port map (sdrasn, sdo.rasn); sdcas_pad : outpad generic map (tech => padtech) port map (sdcasn, sdo.casn); sddqm_pad : outpadv generic map (width =>4, tech => padtech) port map (sddqm, sdo.dqm(3 downto 0)); end generate; sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0)); sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0)); end generate; wpn <= '1'; byten <= '0'; nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, vcc(0)); sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, vcc(0)); end generate; memi.brdyn <= '1'; memi.bexcn <= '1'; memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00"; mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads apbo(0) <= apb_none; ahbso(0) <= ahbs_none; rams_pad : outpad generic map (tech => padtech) port map (ramsn, vcc(0)); roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0)); end generate; mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads addr_pad : outpadv generic map (width => 24, tech => padtech) port map (address, memo.address(23 downto 0)); memb_pad : outpadv generic map (width => 4, tech => padtech) port map (mben, memo.mben); rams_pad : outpad generic map (tech => padtech) port map (ramsn, memo.ramsn(0)); roms_pad : outpad generic map (tech => padtech) port map (romsn, memo.romsn(0)); oen_pad : outpad generic map (tech => padtech) port map (oen, memo.oen); rwen_pad : outpad generic map (tech => padtech) port map (rwen, memo.wrn(0)); roen_pad : outpad generic map (tech => padtech) port map (ramoen, memo.ramoen(0)); wri_pad : outpad generic map (tech => padtech) port map (writen, memo.writen); -- pragma translate_off iosn_pad : outpad generic map (tech => padtech) port map (iosn, memo.iosn); -- pragma translate_on -- for smc lan chip eth_aen_pad : outpad generic map (tech => padtech) port map (eth_aen, s_eth_aen); eth_readn_pad : outpad generic map (tech => padtech) port map (eth_readn, s_eth_readn); eth_writen_pad : outpad generic map (tech => padtech) port map (eth_writen, s_eth_writen); eth_nbe_pad : outpadv generic map (width => 4, tech => padtech) port map (eth_nbe, s_eth_nbe); bdr : for i in 0 to 3 generate data_pad : iopadv generic map (tech => padtech, width => 8) port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); end generate; end generate; ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); ua1 : if CFG_UART1_ENABLE /= 0 generate uart1 : apbuart -- UART 1 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO) port map (rstn, clkm, apbi, apbo(1), u1i, u1o); u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller generic map (pindex => 2, paddr => 2, ncpu => NCPU) port map (rstn, clkm, apbi, apbo(2), irqo, irqi); end generate; irq3 : if CFG_IRQ3_ENABLE = 0 generate x : for i in 0 to NCPU-1 generate irqi(i).irl <= "0000"; end generate; apbo(2) <= apb_none; end generate; gpt : if CFG_GPT_ENABLE /= 0 generate timer0 : gptimer -- timer unit generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW) port map (rstn, clkm, apbi, apbo(3), gpti, open); gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; end generate; notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5), gpioi => gpioi, gpioo => gpioo); pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate pio_pad : iopad generic map (tech => padtech) port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; ----------------------------------------------------------------------- --- AHB ROM ---------------------------------------------------------- ----------------------------------------------------------------------- bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) port map ( rstn, clkm, ahbsi, ahbso(6)); end generate; nobpromgen : if CFG_AHBROMEN = 0 generate ahbso(6) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- ahbramgen : if CFG_AHBRAMEN = 1 generate ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map (rstn, clkm, ahbsi, ahbso(3)); end generate; nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate; ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate ahbmo(i) <= ahbm_none; end generate; nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate; nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate; -- invert signal for input via a key dsubre <= not dsubren; -- for smc lan chip eth_lclk <= vcc(0); eth_nads <= gnd(0); eth_ncycle <= vcc(0); eth_wnr <= vcc(0); eth_nvlbus <= vcc(0); eth_nrdyrtn <= vcc(0); eth_ndatacs <= vcc(0); ----------------------------------------------------------------------- --- Boot message ---------------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off x : report_design generic map ( msg1 => "LEON3 Altera EP2C60 SDR Demonstration design", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); -- pragma translate_on end;
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 -- Date : Wed Mar 01 09:52:04 2017 -- Host : GILAMONSTER running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl -- Design : system_ov7670_controller_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z010clg400-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_controller_0_0_i2c_sender is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); sioc : out STD_LOGIC; p_0_in : out STD_LOGIC; \busy_sr_reg[1]_0\ : out STD_LOGIC; siod : out STD_LOGIC; \busy_sr_reg[31]_0\ : in STD_LOGIC; clk : in STD_LOGIC; p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 ); DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 ); \busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender"; end system_ov7670_controller_0_0_i2c_sender; architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is signal busy_sr0 : STD_LOGIC; signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC; signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC; signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC; signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC; signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC; signal \^busy_sr_reg[1]_0\ : STD_LOGIC; signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC; signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC; signal \data_sr[10]_i_1_n_0\ : STD_LOGIC; signal \data_sr[12]_i_1_n_0\ : STD_LOGIC; signal \data_sr[13]_i_1_n_0\ : STD_LOGIC; signal \data_sr[14]_i_1_n_0\ : STD_LOGIC; signal \data_sr[15]_i_1_n_0\ : STD_LOGIC; signal \data_sr[16]_i_1_n_0\ : STD_LOGIC; signal \data_sr[17]_i_1_n_0\ : STD_LOGIC; signal \data_sr[18]_i_1_n_0\ : STD_LOGIC; signal \data_sr[19]_i_1_n_0\ : STD_LOGIC; signal \data_sr[22]_i_1_n_0\ : STD_LOGIC; signal \data_sr[27]_i_1_n_0\ : STD_LOGIC; signal \data_sr[30]_i_1_n_0\ : STD_LOGIC; signal \data_sr[31]_i_1_n_0\ : STD_LOGIC; signal \data_sr[31]_i_2_n_0\ : STD_LOGIC; signal \data_sr[3]_i_1_n_0\ : STD_LOGIC; signal \data_sr[4]_i_1_n_0\ : STD_LOGIC; signal \data_sr[5]_i_1_n_0\ : STD_LOGIC; signal \data_sr[6]_i_1_n_0\ : STD_LOGIC; signal \data_sr[7]_i_1_n_0\ : STD_LOGIC; signal \data_sr[8]_i_1_n_0\ : STD_LOGIC; signal \data_sr[9]_i_1_n_0\ : STD_LOGIC; signal \data_sr_reg_n_0_[10]\ : STD_LOGIC; signal \data_sr_reg_n_0_[11]\ : STD_LOGIC; signal \data_sr_reg_n_0_[12]\ : STD_LOGIC; signal \data_sr_reg_n_0_[13]\ : STD_LOGIC; signal \data_sr_reg_n_0_[14]\ : STD_LOGIC; signal \data_sr_reg_n_0_[15]\ : STD_LOGIC; signal \data_sr_reg_n_0_[16]\ : STD_LOGIC; signal \data_sr_reg_n_0_[17]\ : STD_LOGIC; signal \data_sr_reg_n_0_[18]\ : STD_LOGIC; signal \data_sr_reg_n_0_[19]\ : STD_LOGIC; signal \data_sr_reg_n_0_[1]\ : STD_LOGIC; signal \data_sr_reg_n_0_[20]\ : STD_LOGIC; signal \data_sr_reg_n_0_[21]\ : STD_LOGIC; signal \data_sr_reg_n_0_[22]\ : STD_LOGIC; signal \data_sr_reg_n_0_[23]\ : STD_LOGIC; signal \data_sr_reg_n_0_[24]\ : STD_LOGIC; signal \data_sr_reg_n_0_[25]\ : STD_LOGIC; signal \data_sr_reg_n_0_[26]\ : STD_LOGIC; signal \data_sr_reg_n_0_[27]\ : STD_LOGIC; signal \data_sr_reg_n_0_[28]\ : STD_LOGIC; signal \data_sr_reg_n_0_[29]\ : STD_LOGIC; signal \data_sr_reg_n_0_[2]\ : STD_LOGIC; signal \data_sr_reg_n_0_[30]\ : STD_LOGIC; signal \data_sr_reg_n_0_[31]\ : STD_LOGIC; signal \data_sr_reg_n_0_[3]\ : STD_LOGIC; signal \data_sr_reg_n_0_[4]\ : STD_LOGIC; signal \data_sr_reg_n_0_[5]\ : STD_LOGIC; signal \data_sr_reg_n_0_[6]\ : STD_LOGIC; signal \data_sr_reg_n_0_[7]\ : STD_LOGIC; signal \data_sr_reg_n_0_[8]\ : STD_LOGIC; signal \data_sr_reg_n_0_[9]\ : STD_LOGIC; signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 ); signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal \^p_0_in\ : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 ); signal sioc_i_1_n_0 : STD_LOGIC; signal sioc_i_2_n_0 : STD_LOGIC; signal sioc_i_3_n_0 : STD_LOGIC; signal sioc_i_4_n_0 : STD_LOGIC; signal sioc_i_5_n_0 : STD_LOGIC; signal siod_INST_0_i_1_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4"; attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3"; begin \busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\; p_0_in <= \^p_0_in\; \busy_sr[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"4000FFFF40004000" ) port map ( I0 => \busy_sr[0]_i_3_n_0\, I1 => \divider_reg__0\(6), I2 => \divider_reg__0\(7), I3 => \^p_0_in\, I4 => \^busy_sr_reg[1]_0\, I5 => p_1_in(0), O => busy_sr0 ); \busy_sr[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \divider_reg__1\(4), I1 => \divider_reg__1\(2), I2 => \divider_reg__1\(0), I3 => \divider_reg__1\(1), I4 => \divider_reg__1\(3), I5 => \divider_reg__1\(5), O => \busy_sr[0]_i_3_n_0\ ); \busy_sr[0]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \divider_reg__1\(2), I1 => \divider_reg__1\(3), I2 => \divider_reg__1\(0), I3 => \divider_reg__1\(1), I4 => \busy_sr[0]_i_5_n_0\, O => \^busy_sr_reg[1]_0\ ); \busy_sr[0]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \divider_reg__1\(5), I1 => \divider_reg__1\(4), I2 => \divider_reg__0\(7), I3 => \divider_reg__0\(6), O => \busy_sr[0]_i_5_n_0\ ); \busy_sr[10]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[9]\, I1 => \^p_0_in\, O => \busy_sr[10]_i_1_n_0\ ); \busy_sr[11]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[10]\, I1 => \^p_0_in\, O => \busy_sr[11]_i_1_n_0\ ); \busy_sr[12]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[11]\, I1 => \^p_0_in\, O => \busy_sr[12]_i_1_n_0\ ); \busy_sr[13]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[12]\, I1 => \^p_0_in\, O => \busy_sr[13]_i_1_n_0\ ); \busy_sr[14]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[13]\, I1 => \^p_0_in\, O => \busy_sr[14]_i_1_n_0\ ); \busy_sr[15]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[14]\, I1 => \^p_0_in\, O => \busy_sr[15]_i_1_n_0\ ); \busy_sr[16]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[15]\, I1 => \^p_0_in\, O => \busy_sr[16]_i_1_n_0\ ); \busy_sr[17]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[16]\, I1 => \^p_0_in\, O => \busy_sr[17]_i_1_n_0\ ); \busy_sr[18]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[17]\, I1 => \^p_0_in\, O => \busy_sr[18]_i_1_n_0\ ); \busy_sr[19]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[18]\, I1 => \^p_0_in\, O => \busy_sr[19]_i_1_n_0\ ); \busy_sr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[0]\, I1 => \^p_0_in\, O => \busy_sr[1]_i_1_n_0\ ); \busy_sr[20]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => p_1_in_0(0), I1 => \^p_0_in\, O => \busy_sr[20]_i_1_n_0\ ); \busy_sr[21]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => p_1_in_0(1), I1 => \^p_0_in\, O => \busy_sr[21]_i_1_n_0\ ); \busy_sr[22]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[21]\, I1 => \^p_0_in\, O => \busy_sr[22]_i_1_n_0\ ); \busy_sr[23]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[22]\, I1 => \^p_0_in\, O => \busy_sr[23]_i_1_n_0\ ); \busy_sr[24]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[23]\, I1 => \^p_0_in\, O => \busy_sr[24]_i_1_n_0\ ); \busy_sr[25]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[24]\, I1 => \^p_0_in\, O => \busy_sr[25]_i_1_n_0\ ); \busy_sr[26]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[25]\, I1 => \^p_0_in\, O => \busy_sr[26]_i_1_n_0\ ); \busy_sr[27]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[26]\, I1 => \^p_0_in\, O => \busy_sr[27]_i_1_n_0\ ); \busy_sr[28]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[27]\, I1 => \^p_0_in\, O => \busy_sr[28]_i_1_n_0\ ); \busy_sr[29]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[28]\, I1 => \^p_0_in\, O => \busy_sr[29]_i_1_n_0\ ); \busy_sr[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[1]\, I1 => \^p_0_in\, O => \busy_sr[2]_i_1_n_0\ ); \busy_sr[30]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[29]\, I1 => \^p_0_in\, O => \busy_sr[30]_i_1_n_0\ ); \busy_sr[31]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"22222222A2222222" ) port map ( I0 => p_1_in(0), I1 => \^busy_sr_reg[1]_0\, I2 => \^p_0_in\, I3 => \divider_reg__0\(7), I4 => \divider_reg__0\(6), I5 => \busy_sr[0]_i_3_n_0\, O => \busy_sr[31]_i_1_n_0\ ); \busy_sr[31]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^p_0_in\, I1 => \busy_sr_reg_n_0_[30]\, O => \busy_sr[31]_i_2_n_0\ ); \busy_sr[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[2]\, I1 => \^p_0_in\, O => \busy_sr[3]_i_1_n_0\ ); \busy_sr[4]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[3]\, I1 => \^p_0_in\, O => \busy_sr[4]_i_1_n_0\ ); \busy_sr[5]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[4]\, I1 => \^p_0_in\, O => \busy_sr[5]_i_1_n_0\ ); \busy_sr[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[5]\, I1 => \^p_0_in\, O => \busy_sr[6]_i_1_n_0\ ); \busy_sr[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[6]\, I1 => \^p_0_in\, O => \busy_sr[7]_i_1_n_0\ ); \busy_sr[8]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[7]\, I1 => \^p_0_in\, O => \busy_sr[8]_i_1_n_0\ ); \busy_sr[9]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \busy_sr_reg_n_0_[8]\, I1 => \^p_0_in\, O => \busy_sr[9]_i_1_n_0\ ); \busy_sr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => p_1_in(0), Q => \busy_sr_reg_n_0_[0]\, R => '0' ); \busy_sr_reg[10]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[10]_i_1_n_0\, Q => \busy_sr_reg_n_0_[10]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[11]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[11]_i_1_n_0\, Q => \busy_sr_reg_n_0_[11]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[12]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[12]_i_1_n_0\, Q => \busy_sr_reg_n_0_[12]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[13]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[13]_i_1_n_0\, Q => \busy_sr_reg_n_0_[13]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[14]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[14]_i_1_n_0\, Q => \busy_sr_reg_n_0_[14]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[15]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[15]_i_1_n_0\, Q => \busy_sr_reg_n_0_[15]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[16]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[16]_i_1_n_0\, Q => \busy_sr_reg_n_0_[16]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[17]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[17]_i_1_n_0\, Q => \busy_sr_reg_n_0_[17]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[18]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[18]_i_1_n_0\, Q => \busy_sr_reg_n_0_[18]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[19]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[19]_i_1_n_0\, Q => p_1_in_0(0), S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[1]_i_1_n_0\, Q => \busy_sr_reg_n_0_[1]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[20]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[20]_i_1_n_0\, Q => p_1_in_0(1), S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[21]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[21]_i_1_n_0\, Q => \busy_sr_reg_n_0_[21]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[22]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[22]_i_1_n_0\, Q => \busy_sr_reg_n_0_[22]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[23]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[23]_i_1_n_0\, Q => \busy_sr_reg_n_0_[23]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[24]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[24]_i_1_n_0\, Q => \busy_sr_reg_n_0_[24]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[25]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[25]_i_1_n_0\, Q => \busy_sr_reg_n_0_[25]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[26]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[26]_i_1_n_0\, Q => \busy_sr_reg_n_0_[26]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[27]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[27]_i_1_n_0\, Q => \busy_sr_reg_n_0_[27]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[28]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[28]_i_1_n_0\, Q => \busy_sr_reg_n_0_[28]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[29]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[29]_i_1_n_0\, Q => \busy_sr_reg_n_0_[29]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[2]_i_1_n_0\, Q => \busy_sr_reg_n_0_[2]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[30]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[30]_i_1_n_0\, Q => \busy_sr_reg_n_0_[30]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[31]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[31]_i_2_n_0\, Q => \^p_0_in\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[3]_i_1_n_0\, Q => \busy_sr_reg_n_0_[3]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[4]_i_1_n_0\, Q => \busy_sr_reg_n_0_[4]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[5]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[5]_i_1_n_0\, Q => \busy_sr_reg_n_0_[5]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[6]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[6]_i_1_n_0\, Q => \busy_sr_reg_n_0_[6]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[7]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[7]_i_1_n_0\, Q => \busy_sr_reg_n_0_[7]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[8]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[8]_i_1_n_0\, Q => \busy_sr_reg_n_0_[8]\, S => \busy_sr[31]_i_1_n_0\ ); \busy_sr_reg[9]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => clk, CE => busy_sr0, D => \busy_sr[9]_i_1_n_0\, Q => \busy_sr_reg_n_0_[9]\, S => \busy_sr[31]_i_1_n_0\ ); \data_sr[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[9]\, I1 => \^p_0_in\, I2 => DOADO(7), O => \data_sr[10]_i_1_n_0\ ); \data_sr[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[11]\, I1 => \^p_0_in\, I2 => DOADO(8), O => \data_sr[12]_i_1_n_0\ ); \data_sr[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[12]\, I1 => \^p_0_in\, I2 => DOADO(9), O => \data_sr[13]_i_1_n_0\ ); \data_sr[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[13]\, I1 => \^p_0_in\, I2 => DOADO(10), O => \data_sr[14]_i_1_n_0\ ); \data_sr[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[14]\, I1 => \^p_0_in\, I2 => DOADO(11), O => \data_sr[15]_i_1_n_0\ ); \data_sr[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[15]\, I1 => \^p_0_in\, I2 => DOADO(12), O => \data_sr[16]_i_1_n_0\ ); \data_sr[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[16]\, I1 => \^p_0_in\, I2 => DOADO(13), O => \data_sr[17]_i_1_n_0\ ); \data_sr[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[17]\, I1 => \^p_0_in\, I2 => DOADO(14), O => \data_sr[18]_i_1_n_0\ ); \data_sr[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[18]\, I1 => \^p_0_in\, I2 => DOADO(15), O => \data_sr[19]_i_1_n_0\ ); \data_sr[22]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CFCFCFCFAACAAAAA" ) port map ( I0 => \data_sr_reg_n_0_[22]\, I1 => \data_sr_reg_n_0_[21]\, I2 => \^p_0_in\, I3 => \data_sr[31]_i_2_n_0\, I4 => \divider_reg__0\(7), I5 => \busy_sr_reg[31]_0\, O => \data_sr[22]_i_1_n_0\ ); \data_sr[27]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CFCFCFCFAACAAAAA" ) port map ( I0 => \data_sr_reg_n_0_[27]\, I1 => \data_sr_reg_n_0_[26]\, I2 => \^p_0_in\, I3 => \data_sr[31]_i_2_n_0\, I4 => \divider_reg__0\(7), I5 => \busy_sr_reg[31]_0\, O => \data_sr[27]_i_1_n_0\ ); \data_sr[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => p_1_in(0), I1 => \^busy_sr_reg[1]_0\, I2 => \^p_0_in\, O => \data_sr[30]_i_1_n_0\ ); \data_sr[31]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CFCFCFCFAACAAAAA" ) port map ( I0 => \data_sr_reg_n_0_[31]\, I1 => \data_sr_reg_n_0_[30]\, I2 => \^p_0_in\, I3 => \data_sr[31]_i_2_n_0\, I4 => \divider_reg__0\(7), I5 => \busy_sr_reg[31]_0\, O => \data_sr[31]_i_1_n_0\ ); \data_sr[31]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \busy_sr[0]_i_3_n_0\, I1 => \divider_reg__0\(6), O => \data_sr[31]_i_2_n_0\ ); \data_sr[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[2]\, I1 => \^p_0_in\, I2 => DOADO(0), O => \data_sr[3]_i_1_n_0\ ); \data_sr[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[3]\, I1 => \^p_0_in\, I2 => DOADO(1), O => \data_sr[4]_i_1_n_0\ ); \data_sr[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[4]\, I1 => \^p_0_in\, I2 => DOADO(2), O => \data_sr[5]_i_1_n_0\ ); \data_sr[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[5]\, I1 => \^p_0_in\, I2 => DOADO(3), O => \data_sr[6]_i_1_n_0\ ); \data_sr[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[6]\, I1 => \^p_0_in\, I2 => DOADO(4), O => \data_sr[7]_i_1_n_0\ ); \data_sr[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[7]\, I1 => \^p_0_in\, I2 => DOADO(5), O => \data_sr[8]_i_1_n_0\ ); \data_sr[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \data_sr_reg_n_0_[8]\, I1 => \^p_0_in\, I2 => DOADO(6), O => \data_sr[9]_i_1_n_0\ ); \data_sr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[10]_i_1_n_0\, Q => \data_sr_reg_n_0_[10]\, R => '0' ); \data_sr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[10]\, Q => \data_sr_reg_n_0_[11]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[12]_i_1_n_0\, Q => \data_sr_reg_n_0_[12]\, R => '0' ); \data_sr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[13]_i_1_n_0\, Q => \data_sr_reg_n_0_[13]\, R => '0' ); \data_sr_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[14]_i_1_n_0\, Q => \data_sr_reg_n_0_[14]\, R => '0' ); \data_sr_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[15]_i_1_n_0\, Q => \data_sr_reg_n_0_[15]\, R => '0' ); \data_sr_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[16]_i_1_n_0\, Q => \data_sr_reg_n_0_[16]\, R => '0' ); \data_sr_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[17]_i_1_n_0\, Q => \data_sr_reg_n_0_[17]\, R => '0' ); \data_sr_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[18]_i_1_n_0\, Q => \data_sr_reg_n_0_[18]\, R => '0' ); \data_sr_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[19]_i_1_n_0\, Q => \data_sr_reg_n_0_[19]\, R => '0' ); \data_sr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \^p_0_in\, Q => \data_sr_reg_n_0_[1]\, R => '0' ); \data_sr_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[19]\, Q => \data_sr_reg_n_0_[20]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[20]\, Q => \data_sr_reg_n_0_[21]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => \data_sr[22]_i_1_n_0\, Q => \data_sr_reg_n_0_[22]\, R => '0' ); \data_sr_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[22]\, Q => \data_sr_reg_n_0_[23]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[23]\, Q => \data_sr_reg_n_0_[24]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[24]\, Q => \data_sr_reg_n_0_[25]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[25]\, Q => \data_sr_reg_n_0_[26]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => \data_sr[27]_i_1_n_0\, Q => \data_sr_reg_n_0_[27]\, R => '0' ); \data_sr_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[27]\, Q => \data_sr_reg_n_0_[28]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[28]\, Q => \data_sr_reg_n_0_[29]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[1]\, Q => \data_sr_reg_n_0_[2]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr_reg_n_0_[29]\, Q => \data_sr_reg_n_0_[30]\, R => \data_sr[30]_i_1_n_0\ ); \data_sr_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => '1', D => \data_sr[31]_i_1_n_0\, Q => \data_sr_reg_n_0_[31]\, R => '0' ); \data_sr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[3]_i_1_n_0\, Q => \data_sr_reg_n_0_[3]\, R => '0' ); \data_sr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[4]_i_1_n_0\, Q => \data_sr_reg_n_0_[4]\, R => '0' ); \data_sr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[5]_i_1_n_0\, Q => \data_sr_reg_n_0_[5]\, R => '0' ); \data_sr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[6]_i_1_n_0\, Q => \data_sr_reg_n_0_[6]\, R => '0' ); \data_sr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[7]_i_1_n_0\, Q => \data_sr_reg_n_0_[7]\, R => '0' ); \data_sr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[8]_i_1_n_0\, Q => \data_sr_reg_n_0_[8]\, R => '0' ); \data_sr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => busy_sr0, D => \data_sr[9]_i_1_n_0\, Q => \data_sr_reg_n_0_[9]\, R => '0' ); \divider[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \divider_reg__1\(0), O => \p_0_in__0\(0) ); \divider[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \divider_reg__1\(0), I1 => \divider_reg__1\(1), O => \p_0_in__0\(1) ); \divider[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \divider_reg__1\(1), I1 => \divider_reg__1\(0), I2 => \divider_reg__1\(2), O => \p_0_in__0\(2) ); \divider[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \divider_reg__1\(2), I1 => \divider_reg__1\(0), I2 => \divider_reg__1\(1), I3 => \divider_reg__1\(3), O => \p_0_in__0\(3) ); \divider[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \divider_reg__1\(3), I1 => \divider_reg__1\(1), I2 => \divider_reg__1\(0), I3 => \divider_reg__1\(2), I4 => \divider_reg__1\(4), O => \p_0_in__0\(4) ); \divider[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \divider_reg__1\(4), I1 => \divider_reg__1\(2), I2 => \divider_reg__1\(0), I3 => \divider_reg__1\(1), I4 => \divider_reg__1\(3), I5 => \divider_reg__1\(5), O => \p_0_in__0\(5) ); \divider[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \busy_sr[0]_i_3_n_0\, I1 => \divider_reg__0\(6), O => \p_0_in__0\(6) ); \divider[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => \divider_reg__0\(6), I1 => \busy_sr[0]_i_3_n_0\, I2 => \divider_reg__0\(7), O => \p_0_in__0\(7) ); \divider_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(0), Q => \divider_reg__1\(0), R => '0' ); \divider_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(1), Q => \divider_reg__1\(1), R => '0' ); \divider_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(2), Q => \divider_reg__1\(2), R => '0' ); \divider_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(3), Q => \divider_reg__1\(3), R => '0' ); \divider_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(4), Q => \divider_reg__1\(4), R => '0' ); \divider_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(5), Q => \divider_reg__1\(5), R => '0' ); \divider_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(6), Q => \divider_reg__0\(6), R => '0' ); \divider_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => \busy_sr_reg[31]_1\(0), D => \p_0_in__0\(7), Q => \divider_reg__0\(7), R => '0' ); sioc_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FCFCFFF8FFFFFFFF" ) port map ( I0 => \busy_sr_reg_n_0_[0]\, I1 => sioc_i_2_n_0, I2 => sioc_i_3_n_0, I3 => \busy_sr_reg_n_0_[1]\, I4 => sioc_i_4_n_0, I5 => \^p_0_in\, O => sioc_i_1_n_0 ); sioc_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \divider_reg__0\(6), I1 => \divider_reg__0\(7), O => sioc_i_2_n_0 ); sioc_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"A222" ) port map ( I0 => sioc_i_5_n_0, I1 => \busy_sr_reg_n_0_[30]\, I2 => \divider_reg__0\(6), I3 => \^p_0_in\, O => sioc_i_3_n_0 ); sioc_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \busy_sr_reg_n_0_[29]\, I1 => \busy_sr_reg_n_0_[2]\, I2 => \^p_0_in\, I3 => \busy_sr_reg_n_0_[30]\, O => sioc_i_4_n_0 ); sioc_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \busy_sr_reg_n_0_[0]\, I1 => \busy_sr_reg_n_0_[1]\, I2 => \busy_sr_reg_n_0_[29]\, I3 => \busy_sr_reg_n_0_[2]\, O => sioc_i_5_n_0 ); sioc_reg: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => sioc_i_1_n_0, Q => sioc, R => '0' ); siod_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \data_sr_reg_n_0_[31]\, I1 => siod_INST_0_i_1_n_0, O => siod ); siod_INST_0_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"B0BBB0BB0000B0BB" ) port map ( I0 => \busy_sr_reg_n_0_[28]\, I1 => \busy_sr_reg_n_0_[29]\, I2 => p_1_in_0(0), I3 => p_1_in_0(1), I4 => \busy_sr_reg_n_0_[11]\, I5 => \busy_sr_reg_n_0_[10]\, O => siod_INST_0_i_1_n_0 ); taken_reg: unisim.vcomponents.FDRE port map ( C => clk, CE => '1', D => \busy_sr_reg[31]_0\, Q => E(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_controller_0_0_ov7670_registers is port ( DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 ); \divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); config_finished : out STD_LOGIC; taken_reg : out STD_LOGIC; p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 ); clk : in STD_LOGIC; \divider_reg[2]\ : in STD_LOGIC; p_0_in : in STD_LOGIC; resend : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers"; end system_ov7670_controller_0_0_ov7670_registers; architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal address : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \address_rep[0]_i_1_n_0\ : STD_LOGIC; signal \address_rep[1]_i_1_n_0\ : STD_LOGIC; signal \address_rep[2]_i_1_n_0\ : STD_LOGIC; signal \address_rep[3]_i_1_n_0\ : STD_LOGIC; signal \address_rep[4]_i_1_n_0\ : STD_LOGIC; signal \address_rep[5]_i_1_n_0\ : STD_LOGIC; signal \address_rep[6]_i_1_n_0\ : STD_LOGIC; signal \address_rep[7]_i_1_n_0\ : STD_LOGIC; signal \address_rep[7]_i_2_n_0\ : STD_LOGIC; signal config_finished_INST_0_i_1_n_0 : STD_LOGIC; signal config_finished_INST_0_i_2_n_0 : STD_LOGIC; signal config_finished_INST_0_i_3_n_0 : STD_LOGIC; signal config_finished_INST_0_i_4_n_0 : STD_LOGIC; signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute equivalent_register_removal : string; attribute equivalent_register_removal of \address_reg[0]\ : label is "no"; attribute equivalent_register_removal of \address_reg[1]\ : label is "no"; attribute equivalent_register_removal of \address_reg[2]\ : label is "no"; attribute equivalent_register_removal of \address_reg[3]\ : label is "no"; attribute equivalent_register_removal of \address_reg[4]\ : label is "no"; attribute equivalent_register_removal of \address_reg[5]\ : label is "no"; attribute equivalent_register_removal of \address_reg[6]\ : label is "no"; attribute equivalent_register_removal of \address_reg[7]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no"; attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT"; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string; attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16"; attribute METHODOLOGY_DRC_VIOS : string; attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}"; attribute RTL_RAM_BITS : integer; attribute RTL_RAM_BITS of sreg_reg : label is 4096; attribute RTL_RAM_NAME : string; attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg"; attribute bram_addr_begin : integer; attribute bram_addr_begin of sreg_reg : label is 0; attribute bram_addr_end : integer; attribute bram_addr_end of sreg_reg : label is 1023; attribute bram_slice_begin : integer; attribute bram_slice_begin of sreg_reg : label is 0; attribute bram_slice_end : integer; attribute bram_slice_end of sreg_reg : label is 15; begin DOADO(15 downto 0) <= \^doado\(15 downto 0); \address_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[0]_i_1_n_0\, Q => \address_reg__0\(0), R => resend ); \address_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[1]_i_1_n_0\, Q => \address_reg__0\(1), R => resend ); \address_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[2]_i_1_n_0\, Q => \address_reg__0\(2), R => resend ); \address_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[3]_i_1_n_0\, Q => \address_reg__0\(3), R => resend ); \address_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[4]_i_1_n_0\, Q => \address_reg__0\(4), R => resend ); \address_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[5]_i_1_n_0\, Q => \address_reg__0\(5), R => resend ); \address_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[6]_i_1_n_0\, Q => \address_reg__0\(6), R => resend ); \address_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[7]_i_1_n_0\, Q => \address_reg__0\(7), R => resend ); \address_reg_rep[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[0]_i_1_n_0\, Q => address(0), R => resend ); \address_reg_rep[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[1]_i_1_n_0\, Q => address(1), R => resend ); \address_reg_rep[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[2]_i_1_n_0\, Q => address(2), R => resend ); \address_reg_rep[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[3]_i_1_n_0\, Q => address(3), R => resend ); \address_reg_rep[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[4]_i_1_n_0\, Q => address(4), R => resend ); \address_reg_rep[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[5]_i_1_n_0\, Q => address(5), R => resend ); \address_reg_rep[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[6]_i_1_n_0\, Q => address(6), R => resend ); \address_reg_rep[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => E(0), D => \address_rep[7]_i_1_n_0\, Q => address(7), R => resend ); \address_rep[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \address_reg__0\(0), O => \address_rep[0]_i_1_n_0\ ); \address_rep[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \address_reg__0\(0), I1 => \address_reg__0\(1), O => \address_rep[1]_i_1_n_0\ ); \address_rep[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \address_reg__0\(1), I1 => \address_reg__0\(0), I2 => \address_reg__0\(2), O => \address_rep[2]_i_1_n_0\ ); \address_rep[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \address_reg__0\(2), I1 => \address_reg__0\(0), I2 => \address_reg__0\(1), I3 => \address_reg__0\(3), O => \address_rep[3]_i_1_n_0\ ); \address_rep[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \address_reg__0\(3), I1 => \address_reg__0\(1), I2 => \address_reg__0\(0), I3 => \address_reg__0\(2), I4 => \address_reg__0\(4), O => \address_rep[4]_i_1_n_0\ ); \address_rep[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \address_reg__0\(4), I1 => \address_reg__0\(2), I2 => \address_reg__0\(0), I3 => \address_reg__0\(1), I4 => \address_reg__0\(3), I5 => \address_reg__0\(5), O => \address_rep[5]_i_1_n_0\ ); \address_rep[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \address_rep[7]_i_2_n_0\, I1 => \address_reg__0\(6), O => \address_rep[6]_i_1_n_0\ ); \address_rep[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => \address_reg__0\(6), I1 => \address_rep[7]_i_2_n_0\, I2 => \address_reg__0\(7), O => \address_rep[7]_i_1_n_0\ ); \address_rep[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \address_reg__0\(4), I1 => \address_reg__0\(2), I2 => \address_reg__0\(0), I3 => \address_reg__0\(1), I4 => \address_reg__0\(3), I5 => \address_reg__0\(5), O => \address_rep[7]_i_2_n_0\ ); \busy_sr[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FFFE" ) port map ( I0 => config_finished_INST_0_i_4_n_0, I1 => config_finished_INST_0_i_3_n_0, I2 => config_finished_INST_0_i_2_n_0, I3 => config_finished_INST_0_i_1_n_0, I4 => p_0_in, O => p_1_in(0) ); config_finished_INST_0: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => config_finished_INST_0_i_1_n_0, I1 => config_finished_INST_0_i_2_n_0, I2 => config_finished_INST_0_i_3_n_0, I3 => config_finished_INST_0_i_4_n_0, O => config_finished ); config_finished_INST_0_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \^doado\(5), I1 => \^doado\(4), I2 => \^doado\(7), I3 => \^doado\(6), O => config_finished_INST_0_i_1_n_0 ); config_finished_INST_0_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \^doado\(1), I1 => \^doado\(0), I2 => \^doado\(3), I3 => \^doado\(2), O => config_finished_INST_0_i_2_n_0 ); config_finished_INST_0_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \^doado\(13), I1 => \^doado\(12), I2 => \^doado\(15), I3 => \^doado\(14), O => config_finished_INST_0_i_3_n_0 ); config_finished_INST_0_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \^doado\(9), I1 => \^doado\(8), I2 => \^doado\(11), I3 => \^doado\(10), O => config_finished_INST_0_i_4_n_0 ); \divider[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFE0000" ) port map ( I0 => config_finished_INST_0_i_1_n_0, I1 => config_finished_INST_0_i_2_n_0, I2 => config_finished_INST_0_i_3_n_0, I3 => config_finished_INST_0_i_4_n_0, I4 => \divider_reg[2]\, I5 => p_0_in, O => \divider_reg[7]\(0) ); sreg_reg: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280", INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440", INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907", INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100", INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_A => X"00000", INIT_B => X"00000", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "PERFORMANCE", READ_WIDTH_A => 18, READ_WIDTH_B => 0, RSTREG_PRIORITY_A => "RSTREG", RSTREG_PRIORITY_B => "RSTREG", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 0 ) port map ( ADDRARDADDR(13 downto 12) => B"00", ADDRARDADDR(11 downto 4) => address(7 downto 0), ADDRARDADDR(3 downto 0) => B"0000", ADDRBWRADDR(13 downto 0) => B"11111111111111", CLKARDCLK => clk, CLKBWRCLK => '0', DIADI(15 downto 0) => B"1111111111111111", DIBDI(15 downto 0) => B"1111111111111111", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"11", DOADO(15 downto 0) => \^doado\(15 downto 0), DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0), DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0), DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0), ENARDEN => '1', ENBWREN => '0', REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1 downto 0) => B"00", WEBWE(3 downto 0) => B"0000" ); taken_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000055555554" ) port map ( I0 => p_0_in, I1 => config_finished_INST_0_i_1_n_0, I2 => config_finished_INST_0_i_2_n_0, I3 => config_finished_INST_0_i_3_n_0, I4 => config_finished_INST_0_i_4_n_0, I5 => \divider_reg[2]\, O => taken_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_controller_0_0_ov7670_controller is port ( config_finished : out STD_LOGIC; siod : out STD_LOGIC; xclk : out STD_LOGIC; sioc : out STD_LOGIC; resend : in STD_LOGIC; clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller"; end system_ov7670_controller_0_0_ov7670_controller; architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is signal Inst_i2c_sender_n_3 : STD_LOGIC; signal Inst_ov7670_registers_n_16 : STD_LOGIC; signal Inst_ov7670_registers_n_18 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 ); signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); signal sys_clk_i_1_n_0 : STD_LOGIC; signal taken : STD_LOGIC; signal \^xclk\ : STD_LOGIC; begin xclk <= \^xclk\; Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender port map ( DOADO(15 downto 0) => sreg_reg(15 downto 0), E(0) => taken, \busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3, \busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18, \busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16, clk => clk, p_0_in => p_0_in, p_1_in(0) => p_1_in(0), sioc => sioc, siod => siod ); Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers port map ( DOADO(15 downto 0) => sreg_reg(15 downto 0), E(0) => taken, clk => clk, config_finished => config_finished, \divider_reg[2]\ => Inst_i2c_sender_n_3, \divider_reg[7]\(0) => Inst_ov7670_registers_n_16, p_0_in => p_0_in, p_1_in(0) => p_1_in(0), resend => resend, taken_reg => Inst_ov7670_registers_n_18 ); sys_clk_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^xclk\, O => sys_clk_i_1_n_0 ); sys_clk_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk, CE => '1', D => sys_clk_i_1_n_0, Q => \^xclk\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity system_ov7670_controller_0_0 is port ( clk : in STD_LOGIC; resend : in STD_LOGIC; config_finished : out STD_LOGIC; sioc : out STD_LOGIC; siod : inout STD_LOGIC; reset : out STD_LOGIC; pwdn : out STD_LOGIC; xclk : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4"; end system_ov7670_controller_0_0; architecture STRUCTURE of system_ov7670_controller_0_0 is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; begin pwdn <= \<const0>\; reset <= \<const1>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); U0: entity work.system_ov7670_controller_0_0_ov7670_controller port map ( clk => clk, config_finished => config_finished, resend => resend, sioc => sioc, siod => siod, xclk => xclk ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); end STRUCTURE;
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ library techmap; use techmap.gencomp.all; package config is -- Technology and synthesis options constant CFG_FABTECH : integer := spartan3e; constant CFG_MEMTECH : integer := spartan3e; constant CFG_PADTECH : integer := spartan3e; constant CFG_NOASYNC : integer := 0; constant CFG_SCAN : integer := 0; -- Clock generator constant CFG_CLKTECH : integer := spartan3e; constant CFG_CLKMUL : integer := (4); constant CFG_CLKDIV : integer := (5); constant CFG_OCLKDIV : integer := 1; constant CFG_OCLKBDIV : integer := 0; constant CFG_OCLKCDIV : integer := 0; constant CFG_PCIDLL : integer := 0; constant CFG_PCISYSCLK: integer := 0; constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 2 + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; constant CFG_SVT : integer := 1; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 1; constant CFG_NWP : integer := (2); constant CFG_PWD : integer := 1*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 2; constant CFG_ISETSZ : integer := 4; constant CFG_ILINE : integer := 8; constant CFG_IREPL : integer := 2; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 2; constant CFG_DSETSZ : integer := 4; constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 1 + 0 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; constant CFG_MMUEN : integer := 1; constant CFG_ITLBNUM : integer := 8; constant CFG_DTLBNUM : integer := 8; constant CFG_TLB_TYPE : integer := 0 + 1*2; constant CFG_TLB_REP : integer := 0; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; constant CFG_ITBSZ : integer := 4; constant CFG_ATBSZ : integer := 4; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; constant CFG_RF_ERRINJ : integer := 0; constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 0; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; constant CFG_AHB_MONERR : integer := 0; constant CFG_AHB_MONWAR : integer := 0; constant CFG_AHB_DTRACE : integer := 0; -- DSU UART constant CFG_AHB_UART : integer := 1; -- JTAG based DSU interface constant CFG_AHB_JTAG : integer := 1; -- Ethernet DSU constant CFG_DSU_ETH : integer := 1 + 0 + 0; constant CFG_ETH_BUF : integer := 2; constant CFG_ETH_IPM : integer := 16#C0A8#; constant CFG_ETH_IPL : integer := 16#0033#; constant CFG_ETH_ENM : integer := 16#020000#; constant CFG_ETH_ENL : integer := 16#000018#; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 0; constant CFG_MCTRL_RAM16BIT : integer := 1; constant CFG_MCTRL_5CS : integer := 0; constant CFG_MCTRL_SDEN : integer := 0; constant CFG_MCTRL_SEPBUS : integer := 0; constant CFG_MCTRL_INVCLK : integer := 0; constant CFG_MCTRL_SD64 : integer := 0; constant CFG_MCTRL_PAGE : integer := 0 + 0; -- DDR controller constant CFG_DDRSP : integer := 1; constant CFG_DDRSP_INIT : integer := 1; constant CFG_DDRSP_FREQ : integer := (90); constant CFG_DDRSP_COL : integer := (10); constant CFG_DDRSP_SIZE : integer := (64); constant CFG_DDRSP_RSKEW : integer := (40); -- AHB ROM constant CFG_AHBROMEN : integer := 0; constant CFG_AHBROPIP : integer := 0; constant CFG_AHBRODDR : integer := 16#000#; constant CFG_ROMADDR : integer := 16#000#; constant CFG_ROMMASK : integer := 16#E00# + 16#000#; -- AHB RAM constant CFG_AHBRAMEN : integer := 0; constant CFG_AHBRSZ : integer := 1; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- Gaisler Ethernet core constant CFG_GRETH : integer := 1; constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 32; -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 8; -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 1; constant CFG_IRQ3_NSEC : integer := 0; -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; constant CFG_GRGPIO_IMASK : integer := 16#0000#; constant CFG_GRGPIO_WIDTH : integer := (8); -- VGA and PS2/ interface constant CFG_KBD_ENABLE : integer := 1; constant CFG_VGA_ENABLE : integer := 0; constant CFG_SVGA_ENABLE : integer := 1; -- GRLIB debugging constant CFG_DUART : integer := 0; end;
-- ------------------------------------------------------------- -- -- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block.vhd -- Created: 2017-03-27 23:13:58 -- -- Generated by MATLAB 9.1 and HDL Coder 3.9 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: RADIX22FFT_SDNF1_3_block -- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_3 -- Hierarchy Level: 2 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY RADIX22FFT_SDNF1_3_block IS PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_2_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_2_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_4_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_3_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_4_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_3_vld : OUT std_logic ); END RADIX22FFT_SDNF1_3_block; ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block IS -- Signals SIGNAL twdlXdin_2_re_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_2_im_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_4_re_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_4_im_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic; SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic; SIGNAL dout_3_re_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_3_im_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_4_re_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_4_im_tmp : signed(19 DOWNTO 0); -- sfix20 BEGIN twdlXdin_2_re_signed <= signed(twdlXdin_2_re); twdlXdin_2_im_signed <= signed(twdlXdin_2_im); twdlXdin_4_re_signed <= signed(twdlXdin_4_re); twdlXdin_4_im_signed <= signed(twdlXdin_4_im); -- Radix22ButterflyG1_NF Radix22ButterflyG1_NF_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next; Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next; Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next; Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next; Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next; END IF; END IF; END PROCESS Radix22ButterflyG1_NF_process; Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg, Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg, Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_2_re_signed, twdlXdin_2_im_signed, twdlXdin_4_re_signed, twdlXdin_4_im_signed, twdlXdin_1_vld) BEGIN Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg; Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg; Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg; Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg; Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld; IF twdlXdin_1_vld = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_2_re_signed, 21) + resize(twdlXdin_4_re_signed, 21); Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_2_re_signed, 21) - resize(twdlXdin_4_re_signed, 21); Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_2_im_signed, 21) + resize(twdlXdin_4_im_signed, 21); Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_2_im_signed, 21) - resize(twdlXdin_4_im_signed, 21); END IF; dout_3_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(19 DOWNTO 0); dout_3_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(19 DOWNTO 0); dout_4_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(19 DOWNTO 0); dout_4_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(19 DOWNTO 0); dout_3_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1; END PROCESS Radix22ButterflyG1_NF_output; dout_3_re <= std_logic_vector(dout_3_re_tmp); dout_3_im <= std_logic_vector(dout_3_im_tmp); dout_4_re <= std_logic_vector(dout_4_re_tmp); dout_4_im <= std_logic_vector(dout_4_im_tmp); END rtl;
------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- Copyright (C) 2015, Cobham Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- -- Package: netcomp -- File: netcomp.vhd -- Author: Jiri Gaisler - Aeroflex Gaisler -- Description: Declaration of netlists components ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library grlib; use grlib.amba.all; use work.gencomp.all; package netcomp is --------------------------------------------------------------------------- -- netlists --------------------------------------------------------------- --------------------------------------------------------------------------- component grusbhc_net is generic ( tech : integer := 0; nports : integer range 1 to 15 := 1; ehcgen : integer range 0 to 1 := 1; uhcgen : integer range 0 to 1 := 1; n_cc : integer range 1 to 15 := 1; n_pcc : integer range 1 to 15 := 1; prr : integer range 0 to 1 := 0; portroute1 : integer := 0; portroute2 : integer := 0; endian_conv : integer range 0 to 1 := 1; be_regs : integer range 0 to 1 := 0; be_desc : integer range 0 to 1 := 0; uhcblo : integer range 0 to 255 := 2; bwrd : integer range 1 to 256 := 16; utm_type : integer range 0 to 2 := 2; vbusconf : integer := 3; ramtest : integer range 0 to 1 := 0; urst_time : integer := 250; oepol : integer range 0 to 1 := 0; scantest : integer range 0 to 1 := 0; isfpga : integer range 0 to 1 := 1; memsel : integer := 0; syncprst : integer range 0 to 1 := 0; sysfreq : integer := 65000; pcidev : integer range 0 to 1 := 0; debug : integer := 0; debug_abits : integer := 12); port ( clk : in std_ulogic; uclk : in std_ulogic; rst : in std_ulogic; -- EHC apb_slv_in_type unwrapped ehc_apbsi_psel : in std_ulogic; ehc_apbsi_penable : in std_ulogic; ehc_apbsi_paddr : in std_logic_vector(31 downto 0); ehc_apbsi_pwrite : in std_ulogic; ehc_apbsi_pwdata : in std_logic_vector(31 downto 0); -- EHC apb_slv_out_type unwrapped ehc_apbso_prdata : out std_logic_vector(31 downto 0); ehc_apbso_pirq : out std_ulogic; -- EHC/UHC ahb_mst_in_type unwrapped ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0); ahbmi_hready : in std_ulogic; ahbmi_hresp : in std_logic_vector(1 downto 0); ahbmi_hrdata : in std_logic_vector(31 downto 0); -- UHC ahb_slv_in_type unwrapped uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen); uhc_ahbsi_haddr : in std_logic_vector(31 downto 0); uhc_ahbsi_hwrite : in std_ulogic; uhc_ahbsi_htrans : in std_logic_vector(1 downto 0); uhc_ahbsi_hsize : in std_logic_vector(2 downto 0); uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0); uhc_ahbsi_hready : in std_ulogic; -- EHC ahb_mst_out_type_unwrapped ehc_ahbmo_hbusreq : out std_ulogic; ehc_ahbmo_hlock : out std_ulogic; ehc_ahbmo_htrans : out std_logic_vector(1 downto 0); ehc_ahbmo_haddr : out std_logic_vector(31 downto 0); ehc_ahbmo_hwrite : out std_ulogic; ehc_ahbmo_hsize : out std_logic_vector(2 downto 0); ehc_ahbmo_hburst : out std_logic_vector(2 downto 0); ehc_ahbmo_hprot : out std_logic_vector(3 downto 0); ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0); -- UHC ahb_mst_out_vector_type unwrapped uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen); uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen); uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen); uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen); uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); -- UHC ahb_slv_out_vector_type unwrapped uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen); uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen); uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); -- grusb_out_type_vector unwrapped xcvrsel : out std_logic_vector(((nports*2)-1) downto 0); termsel : out std_logic_vector((nports-1) downto 0); opmode : out std_logic_vector(((nports*2)-1) downto 0); txvalid : out std_logic_vector((nports-1) downto 0); drvvbus : out std_logic_vector((nports-1) downto 0); dataho : out std_logic_vector(((nports*8)-1) downto 0); validho : out std_logic_vector((nports-1) downto 0); stp : out std_logic_vector((nports-1) downto 0); datao : out std_logic_vector(((nports*8)-1) downto 0); utm_rst : out std_logic_vector((nports-1) downto 0); dctrlo : out std_logic_vector((nports-1) downto 0); suspendm : out std_ulogic; dbus16_8 : out std_ulogic; dppulldown : out std_ulogic; dmpulldown : out std_ulogic; idpullup : out std_ulogic; dischrgvbus : out std_ulogic; chrgvbus : out std_ulogic; txbitstuffenable : out std_ulogic; txbitstuffenableh : out std_ulogic; fslsserialmode : out std_ulogic; txenablen : out std_ulogic; txdat : out std_ulogic; txse0 : out std_ulogic; -- grusb_in_type_vector unwrapped linestate : in std_logic_vector(((nports*2)-1) downto 0); txready : in std_logic_vector((nports-1) downto 0); rxvalid : in std_logic_vector((nports-1) downto 0); rxactive : in std_logic_vector((nports-1) downto 0); rxerror : in std_logic_vector((nports-1) downto 0); vbusvalid : in std_logic_vector((nports-1) downto 0); datahi : in std_logic_vector(((nports*8)-1) downto 0); validhi : in std_logic_vector((nports-1) downto 0); hostdisc : in std_logic_vector((nports-1) downto 0); nxt : in std_logic_vector((nports-1) downto 0); dir : in std_logic_vector((nports-1) downto 0); datai : in std_logic_vector(((nports*8)-1) downto 0); urstdrive : in std_logic_vector((nports-1) downto 0); -- EHC transaction buffer signals mbc20_tb_addr : out std_logic_vector(8 downto 0); mbc20_tb_data : out std_logic_vector(31 downto 0); mbc20_tb_en : out std_ulogic; mbc20_tb_wel : out std_ulogic; mbc20_tb_weh : out std_ulogic; tb_mbc20_data : in std_logic_vector(31 downto 0); pe20_tb_addr : out std_logic_vector(8 downto 0); pe20_tb_data : out std_logic_vector(31 downto 0); pe20_tb_en : out std_ulogic; pe20_tb_wel : out std_ulogic; pe20_tb_weh : out std_ulogic; tb_pe20_data : in std_logic_vector(31 downto 0); -- EHC packet buffer signals mbc20_pb_addr : out std_logic_vector(8 downto 0); mbc20_pb_data : out std_logic_vector(31 downto 0); mbc20_pb_en : out std_ulogic; mbc20_pb_we : out std_ulogic; pb_mbc20_data : in std_logic_vector(31 downto 0); sie20_pb_addr : out std_logic_vector(8 downto 0); sie20_pb_data : out std_logic_vector(31 downto 0); sie20_pb_en : out std_ulogic; sie20_pb_we : out std_ulogic; pb_sie20_data : in std_logic_vector(31 downto 0); -- UHC packet buffer signals sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen); sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen); mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen); pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen); bufsel : out std_ulogic; -- scan signals testen : in std_ulogic; testrst : in std_ulogic; scanen : in std_ulogic; testoen : in std_ulogic; -- debug signals debug_raddr : out std_logic_vector(15 downto 0); debug_waddr : out std_logic_vector(15 downto 0); debug_wdata : out std_logic_vector(31 downto 0); debug_we : out std_ulogic; debug_rdata : in std_logic_vector(31 downto 0)); end component; component grspwc_net generic( tech : integer := 0; sysfreq : integer := 40000; usegen : integer range 0 to 1 := 1; nsync : integer range 1 to 2 := 1; rmap : integer range 0 to 2 := 0; rmapcrc : integer range 0 to 1 := 0; fifosize1 : integer range 4 to 32 := 32; fifosize2 : integer range 16 to 64 := 64; rxunaligned : integer range 0 to 1 := 0; rmapbufs : integer range 2 to 8 := 4; scantest : integer range 0 to 1 := 0; nodeaddr : integer range 0 to 255 := 254; destkey : integer range 0 to 255 := 0 ); port( rst : in std_ulogic; clk : in std_ulogic; txclk : in std_ulogic; --ahb mst in hgrant : in std_ulogic; hready : in std_ulogic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); --ahb mst out hbusreq : out std_ulogic; hlock : out std_ulogic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_ulogic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); --apb slv in psel : in std_ulogic; penable : in std_ulogic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_ulogic; pwdata : in std_logic_vector(31 downto 0); --apb slv out prdata : out std_logic_vector(31 downto 0); --spw in d : in std_logic_vector(1 downto 0); nd : in std_logic_vector(9 downto 0); dconnect : in std_logic_vector(3 downto 0); --spw out do : out std_logic_vector(1 downto 0); so : out std_logic_vector(1 downto 0); rxrsto : out std_ulogic; --time iface tickin : in std_ulogic; tickout : out std_ulogic; --irq irq : out std_logic; --misc clkdiv10 : in std_logic_vector(7 downto 0); dcrstval : in std_logic_vector(9 downto 0); timerrstval : in std_logic_vector(11 downto 0); --rmapen rmapen : in std_ulogic; rmapnodeaddr : in std_logic_vector(7 downto 0); --clk bufs rxclki : in std_logic_vector(1 downto 0); --rx ahb fifo rxrenable : out std_ulogic; rxraddress : out std_logic_vector(4 downto 0); rxwrite : out std_ulogic; rxwdata : out std_logic_vector(31 downto 0); rxwaddress : out std_logic_vector(4 downto 0); rxrdata : in std_logic_vector(31 downto 0); --tx ahb fifo txrenable : out std_ulogic; txraddress : out std_logic_vector(4 downto 0); txwrite : out std_ulogic; txwdata : out std_logic_vector(31 downto 0); txwaddress : out std_logic_vector(4 downto 0); txrdata : in std_logic_vector(31 downto 0); --nchar fifo ncrenable : out std_ulogic; ncraddress : out std_logic_vector(5 downto 0); ncwrite : out std_ulogic; ncwdata : out std_logic_vector(8 downto 0); ncwaddress : out std_logic_vector(5 downto 0); ncrdata : in std_logic_vector(8 downto 0); --rmap buf rmrenable : out std_ulogic; rmraddress : out std_logic_vector(7 downto 0); rmwrite : out std_ulogic; rmwdata : out std_logic_vector(7 downto 0); rmwaddress : out std_logic_vector(7 downto 0); rmrdata : in std_logic_vector(7 downto 0); linkdis : out std_ulogic; testclk : in std_ulogic := '0'; testrst : in std_ulogic := '0'; testen : in std_ulogic := '0' ); end component; component grspwc2_net is generic( rmap : integer range 0 to 2 := 0; rmapcrc : integer range 0 to 1 := 0; fifosize1 : integer range 4 to 32 := 32; fifosize2 : integer range 16 to 64 := 64; rxunaligned : integer range 0 to 1 := 0; rmapbufs : integer range 2 to 8 := 4; scantest : integer range 0 to 1 := 0; ports : integer range 1 to 2 := 1; dmachan : integer range 1 to 4 := 1; tech : integer; input_type : integer range 0 to 4 := 0; output_type : integer range 0 to 2 := 0; rxtx_sameclk : integer range 0 to 1 := 0; nodeaddr : integer range 0 to 255 := 254; destkey : integer range 0 to 255 := 0; interruptdist : integer range 0 to 32 := 0; intscalerbits : integer range 0 to 31 := 0; intisrtimerbits : integer range 0 to 31 := 0; intiatimerbits : integer range 0 to 31 := 0; intctimerbits : integer range 0 to 31 := 0; tickinasync : integer range 0 to 1 := 0; pnp : integer range 0 to 2 := 0; pnpvendid : integer range 0 to 16#FFFF# := 0; pnpprodid : integer range 0 to 16#FFFF# := 0; pnpmajorver : integer range 0 to 16#FF# := 0; pnpminorver : integer range 0 to 16#FF# := 0; pnppatch : integer range 0 to 16#FF# := 0; num_txdesc : integer range 64 to 512 := 64; num_rxdesc : integer range 128 to 1024 := 128 ); port( rst : in std_ulogic; clk : in std_ulogic; rxclk : in std_logic_vector(1 downto 0); txclk : in std_ulogic; txclkn : in std_ulogic; --ahb mst in hgrant : in std_ulogic; hready : in std_ulogic; hresp : in std_logic_vector(1 downto 0); hrdata : in std_logic_vector(31 downto 0); --ahb mst out hbusreq : out std_ulogic; hlock : out std_ulogic; htrans : out std_logic_vector(1 downto 0); haddr : out std_logic_vector(31 downto 0); hwrite : out std_ulogic; hsize : out std_logic_vector(2 downto 0); hburst : out std_logic_vector(2 downto 0); hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); --apb slv in psel : in std_ulogic; penable : in std_ulogic; paddr : in std_logic_vector(31 downto 0); pwrite : in std_ulogic; pwdata : in std_logic_vector(31 downto 0); --apb slv out prdata : out std_logic_vector(31 downto 0); --spw in d : in std_logic_vector(3 downto 0); dv : in std_logic_vector(3 downto 0); dconnect : in std_logic_vector(3 downto 0); --spw out do : out std_logic_vector(3 downto 0); so : out std_logic_vector(3 downto 0); --time iface tickin : in std_logic; tickinraw : in std_logic; timein : in std_logic_vector(7 downto 0); tickindone : out std_logic; tickout : out std_logic; tickoutraw : out std_logic; timeout : out std_logic_vector(7 downto 0); --irq irq : out std_logic; --misc clkdiv10 : in std_logic_vector(7 downto 0); dcrstval : in std_logic_vector(9 downto 0); timerrstval : in std_logic_vector(11 downto 0); --rmapen rmapen : in std_ulogic; rmapnodeaddr : in std_logic_vector(7 downto 0); --rx ahb fifo rxrenable : out std_ulogic; rxraddress : out std_logic_vector(5 downto 0); rxwrite : out std_ulogic; rxwdata : out std_logic_vector(31 downto 0); rxwaddress : out std_logic_vector(5 downto 0); rxrdata : in std_logic_vector(31 downto 0); --tx ahb fifo txrenable : out std_ulogic; txraddress : out std_logic_vector(5 downto 0); txwrite : out std_ulogic; txwdata : out std_logic_vector(31 downto 0); txwaddress : out std_logic_vector(5 downto 0); txrdata : in std_logic_vector(31 downto 0); --nchar fifo ncrenable : out std_ulogic; ncraddress : out std_logic_vector(5 downto 0); ncwrite : out std_ulogic; ncwdata : out std_logic_vector(9 downto 0); ncwaddress : out std_logic_vector(5 downto 0); ncrdata : in std_logic_vector(9 downto 0); --rmap buf rmrenable : out std_ulogic; rmraddress : out std_logic_vector(7 downto 0); rmwrite : out std_ulogic; rmwdata : out std_logic_vector(7 downto 0); rmwaddress : out std_logic_vector(7 downto 0); rmrdata : in std_logic_vector(7 downto 0); linkdis : out std_ulogic; testclk : in std_ulogic; testrst : in std_logic; testen : in std_logic; rxdav : out std_logic; rxdataout : out std_logic_vector(8 downto 0); loopback : out std_logic; -- interrupt dist. default values intpreload : in std_logic_vector(30 downto 0); inttreload : in std_logic_vector(30 downto 0); intiareload : in std_logic_vector(30 downto 0); intcreload : in std_logic_vector(30 downto 0); irqtxdefault : in std_logic_vector(4 downto 0); --SpW PnP enable pnpen : in std_ulogic; pnpuvendid : in std_logic_vector(15 downto 0); pnpuprodid : in std_logic_vector(15 downto 0); pnpusn : in std_logic_vector(31 downto 0) ); end component; component grlfpw_net generic (tech : integer := 0; pclow : integer range 0 to 2 := 2; dsu : integer range 0 to 1 := 1; disas : integer range 0 to 2 := 0; pipe : integer range 0 to 2 := 0 ); port ( rst : in std_ulogic; -- Reset clk : in std_ulogic; holdn : in std_ulogic; -- pipeline hold cpi_flush : in std_ulogic; -- pipeline flush cpi_exack : in std_ulogic; -- FP exception acknowledge cpi_a_rs1 : in std_logic_vector(4 downto 0); cpi_d_pc : in std_logic_vector(31 downto 0); cpi_d_inst : in std_logic_vector(31 downto 0); cpi_d_cnt : in std_logic_vector(1 downto 0); cpi_d_trap : in std_ulogic; cpi_d_annul : in std_ulogic; cpi_d_pv : in std_ulogic; cpi_a_pc : in std_logic_vector(31 downto 0); cpi_a_inst : in std_logic_vector(31 downto 0); cpi_a_cnt : in std_logic_vector(1 downto 0); cpi_a_trap : in std_ulogic; cpi_a_annul : in std_ulogic; cpi_a_pv : in std_ulogic; cpi_e_pc : in std_logic_vector(31 downto 0); cpi_e_inst : in std_logic_vector(31 downto 0); cpi_e_cnt : in std_logic_vector(1 downto 0); cpi_e_trap : in std_ulogic; cpi_e_annul : in std_ulogic; cpi_e_pv : in std_ulogic; cpi_m_pc : in std_logic_vector(31 downto 0); cpi_m_inst : in std_logic_vector(31 downto 0); cpi_m_cnt : in std_logic_vector(1 downto 0); cpi_m_trap : in std_ulogic; cpi_m_annul : in std_ulogic; cpi_m_pv : in std_ulogic; cpi_x_pc : in std_logic_vector(31 downto 0); cpi_x_inst : in std_logic_vector(31 downto 0); cpi_x_cnt : in std_logic_vector(1 downto 0); cpi_x_trap : in std_ulogic; cpi_x_annul : in std_ulogic; cpi_x_pv : in std_ulogic; cpi_lddata : in std_logic_vector(31 downto 0); -- load data cpi_dbg_enable : in std_ulogic; cpi_dbg_write : in std_ulogic; cpi_dbg_fsr : in std_ulogic; -- FSR access cpi_dbg_addr : in std_logic_vector(4 downto 0); cpi_dbg_data : in std_logic_vector(31 downto 0); cpo_data : out std_logic_vector(31 downto 0); -- store data cpo_exc : out std_logic; -- FP exception cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes cpo_ccv : out std_ulogic; -- FP condition codes valid cpo_ldlock : out std_logic; -- FP pipeline hold cpo_holdn : out std_ulogic; cpo_dbg_data : out std_logic_vector(31 downto 0); rfi1_rd1addr : out std_logic_vector(3 downto 0); rfi1_rd2addr : out std_logic_vector(3 downto 0); rfi1_wraddr : out std_logic_vector(3 downto 0); rfi1_wrdata : out std_logic_vector(31 downto 0); rfi1_ren1 : out std_ulogic; rfi1_ren2 : out std_ulogic; rfi1_wren : out std_ulogic; rfi2_rd1addr : out std_logic_vector(3 downto 0); rfi2_rd2addr : out std_logic_vector(3 downto 0); rfi2_wraddr : out std_logic_vector(3 downto 0); rfi2_wrdata : out std_logic_vector(31 downto 0); rfi2_ren1 : out std_ulogic; rfi2_ren2 : out std_ulogic; rfi2_wren : out std_ulogic; rfo1_data1 : in std_logic_vector(31 downto 0); rfo1_data2 : in std_logic_vector(31 downto 0); rfo2_data1 : in std_logic_vector(31 downto 0); rfo2_data2 : in std_logic_vector(31 downto 0) ); end component; component grfpw_net generic (tech : integer := 0; pclow : integer range 0 to 2 := 2; dsu : integer range 0 to 2 := 1; disas : integer range 0 to 2 := 0; pipe : integer range 0 to 2 := 0 ); port ( rst : in std_ulogic; -- Reset clk : in std_ulogic; holdn : in std_ulogic; -- pipeline hold cpi_flush : in std_ulogic; -- pipeline flush cpi_exack : in std_ulogic; -- FP exception acknowledge cpi_a_rs1 : in std_logic_vector(4 downto 0); cpi_d_pc : in std_logic_vector(31 downto 0); cpi_d_inst : in std_logic_vector(31 downto 0); cpi_d_cnt : in std_logic_vector(1 downto 0); cpi_d_trap : in std_ulogic; cpi_d_annul : in std_ulogic; cpi_d_pv : in std_ulogic; cpi_a_pc : in std_logic_vector(31 downto 0); cpi_a_inst : in std_logic_vector(31 downto 0); cpi_a_cnt : in std_logic_vector(1 downto 0); cpi_a_trap : in std_ulogic; cpi_a_annul : in std_ulogic; cpi_a_pv : in std_ulogic; cpi_e_pc : in std_logic_vector(31 downto 0); cpi_e_inst : in std_logic_vector(31 downto 0); cpi_e_cnt : in std_logic_vector(1 downto 0); cpi_e_trap : in std_ulogic; cpi_e_annul : in std_ulogic; cpi_e_pv : in std_ulogic; cpi_m_pc : in std_logic_vector(31 downto 0); cpi_m_inst : in std_logic_vector(31 downto 0); cpi_m_cnt : in std_logic_vector(1 downto 0); cpi_m_trap : in std_ulogic; cpi_m_annul : in std_ulogic; cpi_m_pv : in std_ulogic; cpi_x_pc : in std_logic_vector(31 downto 0); cpi_x_inst : in std_logic_vector(31 downto 0); cpi_x_cnt : in std_logic_vector(1 downto 0); cpi_x_trap : in std_ulogic; cpi_x_annul : in std_ulogic; cpi_x_pv : in std_ulogic; cpi_lddata : in std_logic_vector(31 downto 0); -- load data cpi_dbg_enable : in std_ulogic; cpi_dbg_write : in std_ulogic; cpi_dbg_fsr : in std_ulogic; -- FSR access cpi_dbg_addr : in std_logic_vector(4 downto 0); cpi_dbg_data : in std_logic_vector(31 downto 0); cpo_data : out std_logic_vector(31 downto 0); -- store data cpo_exc : out std_logic; -- FP exception cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes cpo_ccv : out std_ulogic; -- FP condition codes valid cpo_ldlock : out std_logic; -- FP pipeline hold cpo_holdn : out std_ulogic; cpo_dbg_data : out std_logic_vector(31 downto 0); rfi1_rd1addr : out std_logic_vector(3 downto 0); rfi1_rd2addr : out std_logic_vector(3 downto 0); rfi1_wraddr : out std_logic_vector(3 downto 0); rfi1_wrdata : out std_logic_vector(31 downto 0); rfi1_ren1 : out std_ulogic; rfi1_ren2 : out std_ulogic; rfi1_wren : out std_ulogic; rfi2_rd1addr : out std_logic_vector(3 downto 0); rfi2_rd2addr : out std_logic_vector(3 downto 0); rfi2_wraddr : out std_logic_vector(3 downto 0); rfi2_wrdata : out std_logic_vector(31 downto 0); rfi2_ren1 : out std_ulogic; rfi2_ren2 : out std_ulogic; rfi2_wren : out std_ulogic; rfo1_data1 : in std_logic_vector(31 downto 0); rfo1_data2 : in std_logic_vector(31 downto 0); rfo2_data1 : in std_logic_vector(31 downto 0); rfo2_data2 : in std_logic_vector(31 downto 0) ); end component; component leon3_net generic ( hindex : integer := 0; fabtech : integer range 0 to NTECH := DEFFABTECH; memtech : integer range 0 to NTECH := DEFMEMTECH; nwindows : integer range 2 to 32 := 8; dsu : integer range 0 to 1 := 0; fpu : integer range 0 to 63 := 0; v8 : integer range 0 to 63 := 0; cp : integer range 0 to 1 := 0; mac : integer range 0 to 1 := 0; pclow : integer range 0 to 2 := 2; notag : integer range 0 to 1 := 0; nwp : integer range 0 to 4 := 0; icen : integer range 0 to 1 := 0; irepl : integer range 0 to 3 := 2; isets : integer range 1 to 4 := 1; ilinesize : integer range 4 to 8 := 4; isetsize : integer range 1 to 256 := 1; isetlock : integer range 0 to 1 := 0; dcen : integer range 0 to 1 := 0; drepl : integer range 0 to 3 := 2; dsets : integer range 1 to 4 := 1; dlinesize : integer range 4 to 8 := 4; dsetsize : integer range 1 to 256 := 1; dsetlock : integer range 0 to 1 := 0; dsnoop : integer range 0 to 6 := 0; ilram : integer range 0 to 1 := 0; ilramsize : integer range 1 to 512 := 1; ilramstart : integer range 0 to 255 := 16#8e#; dlram : integer range 0 to 1 := 0; dlramsize : integer range 1 to 512 := 1; dlramstart : integer range 0 to 255 := 16#8f#; mmuen : integer range 0 to 1 := 0; itlbnum : integer range 2 to 64 := 8; dtlbnum : integer range 2 to 64 := 8; tlb_type : integer range 0 to 3 := 1; tlb_rep : integer range 0 to 1 := 0; lddel : integer range 1 to 2 := 2; disas : integer range 0 to 2 := 0; tbuf : integer range 0 to 128 := 0; pwd : integer range 0 to 2 := 2; svt : integer range 0 to 1 := 1; rstaddr : integer := 0; smp : integer range 0 to 15 := 0; iuft : integer range 0 to 4 := 0; fpft : integer range 0 to 4 := 0; cmft : integer range 0 to 1 := 0; cached : integer := 0; clk2x : integer := 1; scantest : integer := 0; mmupgsz : integer range 0 to 5 := 0; bp : integer := 1; npasi : integer range 0 to 1 := 0; pwrpsr : integer range 0 to 1 := 0 ); port ( clk : in std_ulogic; -- free-running clock gclk2 : in std_ulogic; -- gated 2x clock gfclk2 : in std_ulogic; -- gated 2x FPU clock clk2 : in std_ulogic; -- free-running 2x clock rstn : in std_ulogic; ahbi : in ahb_mst_in_type; ahbo : out ahb_mst_out_type; ahbsi : in ahb_slv_in_type; -- ahbso : in ahb_slv_out_vector; irqi_irl : in std_logic_vector(3 downto 0); irqi_rst : in std_ulogic; irqi_run : in std_ulogic; irqi_rstvec : in std_logic_vector(31 downto 12); irqi_iact : in std_ulogic; irqi_index : in std_logic_vector(3 downto 0); irqi_hrdrst : in std_ulogic; irqo_intack : out std_ulogic; irqo_irl : out std_logic_vector(3 downto 0); irqo_pwd : out std_ulogic; irqo_fpen : out std_ulogic; irqo_idle : out std_ulogic; dbgi_dsuen : in std_ulogic; -- DSU enable dbgi_denable : in std_ulogic; -- diagnostic register access enablee dbgi_dbreak : in std_ulogic; -- debug break-in dbgi_step : in std_ulogic; -- single step dbgi_halt : in std_ulogic; -- halt processor dbgi_reset : in std_ulogic; -- reset processor dbgi_dwrite : in std_ulogic; -- read/write dbgi_daddr : in std_logic_vector(23 downto 2); -- diagnostic address dbgi_ddata : in std_logic_vector(31 downto 0); -- diagnostic data dbgi_btrapa : in std_ulogic; -- break on IU trap dbgi_btrape : in std_ulogic; -- break on IU trap dbgi_berror : in std_ulogic; -- break on IU error mode dbgi_bwatch : in std_ulogic; -- break on IU watchpoint dbgi_bsoft : in std_ulogic; -- break on software breakpoint (TA 1) dbgi_tenable : in std_ulogic; dbgi_timer : in std_logic_vector(30 downto 0); dbgo_data : out std_logic_vector(31 downto 0); dbgo_crdy : out std_ulogic; dbgo_dsu : out std_ulogic; dbgo_dsumode : out std_ulogic; dbgo_error : out std_ulogic; dbgo_halt : out std_ulogic; dbgo_pwd : out std_ulogic; dbgo_idle : out std_ulogic; dbgo_ipend : out std_ulogic; dbgo_icnt : out std_ulogic; dbgo_fcnt : out std_ulogic; dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type dbgo_bpmiss : out std_ulogic; -- branch predict miss dbgo_istat_cmiss : out std_ulogic; dbgo_istat_tmiss : out std_ulogic; dbgo_istat_chold : out std_ulogic; dbgo_istat_mhold : out std_ulogic; dbgo_dstat_cmiss : out std_ulogic; dbgo_dstat_tmiss : out std_ulogic; dbgo_dstat_chold : out std_ulogic; dbgo_dstat_mhold : out std_ulogic; dbgo_wbhold : out std_ulogic; -- write buffer hold dbgo_su : out std_ulogic; -- fpui : out grfpu_in_type; -- fpuo : in grfpu_out_type; clken : in std_ulogic ); end component; component ssrctrl_net generic ( tech: Integer := 0; bus16: Integer := 1); port ( rst: in Std_Logic; clk: in Std_Logic; n_ahbsi_hsel: in Std_Logic_Vector(0 to 15); n_ahbsi_haddr: in Std_Logic_Vector(31 downto 0); n_ahbsi_hwrite: in Std_Logic; n_ahbsi_htrans: in Std_Logic_Vector(1 downto 0); n_ahbsi_hsize: in Std_Logic_Vector(2 downto 0); n_ahbsi_hburst: in Std_Logic_Vector(2 downto 0); n_ahbsi_hwdata: in Std_Logic_Vector(31 downto 0); n_ahbsi_hprot: in Std_Logic_Vector(3 downto 0); n_ahbsi_hready: in Std_Logic; n_ahbsi_hmaster: in Std_Logic_Vector(3 downto 0); n_ahbsi_hmastlock:in Std_Logic; n_ahbsi_hmbsel: in Std_Logic_Vector(0 to 3); n_ahbsi_hirq: in Std_Logic_Vector(31 downto 0); n_ahbso_hready: out Std_Logic; n_ahbso_hresp: out Std_Logic_Vector(1 downto 0); n_ahbso_hrdata: out Std_Logic_Vector(31 downto 0); n_ahbso_hsplit: out Std_Logic_Vector(15 downto 0); n_ahbso_hirq: out Std_Logic_Vector(31 downto 0); n_apbi_psel: in Std_Logic_Vector(0 to 15); n_apbi_penable: in Std_Logic; n_apbi_paddr: in Std_Logic_Vector(31 downto 0); n_apbi_pwrite: in Std_Logic; n_apbi_pwdata: in Std_Logic_Vector(31 downto 0); n_apbi_pirq: in Std_Logic_Vector(31 downto 0); n_apbo_prdata: out Std_Logic_Vector(31 downto 0); n_apbo_pirq: out Std_Logic_Vector(31 downto 0); n_sri_data: in Std_Logic_Vector(31 downto 0); n_sri_brdyn: in Std_Logic; n_sri_bexcn: in Std_Logic; n_sri_writen: in Std_Logic; n_sri_wrn: in Std_Logic_Vector(3 downto 0); n_sri_bwidth: in Std_Logic_Vector(1 downto 0); n_sri_sd: in Std_Logic_Vector(63 downto 0); n_sri_cb: in Std_Logic_Vector(7 downto 0); n_sri_scb: in Std_Logic_Vector(7 downto 0); n_sri_edac: in Std_Logic; n_sro_address: out Std_Logic_Vector(31 downto 0); n_sro_data: out Std_Logic_Vector(31 downto 0); n_sro_sddata: out Std_Logic_Vector(63 downto 0); n_sro_ramsn: out Std_Logic_Vector(7 downto 0); n_sro_ramoen: out Std_Logic_Vector(7 downto 0); n_sro_ramn: out Std_Logic; n_sro_romn: out Std_Logic; n_sro_mben: out Std_Logic_Vector(3 downto 0); n_sro_iosn: out Std_Logic; n_sro_romsn: out Std_Logic_Vector(7 downto 0); n_sro_oen: out Std_Logic; n_sro_writen: out Std_Logic; n_sro_wrn: out Std_Logic_Vector(3 downto 0); n_sro_bdrive: out Std_Logic_Vector(3 downto 0); n_sro_vbdrive: out Std_Logic_Vector(31 downto 0); n_sro_svbdrive: out Std_Logic_Vector(63 downto 0); n_sro_read: out Std_Logic; n_sro_sa: out Std_Logic_Vector(14 downto 0); n_sro_cb: out Std_Logic_Vector(7 downto 0); n_sro_scb: out Std_Logic_Vector(7 downto 0); n_sro_vcdrive: out Std_Logic_Vector(7 downto 0); n_sro_svcdrive: out Std_Logic_Vector(7 downto 0); n_sro_ce: out Std_Logic); end component; component ftsrctrl_net generic ( hindex : integer := 0; romaddr : integer := 0; rommask : integer := 16#ff0#; ramaddr : integer := 16#400#; rammask : integer := 16#ff0#; ioaddr : integer := 16#200#; iomask : integer := 16#ff0#; ramws : integer := 0; romws : integer := 2; iows : integer := 2; rmw : integer := 0; srbanks : integer range 1 to 8 := 1; banksz : integer range 0 to 15 := 15; rombanks : integer range 1 to 8 := 1; rombanksz : integer range 0 to 15 := 15; rombankszdef : integer range 0 to 15 := 15; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; edacen : integer range 0 to 1 := 1; errcnt : integer range 0 to 1 := 0; cntbits : integer range 1 to 8 := 1; wsreg : integer := 0; oepol : integer := 0; prom8en : integer := 0; netlist : integer := 0; tech : integer := 0 ); port ( rst: in Std_ULogic; clk: in Std_ULogic; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; sri_data: in Std_Logic_Vector(31 downto 0); -- Data bus address sri_brdyn: in Std_Logic; sri_bexcn: in Std_Logic; sri_writen: in Std_Logic; sri_wrn: in Std_Logic_Vector(3 downto 0); sri_bwidth: in Std_Logic_Vector(1 downto 0); sri_sd: in Std_Logic_Vector(63 downto 0); sri_cb: in Std_Logic_Vector(15 downto 0); sri_scb: in Std_Logic_Vector(15 downto 0); sri_edac: in Std_Logic; sro_address: out Std_Logic_Vector(31 downto 0); sro_data: out Std_Logic_Vector(31 downto 0); sro_sddata: out Std_Logic_Vector(63 downto 0); sro_ramsn: out Std_Logic_Vector(7 downto 0); sro_ramoen: out Std_Logic_Vector(7 downto 0); sro_ramn: out Std_ULogic; sro_romn: out Std_ULogic; sro_mben: out Std_Logic_Vector(3 downto 0); sro_iosn: out Std_Logic; sro_romsn: out Std_Logic_Vector(7 downto 0); sro_oen: out Std_Logic; sro_writen: out Std_Logic; sro_wrn: out Std_Logic_Vector(3 downto 0); sro_bdrive: out Std_Logic_Vector(3 downto 0); sro_vbdrive: out Std_Logic_Vector(31 downto 0); --vector bus drive sro_svbdrive: out Std_Logic_Vector(63 downto 0); --vector bus drive sdram sro_read: out Std_Logic; sro_sa: out Std_Logic_Vector(14 downto 0); sro_cb: out Std_Logic_Vector(15 downto 0); sro_scb: out Std_Logic_Vector(15 downto 0); sro_vcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sro_svcdrive: out Std_Logic_Vector(15 downto 0); --vector bus drive cb sdram sro_ce: out Std_ULogic; sdo_sdcke: out Std_Logic_Vector( 1 downto 0); -- clk en sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); -- chip sel sdo_sdwen: out Std_ULogic; -- write en sdo_rasn: out Std_ULogic; -- row addr stb sdo_casn: out Std_ULogic; -- col addr stb sdo_dqm: out Std_Logic_Vector(15 downto 0); -- data i/o mask sdo_bdrive: out Std_ULogic; -- bus drive sdo_qdrive: out Std_ULogic; -- bus drive sdo_vbdrive: out Std_Logic_Vector(31 downto 0); -- vector bus drive sdo_address: out Std_Logic_Vector(16 downto 2); -- address out sdo_data: out Std_Logic_Vector(127 downto 0); -- data out sdo_cb: out Std_Logic_Vector(15 downto 0); sdo_ce: out Std_ULogic; sdo_ba: out Std_Logic_Vector(2 downto 0)); -- bank address end component; component grlfpw4_net generic (tech : integer := 0; pclow : integer range 0 to 2 := 2; dsu : integer range 0 to 1 := 1; disas : integer range 0 to 2 := 0; pipe : integer range 0 to 2 := 0; wrt : integer range 0 to 2 := 0 ); port ( rst : in std_ulogic; -- Reset clk : in std_ulogic; holdn : in std_ulogic; -- pipeline hold cpi_flush : in std_ulogic; -- pipeline flush cpi_exack : in std_ulogic; -- FP exception acknowledge cpi_a_rs1 : in std_logic_vector(4 downto 0); cpi_d_pc : in std_logic_vector(31 downto 0); cpi_d_inst : in std_logic_vector(31 downto 0); cpi_d_cnt : in std_logic_vector(1 downto 0); cpi_d_trap : in std_ulogic; cpi_d_annul : in std_ulogic; cpi_d_pv : in std_ulogic; cpi_a_pc : in std_logic_vector(31 downto 0); cpi_a_inst : in std_logic_vector(31 downto 0); cpi_a_cnt : in std_logic_vector(1 downto 0); cpi_a_trap : in std_ulogic; cpi_a_annul : in std_ulogic; cpi_a_pv : in std_ulogic; cpi_e_pc : in std_logic_vector(31 downto 0); cpi_e_inst : in std_logic_vector(31 downto 0); cpi_e_cnt : in std_logic_vector(1 downto 0); cpi_e_trap : in std_ulogic; cpi_e_annul : in std_ulogic; cpi_e_pv : in std_ulogic; cpi_m_pc : in std_logic_vector(31 downto 0); cpi_m_inst : in std_logic_vector(31 downto 0); cpi_m_cnt : in std_logic_vector(1 downto 0); cpi_m_trap : in std_ulogic; cpi_m_annul : in std_ulogic; cpi_m_pv : in std_ulogic; cpi_x_pc : in std_logic_vector(31 downto 0); cpi_x_inst : in std_logic_vector(31 downto 0); cpi_x_cnt : in std_logic_vector(1 downto 0); cpi_x_trap : in std_ulogic; cpi_x_annul : in std_ulogic; cpi_x_pv : in std_ulogic; cpi_lddata : in std_logic_vector(63 downto 0); -- load data cpi_dbg_enable : in std_ulogic; cpi_dbg_write : in std_ulogic; cpi_dbg_fsr : in std_ulogic; -- FSR access cpi_dbg_addr : in std_logic_vector(4 downto 0); cpi_dbg_data : in std_logic_vector(31 downto 0); cpo_data : out std_logic_vector(63 downto 0); -- store data cpo_exc : out std_logic; -- FP exception cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes cpo_ccv : out std_ulogic; -- FP condition codes valid cpo_ldlock : out std_logic; -- FP pipeline hold cpo_holdn : out std_ulogic; cpo_dbg_data : out std_logic_vector(31 downto 0); rfi1_rd1addr : out std_logic_vector(3 downto 0); rfi1_rd2addr : out std_logic_vector(3 downto 0); rfi1_wraddr : out std_logic_vector(3 downto 0); rfi1_wrdata : out std_logic_vector(31 downto 0); rfi1_ren1 : out std_ulogic; rfi1_ren2 : out std_ulogic; rfi1_wren : out std_ulogic; rfi2_rd1addr : out std_logic_vector(3 downto 0); rfi2_rd2addr : out std_logic_vector(3 downto 0); rfi2_wraddr : out std_logic_vector(3 downto 0); rfi2_wrdata : out std_logic_vector(31 downto 0); rfi2_ren1 : out std_ulogic; rfi2_ren2 : out std_ulogic; rfi2_wren : out std_ulogic; rfo1_data1 : in std_logic_vector(31 downto 0); rfo1_data2 : in std_logic_vector(31 downto 0); rfo2_data1 : in std_logic_vector(31 downto 0); rfo2_data2 : in std_logic_vector(31 downto 0) ); end component; component grfpw4_net generic (tech : integer := 0; pclow : integer range 0 to 2 := 2; dsu : integer range 0 to 2 := 1; disas : integer range 0 to 2 := 0; pipe : integer range 0 to 2 := 0 ); port ( rst : in std_ulogic; -- Reset clk : in std_ulogic; fpuclk : in std_ulogic; holdn : in std_ulogic; -- pipeline hold cpi_flush : in std_ulogic; -- pipeline flush cpi_exack : in std_ulogic; -- FP exception acknowledge cpi_a_rs1 : in std_logic_vector(4 downto 0); cpi_d_pc : in std_logic_vector(31 downto 0); cpi_d_inst : in std_logic_vector(31 downto 0); cpi_d_cnt : in std_logic_vector(1 downto 0); cpi_d_trap : in std_ulogic; cpi_d_annul : in std_ulogic; cpi_d_pv : in std_ulogic; cpi_a_pc : in std_logic_vector(31 downto 0); cpi_a_inst : in std_logic_vector(31 downto 0); cpi_a_cnt : in std_logic_vector(1 downto 0); cpi_a_trap : in std_ulogic; cpi_a_annul : in std_ulogic; cpi_a_pv : in std_ulogic; cpi_e_pc : in std_logic_vector(31 downto 0); cpi_e_inst : in std_logic_vector(31 downto 0); cpi_e_cnt : in std_logic_vector(1 downto 0); cpi_e_trap : in std_ulogic; cpi_e_annul : in std_ulogic; cpi_e_pv : in std_ulogic; cpi_m_pc : in std_logic_vector(31 downto 0); cpi_m_inst : in std_logic_vector(31 downto 0); cpi_m_cnt : in std_logic_vector(1 downto 0); cpi_m_trap : in std_ulogic; cpi_m_annul : in std_ulogic; cpi_m_pv : in std_ulogic; cpi_x_pc : in std_logic_vector(31 downto 0); cpi_x_inst : in std_logic_vector(31 downto 0); cpi_x_cnt : in std_logic_vector(1 downto 0); cpi_x_trap : in std_ulogic; cpi_x_annul : in std_ulogic; cpi_x_pv : in std_ulogic; cpi_lddata : in std_logic_vector(63 downto 0); -- load data cpi_dbg_enable : in std_ulogic; cpi_dbg_write : in std_ulogic; cpi_dbg_fsr : in std_ulogic; -- FSR access cpi_dbg_addr : in std_logic_vector(4 downto 0); cpi_dbg_data : in std_logic_vector(31 downto 0); cpo_data : out std_logic_vector(63 downto 0); -- store data cpo_exc : out std_logic; -- FP exception cpo_cc : out std_logic_vector(1 downto 0); -- FP condition codes cpo_ccv : out std_ulogic; -- FP condition codes valid cpo_ldlock : out std_logic; -- FP pipeline hold cpo_holdn : out std_ulogic; cpo_dbg_data : out std_logic_vector(31 downto 0); rfi1_rd1addr : out std_logic_vector(3 downto 0); rfi1_rd2addr : out std_logic_vector(3 downto 0); rfi1_wraddr : out std_logic_vector(3 downto 0); rfi1_wrdata : out std_logic_vector(31 downto 0); rfi1_ren1 : out std_ulogic; rfi1_ren2 : out std_ulogic; rfi1_wren : out std_ulogic; rfi2_rd1addr : out std_logic_vector(3 downto 0); rfi2_rd2addr : out std_logic_vector(3 downto 0); rfi2_wraddr : out std_logic_vector(3 downto 0); rfi2_wrdata : out std_logic_vector(31 downto 0); rfi2_ren1 : out std_ulogic; rfi2_ren2 : out std_ulogic; rfi2_wren : out std_ulogic; rfo1_data1 : in std_logic_vector(31 downto 0); rfo1_data2 : in std_logic_vector(31 downto 0); rfo2_data1 : in std_logic_vector(31 downto 0); rfo2_data2 : in std_logic_vector(31 downto 0) ); end component; component spictrl_net generic ( tech : integer range 0 to NTECH := 0; fdepth : integer range 1 to 7 := 1; slvselen : integer range 0 to 1 := 0; slvselsz : integer range 1 to 32 := 1; oepol : integer range 0 to 1 := 0; odmode : integer range 0 to 1 := 0; automode : integer range 0 to 1 := 0; acntbits : integer range 1 to 32 := 32; aslvsel : integer range 0 to 1 := 0; twen : integer range 0 to 1 := 1; maxwlen : integer range 0 to 15 := 0; automask0 : integer := 0; automask1 : integer := 0; automask2 : integer := 0; automask3 : integer := 0); port ( rstn : in std_ulogic; clk : in std_ulogic; apbi_psel : in std_ulogic; apbi_penable : in std_ulogic; apbi_paddr : in std_logic_vector(31 downto 0); apbi_pwrite : in std_ulogic; apbi_pwdata : in std_logic_vector(31 downto 0); apbi_testen : in std_ulogic; apbi_testrst : in std_ulogic; apbi_scanen : in std_ulogic; apbi_testoen : in std_ulogic; apbo_prdata : out std_logic_vector(31 downto 0); apbo_pirq : out std_ulogic; spii_miso : in std_ulogic; spii_mosi : in std_ulogic; spii_sck : in std_ulogic; spii_spisel : in std_ulogic; spii_astart : in std_ulogic; spii_cstart : in std_ulogic; spio_miso : out std_ulogic; spio_misooen : out std_ulogic; spio_mosi : out std_ulogic; spio_mosioen : out std_ulogic; spio_sck : out std_ulogic; spio_sckoen : out std_ulogic; spio_enable : out std_ulogic; spio_astart : out std_ulogic; spio_aready : out std_ulogic; slvsel : out std_logic_vector((slvselsz-1) downto 0)); end component; component leon4_net generic ( hindex : integer := 0; fabtech : integer range 0 to NTECH := DEFFABTECH; memtech : integer range 0 to NTECH := DEFMEMTECH; nwindows : integer range 2 to 32 := 8; dsu : integer range 0 to 1 := 0; fpu : integer range 0 to 31 := 0; v8 : integer range 0 to 63 := 0; cp : integer range 0 to 1 := 0; mac : integer range 0 to 1 := 0; pclow : integer range 0 to 2 := 2; notag : integer range 0 to 1 := 0; nwp : integer range 0 to 4 := 0; icen : integer range 0 to 1 := 0; irepl : integer range 0 to 2 := 2; isets : integer range 1 to 4 := 1; ilinesize : integer range 4 to 8 := 4; isetsize : integer range 1 to 256 := 1; isetlock : integer range 0 to 1 := 0; dcen : integer range 0 to 1 := 0; drepl : integer range 0 to 2 := 2; dsets : integer range 1 to 4 := 1; dlinesize : integer range 4 to 8 := 4; dsetsize : integer range 1 to 256 := 1; dsetlock : integer range 0 to 1 := 0; dsnoop : integer range 0 to 6 := 0; ilram : integer range 0 to 1 := 0; ilramsize : integer range 1 to 512 := 1; ilramstart : integer range 0 to 255 := 16#8e#; dlram : integer range 0 to 1 := 0; dlramsize : integer range 1 to 512 := 1; dlramstart : integer range 0 to 255 := 16#8f#; mmuen : integer range 0 to 1 := 0; itlbnum : integer range 2 to 64 := 8; dtlbnum : integer range 2 to 64 := 8; tlb_type : integer range 0 to 3 := 1; tlb_rep : integer range 0 to 1 := 0; lddel : integer range 1 to 2 := 2; disas : integer range 0 to 2 := 0; tbuf : integer range 0 to 64 := 0; pwd : integer range 0 to 2 := 2; -- power-down svt : integer range 0 to 1 := 1; -- single vector trapping rstaddr : integer := 0; smp : integer range 0 to 31 := 0; -- support SMP systems iuft : integer range 0 to 4 := 0; fpft : integer range 0 to 4 := 0; cmft : integer range 0 to 1 := 0; cached : integer := 0; scantest : integer := 0 ); port ( clk : in std_ulogic; gclk : in std_ulogic; hclken : in std_ulogic; rstn : in std_ulogic; ahbix : in ahb_mst_in_type; ahbox : out ahb_mst_out_type; ahbsix : in ahb_slv_in_type; ahbso : in ahb_slv_out_vector; irqi_irl: in std_logic_vector(3 downto 0); irqi_rst: in std_ulogic; irqi_run: in std_ulogic; irqi_rstvec: in std_logic_vector(31 downto 12); irqi_iact: in std_ulogic; irqi_index: in std_logic_vector(3 downto 0); irqi_hrdrst: in std_ulogic; irqo_intack: out std_ulogic; irqo_irl: out std_logic_vector(3 downto 0); irqo_pwd: out std_ulogic; irqo_fpen: out std_ulogic; irqo_idle: out std_ulogic; dbgi_dsuen: in std_ulogic; -- DSU enable dbgi_denable: in std_ulogic; -- diagnostic register access enable dbgi_dbreak: in std_ulogic; -- debug break-in dbgi_step: in std_ulogic; -- single step dbgi_halt: in std_ulogic; -- halt processor dbgi_reset: in std_ulogic; -- reset processor dbgi_dwrite: in std_ulogic; -- read/write dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data dbgi_btrapa: in std_ulogic; -- break on IU trap dbgi_btrape: in std_ulogic; -- break on IU trap dbgi_berror: in std_ulogic; -- break on IU error mode dbgi_bwatch: in std_ulogic; -- break on IU watchpoint dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1) dbgi_tenable: in std_ulogic; dbgi_timer: in std_logic_vector(63 downto 0); dbgo_data: out std_logic_vector(31 downto 0); dbgo_crdy: out std_ulogic; dbgo_dsu: out std_ulogic; dbgo_dsumode: out std_ulogic; dbgo_error: out std_ulogic; dbgo_halt: out std_ulogic; dbgo_pwd: out std_ulogic; dbgo_idle: out std_ulogic; dbgo_ipend: out std_ulogic; dbgo_icnt: out std_ulogic; dbgo_fcnt : out std_ulogic; dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type dbgo_bpmiss : out std_ulogic; -- branch predict miss dbgo_istat_cmiss: out std_ulogic; dbgo_istat_tmiss: out std_ulogic; dbgo_istat_chold: out std_ulogic; dbgo_istat_mhold: out std_ulogic; dbgo_dstat_cmiss: out std_ulogic; dbgo_dstat_tmiss: out std_ulogic; dbgo_dstat_chold: out std_ulogic; dbgo_dstat_mhold: out std_ulogic; dbgo_wbhold : out std_ulogic; -- write buffer hold dbgo_su : out std_ulogic; dbgo_ducnt : out std_ulogic); end component; component grpci2_phy_net is generic( tech : integer := DEFMEMTECH; oepol : integer := 0; bypass : integer range 0 to 1 := 1; netlist : integer := 0 ); port( pciclk : in std_logic; pcii_rst : in std_ulogic; pcii_gnt : in std_ulogic; pcii_idsel : in std_ulogic; pcii_ad : in std_logic_vector(31 downto 0); pcii_cbe : in std_logic_vector(3 downto 0); pcii_frame : in std_ulogic; pcii_irdy : in std_ulogic; pcii_trdy : in std_ulogic; pcii_devsel : in std_ulogic; pcii_stop : in std_ulogic; pcii_lock : in std_ulogic; pcii_perr : in std_ulogic; pcii_serr : in std_ulogic; pcii_par : in std_ulogic; pcii_host : in std_ulogic; pcii_pci66 : in std_ulogic; pcii_pme_status : in std_ulogic; pcii_int : in std_logic_vector(3 downto 0); phyi_pcirstout : in std_logic; phyi_pciasyncrst : in std_logic; phyi_pcisoftrst : in std_logic_vector(2 downto 0); phyi_pciinten : in std_logic_vector(3 downto 0); phyi_m_request : in std_logic; phyi_m_mabort : in std_logic; phyi_pr_m_fstate : in std_logic_vector(1 downto 0); phyi_pr_m_cfifo_0_data : in std_logic_vector(31 downto 0); phyi_pr_m_cfifo_0_last : in std_logic; phyi_pr_m_cfifo_0_stlast : in std_logic; phyi_pr_m_cfifo_0_hold : in std_logic; phyi_pr_m_cfifo_0_valid : in std_logic; phyi_pr_m_cfifo_0_err : in std_logic; phyi_pr_m_cfifo_1_data : in std_logic_vector(31 downto 0); phyi_pr_m_cfifo_1_last : in std_logic; phyi_pr_m_cfifo_1_stlast : in std_logic; phyi_pr_m_cfifo_1_hold : in std_logic; phyi_pr_m_cfifo_1_valid : in std_logic; phyi_pr_m_cfifo_1_err : in std_logic; phyi_pr_m_cfifo_2_data : in std_logic_vector(31 downto 0); phyi_pr_m_cfifo_2_last : in std_logic; phyi_pr_m_cfifo_2_stlast : in std_logic; phyi_pr_m_cfifo_2_hold : in std_logic; phyi_pr_m_cfifo_2_valid : in std_logic; phyi_pr_m_cfifo_2_err : in std_logic; phyi_pv_m_cfifo_0_data : in std_logic_vector(31 downto 0); phyi_pv_m_cfifo_0_last : in std_logic; phyi_pv_m_cfifo_0_stlast : in std_logic; phyi_pv_m_cfifo_0_hold : in std_logic; phyi_pv_m_cfifo_0_valid : in std_logic; phyi_pv_m_cfifo_0_err : in std_logic; phyi_pv_m_cfifo_1_data : in std_logic_vector(31 downto 0); phyi_pv_m_cfifo_1_last : in std_logic; phyi_pv_m_cfifo_1_stlast : in std_logic; phyi_pv_m_cfifo_1_hold : in std_logic; phyi_pv_m_cfifo_1_valid : in std_logic; phyi_pv_m_cfifo_1_err : in std_logic; phyi_pv_m_cfifo_2_data : in std_logic_vector(31 downto 0); phyi_pv_m_cfifo_2_last : in std_logic; phyi_pv_m_cfifo_2_stlast : in std_logic; phyi_pv_m_cfifo_2_hold : in std_logic; phyi_pv_m_cfifo_2_valid : in std_logic; phyi_pv_m_cfifo_2_err : in std_logic; phyi_pr_m_addr : in std_logic_vector(31 downto 0); phyi_pr_m_cbe_data : in std_logic_vector(3 downto 0); phyi_pr_m_cbe_cmd : in std_logic_vector(3 downto 0); phyi_pr_m_first : in std_logic_vector(1 downto 0); phyi_pv_m_term : in std_logic_vector(1 downto 0); phyi_pr_m_ltimer : in std_logic_vector(7 downto 0); phyi_pr_m_burst : in std_logic; phyi_pr_m_abort : in std_logic_vector(0 downto 0); phyi_pr_m_perren : in std_logic_vector(0 downto 0); phyi_pr_m_done_fifo : in std_logic; phyi_t_abort : in std_logic; phyi_t_ready : in std_logic; phyi_t_retry : in std_logic; phyi_pr_t_state : in std_logic_vector(2 downto 0); phyi_pv_t_state : in std_logic_vector(2 downto 0); phyi_pr_t_fstate : in std_logic_vector(1 downto 0); phyi_pr_t_cfifo_0_data : in std_logic_vector(31 downto 0); phyi_pr_t_cfifo_0_last : in std_logic; phyi_pr_t_cfifo_0_stlast : in std_logic; phyi_pr_t_cfifo_0_hold : in std_logic; phyi_pr_t_cfifo_0_valid : in std_logic; phyi_pr_t_cfifo_0_err : in std_logic; phyi_pr_t_cfifo_1_data : in std_logic_vector(31 downto 0); phyi_pr_t_cfifo_1_last : in std_logic; phyi_pr_t_cfifo_1_stlast : in std_logic; phyi_pr_t_cfifo_1_hold : in std_logic; phyi_pr_t_cfifo_1_valid : in std_logic; phyi_pr_t_cfifo_1_err : in std_logic; phyi_pr_t_cfifo_2_data : in std_logic_vector(31 downto 0); phyi_pr_t_cfifo_2_last : in std_logic; phyi_pr_t_cfifo_2_stlast : in std_logic; phyi_pr_t_cfifo_2_hold : in std_logic; phyi_pr_t_cfifo_2_valid : in std_logic; phyi_pr_t_cfifo_2_err : in std_logic; phyi_pv_t_diswithout : in std_logic; phyi_pr_t_stoped : in std_logic; phyi_pr_t_lcount : in std_logic_vector(2 downto 0); phyi_pr_t_first_word : in std_logic; phyi_pr_t_cur_acc_0_read : in std_logic; phyi_pv_t_hold_write : in std_logic; phyi_pv_t_hold_reset : in std_logic; phyi_pr_conf_comm_perren : in std_logic; phyi_pr_conf_comm_serren : in std_logic; pcio_aden : out std_ulogic; pcio_vaden : out std_logic_vector(31 downto 0); pcio_cbeen : out std_logic_vector(3 downto 0); pcio_frameen : out std_ulogic; pcio_irdyen : out std_ulogic; pcio_trdyen : out std_ulogic; pcio_devselen : out std_ulogic; pcio_stopen : out std_ulogic; pcio_ctrlen : out std_ulogic; pcio_perren : out std_ulogic; pcio_paren : out std_ulogic; pcio_reqen : out std_ulogic; pcio_locken : out std_ulogic; pcio_serren : out std_ulogic; pcio_inten : out std_ulogic; pcio_vinten : out std_logic_vector(3 downto 0); pcio_req : out std_ulogic; pcio_ad : out std_logic_vector(31 downto 0); pcio_cbe : out std_logic_vector(3 downto 0); pcio_frame : out std_ulogic; pcio_irdy : out std_ulogic; pcio_trdy : out std_ulogic; pcio_devsel : out std_ulogic; pcio_stop : out std_ulogic; pcio_perr : out std_ulogic; pcio_serr : out std_ulogic; pcio_par : out std_ulogic; pcio_lock : out std_ulogic; pcio_power_state : out std_logic_vector(1 downto 0); pcio_pme_enable : out std_ulogic; pcio_pme_clear : out std_ulogic; pcio_int : out std_ulogic; pcio_rst : out std_ulogic; phyo_pciv_rst : out std_ulogic; phyo_pciv_gnt : out std_ulogic; phyo_pciv_idsel : out std_ulogic; phyo_pciv_ad : out std_logic_vector(31 downto 0); phyo_pciv_cbe : out std_logic_vector(3 downto 0); phyo_pciv_frame : out std_ulogic; phyo_pciv_irdy : out std_ulogic; phyo_pciv_trdy : out std_ulogic; phyo_pciv_devsel : out std_ulogic; phyo_pciv_stop : out std_ulogic; phyo_pciv_lock : out std_ulogic; phyo_pciv_perr : out std_ulogic; phyo_pciv_serr : out std_ulogic; phyo_pciv_par : out std_ulogic; phyo_pciv_host : out std_ulogic; phyo_pciv_pci66 : out std_ulogic; phyo_pciv_pme_status : out std_ulogic; phyo_pciv_int : out std_logic_vector(3 downto 0); phyo_pr_m_state : out std_logic_vector(2 downto 0); phyo_pr_m_last : out std_logic_vector(1 downto 0); phyo_pr_m_hold : out std_logic_vector(1 downto 0); phyo_pr_m_term : out std_logic_vector(1 downto 0); phyo_pr_t_hold : out std_logic_vector(0 downto 0); phyo_pr_t_stop : out std_logic; phyo_pr_t_abort : out std_logic; phyo_pr_t_diswithout : out std_logic; phyo_pr_t_addr_perr : out std_logic; phyo_pcirsto : out std_logic_vector(0 downto 0); phyo_pr_po_ad : out std_logic_vector(31 downto 0); phyo_pr_po_aden : out std_logic_vector(31 downto 0); phyo_pr_po_cbe : out std_logic_vector(3 downto 0); phyo_pr_po_cbeen : out std_logic_vector(3 downto 0); phyo_pr_po_frame : out std_logic; phyo_pr_po_frameen : out std_logic; phyo_pr_po_irdy : out std_logic; phyo_pr_po_irdyen : out std_logic; phyo_pr_po_trdy : out std_logic; phyo_pr_po_trdyen : out std_logic; phyo_pr_po_stop : out std_logic; phyo_pr_po_stopen : out std_logic; phyo_pr_po_devsel : out std_logic; phyo_pr_po_devselen : out std_logic; phyo_pr_po_par : out std_logic; phyo_pr_po_paren : out std_logic; phyo_pr_po_perr : out std_logic; phyo_pr_po_perren : out std_logic; phyo_pr_po_lock : out std_logic; phyo_pr_po_locken : out std_logic; phyo_pr_po_req : out std_logic; phyo_pr_po_reqen : out std_logic; phyo_pr_po_serren : out std_logic; phyo_pr_po_inten : out std_logic; phyo_pr_po_vinten : out std_logic_vector(3 downto 0); phyo_pio_rst : out std_ulogic; phyo_pio_gnt : out std_ulogic; phyo_pio_idsel : out std_ulogic; phyo_pio_ad : out std_logic_vector(31 downto 0); phyo_pio_cbe : out std_logic_vector(3 downto 0); phyo_pio_frame : out std_ulogic; phyo_pio_irdy : out std_ulogic; phyo_pio_trdy : out std_ulogic; phyo_pio_devsel : out std_ulogic; phyo_pio_stop : out std_ulogic; phyo_pio_lock : out std_ulogic; phyo_pio_perr : out std_ulogic; phyo_pio_serr : out std_ulogic; phyo_pio_par : out std_ulogic; phyo_pio_host : out std_ulogic; phyo_pio_pci66 : out std_ulogic; phyo_pio_pme_status : out std_ulogic; phyo_pio_int : out std_logic_vector(3 downto 0); phyo_poo_ad : out std_logic_vector(31 downto 0); phyo_poo_aden : out std_logic_vector(31 downto 0); phyo_poo_cbe : out std_logic_vector(3 downto 0); phyo_poo_cbeen : out std_logic_vector(3 downto 0); phyo_poo_frame : out std_logic; phyo_poo_frameen : out std_logic; phyo_poo_irdy : out std_logic; phyo_poo_irdyen : out std_logic; phyo_poo_trdy : out std_logic; phyo_poo_trdyen : out std_logic; phyo_poo_stop : out std_logic; phyo_poo_stopen : out std_logic; phyo_poo_devsel : out std_logic; phyo_poo_devselen : out std_logic; phyo_poo_par : out std_logic; phyo_poo_paren : out std_logic; phyo_poo_perr : out std_logic; phyo_poo_perren : out std_logic; phyo_poo_lock : out std_logic; phyo_poo_locken : out std_logic; phyo_poo_req : out std_logic; phyo_poo_reqen : out std_logic; phyo_poo_serren : out std_logic; phyo_poo_inten : out std_logic; phyo_poo_vinten : out std_logic_vector(3 downto 0) ); end component; end;
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Wed Sep 20 21:07:50 2017 -- Host : EffulgentTome running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_0_sim_netlist.vhdl -- Design : zqynq_lab_1_design_axi_gpio_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is port ( D : out STD_LOGIC_VECTOR ( 7 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 ); GPIO_xferAck_i : out STD_LOGIC; gpio_xferAck_Reg : out STD_LOGIC; ip2bus_rdack_i : out STD_LOGIC; ip2bus_wrack_i_D1_reg : out STD_LOGIC; gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 ); bus2ip_rnw_i_reg : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; SS : in STD_LOGIC_VECTOR ( 0 to 0 ); bus2ip_rnw : in STD_LOGIC; bus2ip_cs : in STD_LOGIC; E : in STD_LOGIC_VECTOR ( 0 to 0 ); \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is signal \^gpio_xferack_i\ : STD_LOGIC; signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^gpio_xferack_reg\ : STD_LOGIC; signal iGPIO_xferAck : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4"; attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4"; begin GPIO_xferAck_i <= \^gpio_xferack_i\; gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0); gpio_xferAck_Reg <= \^gpio_xferack_reg\; \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(7), Q => D(7), R => bus2ip_rnw_i_reg ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(6), Q => D(6), R => bus2ip_rnw_i_reg ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(5), Q => D(5), R => bus2ip_rnw_i_reg ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(4), Q => D(4), R => bus2ip_rnw_i_reg ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(3), Q => D(3), R => bus2ip_rnw_i_reg ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(2), Q => D(2), R => bus2ip_rnw_i_reg ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(1), Q => D(1), R => bus2ip_rnw_i_reg ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_io_o\(0), Q => D(0), R => bus2ip_rnw_i_reg ); \Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7), Q => \^gpio_io_o\(7), R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6), Q => \^gpio_io_o\(6), R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5), Q => \^gpio_io_o\(5), R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4), Q => \^gpio_io_o\(4), R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3), Q => \^gpio_io_o\(3), R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2), Q => \^gpio_io_o\(2), R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1), Q => \^gpio_io_o\(1), R => SS(0) ); \Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => E(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0), Q => \^gpio_io_o\(0), R => SS(0) ); \Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7), Q => gpio_io_t(7), S => SS(0) ); \Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6), Q => gpio_io_t(6), S => SS(0) ); \Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5), Q => gpio_io_t(5), S => SS(0) ); \Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4), Q => gpio_io_t(4), S => SS(0) ); \Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3), Q => gpio_io_t(3), S => SS(0) ); \Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2), Q => gpio_io_t(2), S => SS(0) ); \Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1), Q => gpio_io_t(1), S => SS(0) ); \Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => s_axi_aclk, CE => rst_reg(0), D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0), Q => gpio_io_t(0), S => SS(0) ); gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \^gpio_xferack_i\, Q => \^gpio_xferack_reg\, R => SS(0) ); iGPIO_xferAck_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => bus2ip_cs, I1 => \^gpio_xferack_reg\, I2 => \^gpio_xferack_i\, O => iGPIO_xferAck ); iGPIO_xferAck_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => iGPIO_xferAck, Q => \^gpio_xferack_i\, R => SS(0) ); ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^gpio_xferack_i\, I1 => bus2ip_rnw, O => ip2bus_rdack_i ); ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^gpio_xferack_i\, I1 => bus2ip_rnw, O => ip2bus_wrack_i_D1_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is port ( \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC; s_axi_wready : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 7 downto 0 ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; s_axi_aclk : in STD_LOGIC; rst_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); bus2ip_rnw_i_reg : in STD_LOGIC; ip2bus_rdack_i_D1 : in STD_LOGIC; is_read : in STD_LOGIC; \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); ip2bus_wrack_i_D1 : in STD_LOGIC; is_write_reg : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); start2_reg : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; gpio_xferAck_Reg : in STD_LOGIC; GPIO_xferAck_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC; signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC; signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; begin \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\; s_axi_arready <= \^s_axi_arready\; s_axi_wready <= \^s_axi_wready\; \MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000000E0" ) port map ( I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I1 => start2_reg, I2 => s_axi_aresetn, I3 => \^s_axi_arready\, I4 => \^s_axi_wready\, O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ ); \MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\, Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, R => '0' ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FFF7" ) port map ( I0 => bus2ip_rnw_i_reg, I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => gpio_xferAck_Reg, I3 => GPIO_xferAck_i, O => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ ); \Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAABAAAA" ) port map ( I0 => rst_reg, I1 => Q(1), I2 => bus2ip_rnw_i_reg, I3 => Q(0), I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I5 => Q(2), O => E(0) ); \Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(7), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(15), O => D(7) ); \Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(6), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(14), O => D(6) ); \Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(5), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(13), O => D(5) ); \Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(4), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(12), O => D(4) ); \Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(3), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(11), O => D(3) ); \Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(2), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(10), O => D(2) ); \Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(1), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(9), O => D(1) ); \Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FB08" ) port map ( I0 => s_axi_wdata(0), I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I2 => Q(1), I3 => s_axi_wdata(8), O => D(0) ); \Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAEAAAA" ) port map ( I0 => rst_reg, I1 => Q(0), I2 => Q(1), I3 => bus2ip_rnw_i_reg, I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\, I5 => Q(2), O => \Not_Dual.gpio_OE_reg[0]\(0) ); s_axi_arready_INST_0: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAEAAAA" ) port map ( I0 => ip2bus_rdack_i_D1, I1 => is_read, I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => \^s_axi_arready\ ); s_axi_wready_INST_0: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAEAAAA" ) port map ( I0 => ip2bus_wrack_i_D1, I1 => is_write_reg, I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1), I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3), I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0), O => \^s_axi_wready\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is port ( SR : out STD_LOGIC; \Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC; \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_arready : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 7 downto 0 ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; ip2bus_rdack_i_D1 : in STD_LOGIC; ip2bus_wrack_i_D1 : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_xferAck_Reg : in STD_LOGIC; GPIO_xferAck_i : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC; signal \^sr\ : STD_LOGIC; signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 ); signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC; signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC; signal bus2ip_rnw_i06_out : STD_LOGIC; signal clear : STD_LOGIC; signal is_read : STD_LOGIC; signal is_read_i_1_n_0 : STD_LOGIC; signal is_write : STD_LOGIC; signal is_write_i_1_n_0 : STD_LOGIC; signal is_write_reg_n_0 : STD_LOGIC; signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 ); signal p_1_in : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \^s_axi_arready\ : STD_LOGIC; signal \^s_axi_bvalid\ : STD_LOGIC; signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC; signal \s_axi_rdata_i[7]_i_1_n_0\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal start2 : STD_LOGIC; signal start2_i_1_n_0 : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \state1__2\ : STD_LOGIC; signal \state[1]_i_3_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1"; begin \Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\; SR <= \^sr\; s_axi_arready <= \^s_axi_arready\; s_axi_bvalid <= \^s_axi_bvalid\; s_axi_rvalid <= \^s_axi_rvalid\; s_axi_wready <= \^s_axi_wready\; \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), O => plusOp(0) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), O => plusOp(1) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), O => plusOp(2) ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => state(0), I1 => state(1), O => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), O => plusOp(3) ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(0), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(1), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(2), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2), R => clear ); \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => plusOp(3), Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3), R => clear ); I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder port map ( D(7 downto 0) => D(7 downto 0), E(0) => E(0), GPIO_xferAck_i => GPIO_xferAck_i, \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0), \MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\, \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\, \Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0), Q(2) => bus2ip_addr(0), Q(1) => bus2ip_addr(5), Q(0) => bus2ip_addr(6), bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\, gpio_xferAck_Reg => gpio_xferAck_Reg, ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, is_read => is_read, is_write_reg => is_write_reg_n_0, rst_reg => \^sr\, s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_arready => \^s_axi_arready\, s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0), s_axi_wready => \^s_axi_wready\, start2_reg => start2 ); \bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCACCCC" ) port map ( I0 => s_axi_araddr(0), I1 => s_axi_awaddr(0), I2 => state(0), I3 => state(1), I4 => s_axi_arvalid, O => \bus2ip_addr_i[2]_i_1_n_0\ ); \bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCACCCC" ) port map ( I0 => s_axi_araddr(1), I1 => s_axi_awaddr(1), I2 => state(0), I3 => state(1), I4 => s_axi_arvalid, O => \bus2ip_addr_i[3]_i_1_n_0\ ); \bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000000EA" ) port map ( I0 => s_axi_arvalid, I1 => s_axi_awvalid, I2 => s_axi_wvalid, I3 => state(1), I4 => state(0), O => \bus2ip_addr_i[8]_i_1_n_0\ ); \bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCACCCC" ) port map ( I0 => s_axi_araddr(2), I1 => s_axi_awaddr(2), I2 => state(0), I3 => state(1), I4 => s_axi_arvalid, O => \bus2ip_addr_i[8]_i_2_n_0\ ); \bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[8]_i_1_n_0\, D => \bus2ip_addr_i[2]_i_1_n_0\, Q => bus2ip_addr(6), R => \^sr\ ); \bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[8]_i_1_n_0\, D => \bus2ip_addr_i[3]_i_1_n_0\, Q => bus2ip_addr(5), R => \^sr\ ); \bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[8]_i_1_n_0\, D => \bus2ip_addr_i[8]_i_2_n_0\, Q => bus2ip_addr(0), R => \^sr\ ); bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"10" ) port map ( I0 => state(0), I1 => state(1), I2 => s_axi_arvalid, O => bus2ip_rnw_i06_out ); bus2ip_rnw_i_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => \bus2ip_addr_i[8]_i_1_n_0\, D => bus2ip_rnw_i06_out, Q => \^not_dual.gpio_data_out_reg[0]\, R => \^sr\ ); is_read_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"3FFA000A" ) port map ( I0 => s_axi_arvalid, I1 => \state1__2\, I2 => state(0), I3 => state(1), I4 => is_read, O => is_read_i_1_n_0 ); is_read_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => is_read_i_1_n_0, Q => is_read, R => \^sr\ ); is_write_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0040FFFF00400000" ) port map ( I0 => s_axi_arvalid, I1 => s_axi_awvalid, I2 => s_axi_wvalid, I3 => state(1), I4 => is_write, I5 => is_write_reg_n_0, O => is_write_i_1_n_0 ); is_write_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F88800000000FFFF" ) port map ( I0 => \^s_axi_rvalid\, I1 => s_axi_rready, I2 => \^s_axi_bvalid\, I3 => s_axi_bready, I4 => state(0), I5 => state(1), O => is_write ); is_write_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => is_write_i_1_n_0, Q => is_write_reg_n_0, R => \^sr\ ); rst_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s_axi_aresetn, O => p_1_in ); rst_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => p_1_in, Q => \^sr\, R => '0' ); s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"08FF0808" ) port map ( I0 => \^s_axi_wready\, I1 => state(1), I2 => state(0), I3 => s_axi_bready, I4 => \^s_axi_bvalid\, O => s_axi_bvalid_i_i_1_n_0 ); s_axi_bvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_axi_bvalid_i_i_1_n_0, Q => \^s_axi_bvalid\, R => \^sr\ ); \s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => state(0), I1 => state(1), O => \s_axi_rdata_i[7]_i_1_n_0\ ); \s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(0), Q => s_axi_rdata(0), R => \^sr\ ); \s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(1), Q => s_axi_rdata(1), R => \^sr\ ); \s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(2), Q => s_axi_rdata(2), R => \^sr\ ); \s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(3), Q => s_axi_rdata(3), R => \^sr\ ); \s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(4), Q => s_axi_rdata(4), R => \^sr\ ); \s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(5), Q => s_axi_rdata(5), R => \^sr\ ); \s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(6), Q => s_axi_rdata(6), R => \^sr\ ); \s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \s_axi_rdata_i[7]_i_1_n_0\, D => Q(7), Q => s_axi_rdata(7), R => \^sr\ ); s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"08FF0808" ) port map ( I0 => \^s_axi_arready\, I1 => state(0), I2 => state(1), I3 => s_axi_rready, I4 => \^s_axi_rvalid\, O => s_axi_rvalid_i_i_1_n_0 ); s_axi_rvalid_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_axi_rvalid_i_i_1_n_0, Q => \^s_axi_rvalid\, R => \^sr\ ); start2_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"000000F8" ) port map ( I0 => s_axi_awvalid, I1 => s_axi_wvalid, I2 => s_axi_arvalid, I3 => state(1), I4 => state(0), O => start2_i_1_n_0 ); start2_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => start2_i_1_n_0, Q => start2, R => \^sr\ ); \state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"77FC44FC" ) port map ( I0 => \state1__2\, I1 => state(0), I2 => s_axi_arvalid, I3 => state(1), I4 => \^s_axi_wready\, O => p_0_out(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"5FFC50FC" ) port map ( I0 => \state1__2\, I1 => \state[1]_i_3_n_0\, I2 => state(1), I3 => state(0), I4 => \^s_axi_arready\, O => p_0_out(1) ); \state[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => s_axi_bready, I1 => \^s_axi_bvalid\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => \state1__2\ ); \state[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => s_axi_wvalid, I1 => s_axi_awvalid, I2 => s_axi_arvalid, O => \state[1]_i_3_n_0\ ); \state_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => p_0_out(0), Q => state(0), R => \^sr\ ); \state_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => p_0_out(1), Q => state(1), R => \^sr\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is port ( bus2ip_reset : out STD_LOGIC; bus2ip_rnw : out STD_LOGIC; bus2ip_cs : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_arready : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); \Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 7 downto 0 ); \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; ip2bus_rdack_i_D1 : in STD_LOGIC; ip2bus_wrack_i_D1 : in STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); gpio_xferAck_Reg : in STD_LOGIC; GPIO_xferAck_i : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is begin I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment port map ( D(7 downto 0) => D(7 downto 0), E(0) => E(0), GPIO_xferAck_i => GPIO_xferAck_i, \MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs, \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\, \Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw, \Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0), Q(7 downto 0) => Q(7 downto 0), SR => bus2ip_reset, gpio_xferAck_Reg => gpio_xferAck_Reg, ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, s_axi_aclk => s_axi_aclk, s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0), s_axi_wready => s_axi_wready, s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; ip2intc_irpt : out STD_LOGIC; gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 ); gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 ); gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 ); gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 ); gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 ); gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute C_ALL_INPUTS : integer; attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; attribute C_ALL_INPUTS_2 : integer; attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; attribute C_ALL_OUTPUTS : integer; attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1; attribute C_ALL_OUTPUTS_2 : integer; attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; attribute C_DOUT_DEFAULT : integer; attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; attribute C_DOUT_DEFAULT_2 : integer; attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq"; attribute C_GPIO2_WIDTH : integer; attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32; attribute C_GPIO_WIDTH : integer; attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 8; attribute C_INTERRUPT_PRESENT : integer; attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; attribute C_IS_DUAL : integer; attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32; attribute C_TRI_DEFAULT : integer; attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1; attribute C_TRI_DEFAULT_2 : integer; attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes"; attribute ip_group : string; attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is signal \<const0>\ : STD_LOGIC; signal \<const1>\ : STD_LOGIC; signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC; signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC; signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 7 ); signal GPIO_xferAck_i : STD_LOGIC; signal bus2ip_cs : STD_LOGIC; signal bus2ip_reset : STD_LOGIC; signal bus2ip_rnw : STD_LOGIC; signal gpio_core_1_n_19 : STD_LOGIC; signal gpio_xferAck_Reg : STD_LOGIC; signal ip2bus_data : STD_LOGIC_VECTOR ( 24 to 31 ); signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 24 to 31 ); signal ip2bus_rdack_i : STD_LOGIC; signal ip2bus_rdack_i_D1 : STD_LOGIC; signal ip2bus_wrack_i_D1 : STD_LOGIC; signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^s_axi_wready\ : STD_LOGIC; begin gpio2_io_o(31) <= \<const0>\; gpio2_io_o(30) <= \<const0>\; gpio2_io_o(29) <= \<const0>\; gpio2_io_o(28) <= \<const0>\; gpio2_io_o(27) <= \<const0>\; gpio2_io_o(26) <= \<const0>\; gpio2_io_o(25) <= \<const0>\; gpio2_io_o(24) <= \<const0>\; gpio2_io_o(23) <= \<const0>\; gpio2_io_o(22) <= \<const0>\; gpio2_io_o(21) <= \<const0>\; gpio2_io_o(20) <= \<const0>\; gpio2_io_o(19) <= \<const0>\; gpio2_io_o(18) <= \<const0>\; gpio2_io_o(17) <= \<const0>\; gpio2_io_o(16) <= \<const0>\; gpio2_io_o(15) <= \<const0>\; gpio2_io_o(14) <= \<const0>\; gpio2_io_o(13) <= \<const0>\; gpio2_io_o(12) <= \<const0>\; gpio2_io_o(11) <= \<const0>\; gpio2_io_o(10) <= \<const0>\; gpio2_io_o(9) <= \<const0>\; gpio2_io_o(8) <= \<const0>\; gpio2_io_o(7) <= \<const0>\; gpio2_io_o(6) <= \<const0>\; gpio2_io_o(5) <= \<const0>\; gpio2_io_o(4) <= \<const0>\; gpio2_io_o(3) <= \<const0>\; gpio2_io_o(2) <= \<const0>\; gpio2_io_o(1) <= \<const0>\; gpio2_io_o(0) <= \<const0>\; gpio2_io_t(31) <= \<const1>\; gpio2_io_t(30) <= \<const1>\; gpio2_io_t(29) <= \<const1>\; gpio2_io_t(28) <= \<const1>\; gpio2_io_t(27) <= \<const1>\; gpio2_io_t(26) <= \<const1>\; gpio2_io_t(25) <= \<const1>\; gpio2_io_t(24) <= \<const1>\; gpio2_io_t(23) <= \<const1>\; gpio2_io_t(22) <= \<const1>\; gpio2_io_t(21) <= \<const1>\; gpio2_io_t(20) <= \<const1>\; gpio2_io_t(19) <= \<const1>\; gpio2_io_t(18) <= \<const1>\; gpio2_io_t(17) <= \<const1>\; gpio2_io_t(16) <= \<const1>\; gpio2_io_t(15) <= \<const1>\; gpio2_io_t(14) <= \<const1>\; gpio2_io_t(13) <= \<const1>\; gpio2_io_t(12) <= \<const1>\; gpio2_io_t(11) <= \<const1>\; gpio2_io_t(10) <= \<const1>\; gpio2_io_t(9) <= \<const1>\; gpio2_io_t(8) <= \<const1>\; gpio2_io_t(7) <= \<const1>\; gpio2_io_t(6) <= \<const1>\; gpio2_io_t(5) <= \<const1>\; gpio2_io_t(4) <= \<const1>\; gpio2_io_t(3) <= \<const1>\; gpio2_io_t(2) <= \<const1>\; gpio2_io_t(1) <= \<const1>\; gpio2_io_t(0) <= \<const1>\; ip2intc_irpt <= \<const0>\; s_axi_awready <= \^s_axi_wready\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_rdata(31) <= \<const0>\; s_axi_rdata(30) <= \<const0>\; s_axi_rdata(29) <= \<const0>\; s_axi_rdata(28) <= \<const0>\; s_axi_rdata(27) <= \<const0>\; s_axi_rdata(26) <= \<const0>\; s_axi_rdata(25) <= \<const0>\; s_axi_rdata(24) <= \<const0>\; s_axi_rdata(23) <= \<const0>\; s_axi_rdata(22) <= \<const0>\; s_axi_rdata(21) <= \<const0>\; s_axi_rdata(20) <= \<const0>\; s_axi_rdata(19) <= \<const0>\; s_axi_rdata(18) <= \<const0>\; s_axi_rdata(17) <= \<const0>\; s_axi_rdata(16) <= \<const0>\; s_axi_rdata(15) <= \<const0>\; s_axi_rdata(14) <= \<const0>\; s_axi_rdata(13) <= \<const0>\; s_axi_rdata(12) <= \<const0>\; s_axi_rdata(11) <= \<const0>\; s_axi_rdata(10) <= \<const0>\; s_axi_rdata(9) <= \<const0>\; s_axi_rdata(8) <= \<const0>\; s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0); s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_wready <= \^s_axi_wready\; AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif port map ( D(7) => DBus_Reg(0), D(6) => DBus_Reg(1), D(5) => DBus_Reg(2), D(4) => DBus_Reg(3), D(3) => DBus_Reg(4), D(2) => DBus_Reg(5), D(1) => DBus_Reg(6), D(0) => DBus_Reg(7), E(0) => AXI_LITE_IPIF_I_n_6, GPIO_xferAck_i => GPIO_xferAck_i, \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17, \Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7, Q(7) => ip2bus_data_i_D1(24), Q(6) => ip2bus_data_i_D1(25), Q(5) => ip2bus_data_i_D1(26), Q(4) => ip2bus_data_i_D1(27), Q(3) => ip2bus_data_i_D1(28), Q(2) => ip2bus_data_i_D1(29), Q(1) => ip2bus_data_i_D1(30), Q(0) => ip2bus_data_i_D1(31), bus2ip_cs => bus2ip_cs, bus2ip_reset => bus2ip_reset, bus2ip_rnw => bus2ip_rnw, gpio_xferAck_Reg => gpio_xferAck_Reg, ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1, ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1, s_axi_aclk => s_axi_aclk, s_axi_araddr(2) => s_axi_araddr(8), s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(2) => s_axi_awaddr(8), s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2), s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0), s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(15 downto 8) => s_axi_wdata(31 downto 24), s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0), s_axi_wready => \^s_axi_wready\, s_axi_wvalid => s_axi_wvalid ); GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); VCC: unisim.vcomponents.VCC port map ( P => \<const1>\ ); gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core port map ( D(7) => ip2bus_data(24), D(6) => ip2bus_data(25), D(5) => ip2bus_data(26), D(4) => ip2bus_data(27), D(3) => ip2bus_data(28), D(2) => ip2bus_data(29), D(1) => ip2bus_data(30), D(0) => ip2bus_data(31), E(0) => AXI_LITE_IPIF_I_n_6, GPIO_xferAck_i => GPIO_xferAck_i, \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(0), \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(1), \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(2), \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(3), \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(4), \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(5), \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(6), \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(7), SS(0) => bus2ip_reset, bus2ip_cs => bus2ip_cs, bus2ip_rnw => bus2ip_rnw, bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_17, gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0), gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0), gpio_xferAck_Reg => gpio_xferAck_Reg, ip2bus_rdack_i => ip2bus_rdack_i, ip2bus_wrack_i_D1_reg => gpio_core_1_n_19, rst_reg(0) => AXI_LITE_IPIF_I_n_7, s_axi_aclk => s_axi_aclk ); \ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(24), Q => ip2bus_data_i_D1(24), R => bus2ip_reset ); \ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(25), Q => ip2bus_data_i_D1(25), R => bus2ip_reset ); \ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(26), Q => ip2bus_data_i_D1(26), R => bus2ip_reset ); \ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(27), Q => ip2bus_data_i_D1(27), R => bus2ip_reset ); \ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(28), Q => ip2bus_data_i_D1(28), R => bus2ip_reset ); \ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(29), Q => ip2bus_data_i_D1(29), R => bus2ip_reset ); \ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(30), Q => ip2bus_data_i_D1(30), R => bus2ip_reset ); \ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_data(31), Q => ip2bus_data_i_D1(31), R => bus2ip_reset ); ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => ip2bus_rdack_i, Q => ip2bus_rdack_i_D1, R => bus2ip_reset ); ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => gpio_core_1_n_19, Q => ip2bus_wrack_i_D1, R => bus2ip_reset ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_gpio_0_0,axi_gpio,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.2"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC; signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute C_ALL_INPUTS : integer; attribute C_ALL_INPUTS of U0 : label is 0; attribute C_ALL_INPUTS_2 : integer; attribute C_ALL_INPUTS_2 of U0 : label is 0; attribute C_ALL_OUTPUTS : integer; attribute C_ALL_OUTPUTS of U0 : label is 1; attribute C_ALL_OUTPUTS_2 : integer; attribute C_ALL_OUTPUTS_2 of U0 : label is 0; attribute C_DOUT_DEFAULT : integer; attribute C_DOUT_DEFAULT of U0 : label is 0; attribute C_DOUT_DEFAULT_2 : integer; attribute C_DOUT_DEFAULT_2 of U0 : label is 0; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_GPIO2_WIDTH : integer; attribute C_GPIO2_WIDTH of U0 : label is 32; attribute C_GPIO_WIDTH : integer; attribute C_GPIO_WIDTH of U0 : label is 8; attribute C_INTERRUPT_PRESENT : integer; attribute C_INTERRUPT_PRESENT of U0 : label is 0; attribute C_IS_DUAL : integer; attribute C_IS_DUAL of U0 : label is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; attribute C_TRI_DEFAULT : integer; attribute C_TRI_DEFAULT of U0 : label is -1; attribute C_TRI_DEFAULT_2 : integer; attribute C_TRI_DEFAULT_2 of U0 : label is -1; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; attribute ip_group : string; attribute ip_group of U0 : label is "LOGICORE"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio port map ( gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000", gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0), gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0), gpio_io_i(7 downto 0) => B"00000000", gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0), gpio_io_t(7 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(7 downto 0), ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED, s_axi_aclk => s_axi_aclk, s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;
library ieee; use ieee.std_logic_1164.all; -- Add your library and packages declaration here ... entity liaison_tb is end liaison_tb; architecture TB_ARCHITECTURE of liaison_tb is -- Component declaration of the tested unit component liaison port( clk : in STD_LOGIC; reset : in STD_LOGIC; di_ready : in STD_LOGIC; mp_data : in STD_LOGIC_VECTOR(3 downto 0); do_ready : out STD_LOGIC; voted_data : out STD_LOGIC ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal clk : STD_LOGIC; signal reset : STD_LOGIC; signal di_ready : STD_LOGIC; signal mp_data : STD_LOGIC_VECTOR(3 downto 0); -- Observed signals - signals mapped to the output ports of tested entity signal do_ready : STD_LOGIC; signal voted_data : STD_LOGIC; -- Add your code here ... begin stim_proc: process begin -- Setup and reset di_ready <= '0'; mp_data <= "1111"; reset <= '0'; wait for 10 ns; reset <= '1'; wait for 10 ns; reset <= '0'; wait for 10 ns; -- Test with alternating output and no errors di_ready <= '1'; mp_data <= "0000"; wait for 10 ns; di_ready <= '0'; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; -- Wait while data is transmited wait for 80 ns; -- Test with alternating output and a single errorous bit di_ready <= '1'; mp_data <= "0000"; wait for 10 ns; di_ready <= '0'; mp_data <= "1110"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; -- Wait while data is transmited wait for 80 ns; -- Test with alternating output and a single errorous bit di_ready <= '1'; mp_data <= "0000"; wait for 10 ns; di_ready <= '0'; mp_data <= "1110"; wait for 10 ns; mp_data <= "0010"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; -- Wait while data is transmited wait for 80 ns; -- Test with alternating output and a single errorous bit di_ready <= '1'; mp_data <= "0000"; wait for 10 ns; di_ready <= '0'; mp_data <= "1110"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "0111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; -- Wait while data is transmited wait for 80 ns; reset <= '1'; wait for 10 ns; reset <= '0'; -- Test with alternating output immediately di_ready <= '1'; mp_data <= "0000"; wait for 10 ns; di_ready <= '0'; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait for 10 ns; mp_data <= "0000"; wait for 10 ns; mp_data <= "1111"; wait; end process; -- Unit Under Test port map UUT : liaison port map ( clk => clk, reset => reset, di_ready => di_ready, mp_data => mp_data, do_ready => do_ready, voted_data => voted_data ); -- This drive the clock clk_process :process begin clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns; end process; end TB_ARCHITECTURE; configuration TESTBENCH_FOR_liaison of liaison_tb is for TB_ARCHITECTURE for UUT : liaison use entity work.liaison(liaison); end for; end for; end TESTBENCH_FOR_liaison;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block YaLsZ52y3ZVfENdu1oPuhyWXGqD1HgI88nJlN9D7xyw+SKSqu4D9pf5xVF9ZBDRb24+bz6tBuyRY xLUmvtpDwg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block oVXciUdE3RIuQWZVH8yTQTh12ttJ2gqH8r6cCR/6gsQjSK9Mr4H5tI300dIgQS9vO/tbyVnj+ZO9 zfje8hPR2U5BBgA5z7tBTGn8Q/I4juQ23ZFrPItTNQaJicqlSmrqvgIdSirjGZQFKoyVI5pfmSOu T06iVq395XOblsvHWCw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block YaLsZ52y3ZVfENdu1oPuhyWXGqD1HgI88nJlN9D7xyw+SKSqu4D9pf5xVF9ZBDRb24+bz6tBuyRY xLUmvtpDwg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block oVXciUdE3RIuQWZVH8yTQTh12ttJ2gqH8r6cCR/6gsQjSK9Mr4H5tI300dIgQS9vO/tbyVnj+ZO9 zfje8hPR2U5BBgA5z7tBTGn8Q/I4juQ23ZFrPItTNQaJicqlSmrqvgIdSirjGZQFKoyVI5pfmSOu T06iVq395XOblsvHWCw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block YaLsZ52y3ZVfENdu1oPuhyWXGqD1HgI88nJlN9D7xyw+SKSqu4D9pf5xVF9ZBDRb24+bz6tBuyRY xLUmvtpDwg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block oVXciUdE3RIuQWZVH8yTQTh12ttJ2gqH8r6cCR/6gsQjSK9Mr4H5tI300dIgQS9vO/tbyVnj+ZO9 zfje8hPR2U5BBgA5z7tBTGn8Q/I4juQ23ZFrPItTNQaJicqlSmrqvgIdSirjGZQFKoyVI5pfmSOu T06iVq395XOblsvHWCw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use work.component_pack.all; entity arbiter_out is port ( reset: in std_logic; clk: in std_logic; X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules credit: in std_logic_vector(1 downto 0); grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot) -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N, err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E, err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W, err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S, err_state_in_onehot, err_no_request_grants, err_request_IDLE_state, err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant, err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero : out std_logic ); end; architecture behavior of arbiter_out is ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 7 bits signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) ---------------------------------------- --TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); SIGNAL state, state_in : std_logic_vector (5 downto 0) := IDLE; -- : STATE_TYPE := IDLE; SIGNAL grant_Y_N_sig, grant_Y_E_sig, grant_Y_W_sig, grant_Y_S_sig, grant_Y_L_sig : std_logic; -- needed for connecting output ports -- of Arbiter_out to checker inputs -- Signal(s) used for creating the chain of injected fault locations -- Total: 17 bits ??!! -- Arbiter_out internal-related signals signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0); -- Arbiter_out output-related signals signal grant_Y_N_sig_faulty, grant_Y_E_sig_faulty, grant_Y_W_sig_faulty, grant_Y_S_sig_faulty, grant_Y_L_sig_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 17 bits -- for grant_Y_N, ... , grant_Y_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!! non_faulty_signals <= state & state_in & grant_Y_N_sig & grant_Y_E_sig & grant_Y_W_sig & grant_Y_S_sig & grant_Y_L_sig; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5) port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 17 bits state_faulty <= faulty_signals (16 downto 11); state_in_faulty <= faulty_signals (10 downto 5); grant_Y_N_sig_faulty <= faulty_signals (4); grant_Y_E_sig_faulty <= faulty_signals (3); grant_Y_W_sig_faulty <= faulty_signals (2); grant_Y_S_sig_faulty <= faulty_signals (1); grant_Y_L_sig_faulty <= faulty_signals (0); -- Total: 7 bits SR: shift_register_serial_in generic map(REG_WIDTH => 7) port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta ); ------------------------------------- ------------------------------------- -- We did this because of the checker outputs! grant_Y_N <= grant_Y_N_sig; grant_Y_E <= grant_Y_E_sig; grant_Y_W <= grant_Y_W_sig; grant_Y_S <= grant_Y_S_sig; grant_Y_L <= grant_Y_L_sig; -- Sequential part process (clk, reset)begin if reset = '0' then state <= IDLE; elsif clk'event and clk ='1' then state <= state_in; end if; end process; -- Arbiter_out checkers module instantiation ARBITER_OUT_ONE_HOT_CHECKERS: Arbiter_out_one_hot_pseudo_checkers port map ( credit => credit, req_X_N => X_N_Y, req_X_E => X_E_Y, req_X_W => X_W_Y, req_X_S => X_S_Y, req_X_L => X_L_Y, state => state_faulty, grant_Y_N => grant_Y_N_sig_faulty, grant_Y_E => grant_Y_E_sig_faulty, grant_Y_W => grant_Y_W_sig_faulty, grant_Y_S => grant_Y_S_sig_faulty, grant_Y_L => grant_Y_L_sig_faulty, state_in => state_in_faulty, -- Checker outputs err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => err_IDLE_req_X_N, err_North_req_X_N => err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => err_IDLE_req_X_E, err_North_req_X_E => err_North_req_X_E, err_East_req_X_W => err_East_req_X_W, err_West_req_X_S => err_West_req_X_S, err_South_req_X_L => err_South_req_X_L, err_Local_req_X_N => err_Local_req_X_N, err_IDLE_req_X_W => err_IDLE_req_X_W, err_North_req_X_W => err_North_req_X_W, err_East_req_X_S => err_East_req_X_S, err_West_req_X_L => err_West_req_X_L, err_South_req_X_N => err_South_req_X_N, err_Local_req_X_E => err_Local_req_X_E, err_IDLE_req_X_S => err_IDLE_req_X_S, err_North_req_X_S => err_North_req_X_S, err_East_req_X_L => err_East_req_X_L, err_West_req_X_N => err_West_req_X_N, err_South_req_X_E => err_South_req_X_E, err_Local_req_X_W => err_Local_req_X_W, err_IDLE_req_X_L => err_IDLE_req_X_L, err_North_req_X_L => err_North_req_X_L, err_East_req_X_N => err_East_req_X_N, err_West_req_X_E => err_West_req_X_E, err_South_req_X_W => err_South_req_X_W, err_Local_req_X_S => err_Local_req_X_S, err_state_in_onehot => err_state_in_onehot, err_no_request_grants => err_no_request_grants, err_request_IDLE_state => err_request_IDLE_state, err_request_IDLE_not_Grants => err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => err_Grants_onehot_or_all_zero ); -- anything below here is pure combinational process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin grant_Y_N_sig <= '0'; grant_Y_E_sig <= '0'; grant_Y_W_sig <= '0'; grant_Y_S_sig <= '0'; grant_Y_L_sig <= '0'; case state is when IDLE => if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when North => if credit /= "00" and X_N_Y = '1' then grant_Y_N_sig <= '1'; end if; if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when East => if credit /= "00" and X_E_Y = '1' then grant_Y_E_sig <= '1'; end if; if X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; else state_in <= IDLE; end if; when West => if credit /= "00" and X_W_Y = '1' then grant_Y_W_sig <= '1'; end if; if X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; else state_in <= IDLE; end if; when South => if credit /= "00" and X_S_Y = '1' then grant_Y_S_sig <= '1'; end if; if X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; else state_in <= IDLE; end if; when others => if credit /= "00" and X_L_Y = '1' then grant_Y_L_sig <= '1'; end if; if X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; else state_in <= IDLE; end if; end case; end process; end;
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use work.component_pack.all; entity arbiter_out is port ( reset: in std_logic; clk: in std_logic; X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules credit: in std_logic_vector(1 downto 0); grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot) -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N, err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E, err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W, err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S, err_state_in_onehot, err_no_request_grants, err_request_IDLE_state, err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant, err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero : out std_logic ); end; architecture behavior of arbiter_out is ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 7 bits signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) ---------------------------------------- --TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); SIGNAL state, state_in : std_logic_vector (5 downto 0) := IDLE; -- : STATE_TYPE := IDLE; SIGNAL grant_Y_N_sig, grant_Y_E_sig, grant_Y_W_sig, grant_Y_S_sig, grant_Y_L_sig : std_logic; -- needed for connecting output ports -- of Arbiter_out to checker inputs -- Signal(s) used for creating the chain of injected fault locations -- Total: 17 bits ??!! -- Arbiter_out internal-related signals signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0); -- Arbiter_out output-related signals signal grant_Y_N_sig_faulty, grant_Y_E_sig_faulty, grant_Y_W_sig_faulty, grant_Y_S_sig_faulty, grant_Y_L_sig_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 17 bits -- for grant_Y_N, ... , grant_Y_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!! non_faulty_signals <= state & state_in & grant_Y_N_sig & grant_Y_E_sig & grant_Y_W_sig & grant_Y_S_sig & grant_Y_L_sig; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5) port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 17 bits state_faulty <= faulty_signals (16 downto 11); state_in_faulty <= faulty_signals (10 downto 5); grant_Y_N_sig_faulty <= faulty_signals (4); grant_Y_E_sig_faulty <= faulty_signals (3); grant_Y_W_sig_faulty <= faulty_signals (2); grant_Y_S_sig_faulty <= faulty_signals (1); grant_Y_L_sig_faulty <= faulty_signals (0); -- Total: 7 bits SR: shift_register_serial_in generic map(REG_WIDTH => 7) port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta ); ------------------------------------- ------------------------------------- -- We did this because of the checker outputs! grant_Y_N <= grant_Y_N_sig; grant_Y_E <= grant_Y_E_sig; grant_Y_W <= grant_Y_W_sig; grant_Y_S <= grant_Y_S_sig; grant_Y_L <= grant_Y_L_sig; -- Sequential part process (clk, reset)begin if reset = '0' then state <= IDLE; elsif clk'event and clk ='1' then state <= state_in; end if; end process; -- Arbiter_out checkers module instantiation ARBITER_OUT_ONE_HOT_CHECKERS: Arbiter_out_one_hot_pseudo_checkers port map ( credit => credit, req_X_N => X_N_Y, req_X_E => X_E_Y, req_X_W => X_W_Y, req_X_S => X_S_Y, req_X_L => X_L_Y, state => state_faulty, grant_Y_N => grant_Y_N_sig_faulty, grant_Y_E => grant_Y_E_sig_faulty, grant_Y_W => grant_Y_W_sig_faulty, grant_Y_S => grant_Y_S_sig_faulty, grant_Y_L => grant_Y_L_sig_faulty, state_in => state_in_faulty, -- Checker outputs err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => err_IDLE_req_X_N, err_North_req_X_N => err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => err_IDLE_req_X_E, err_North_req_X_E => err_North_req_X_E, err_East_req_X_W => err_East_req_X_W, err_West_req_X_S => err_West_req_X_S, err_South_req_X_L => err_South_req_X_L, err_Local_req_X_N => err_Local_req_X_N, err_IDLE_req_X_W => err_IDLE_req_X_W, err_North_req_X_W => err_North_req_X_W, err_East_req_X_S => err_East_req_X_S, err_West_req_X_L => err_West_req_X_L, err_South_req_X_N => err_South_req_X_N, err_Local_req_X_E => err_Local_req_X_E, err_IDLE_req_X_S => err_IDLE_req_X_S, err_North_req_X_S => err_North_req_X_S, err_East_req_X_L => err_East_req_X_L, err_West_req_X_N => err_West_req_X_N, err_South_req_X_E => err_South_req_X_E, err_Local_req_X_W => err_Local_req_X_W, err_IDLE_req_X_L => err_IDLE_req_X_L, err_North_req_X_L => err_North_req_X_L, err_East_req_X_N => err_East_req_X_N, err_West_req_X_E => err_West_req_X_E, err_South_req_X_W => err_South_req_X_W, err_Local_req_X_S => err_Local_req_X_S, err_state_in_onehot => err_state_in_onehot, err_no_request_grants => err_no_request_grants, err_request_IDLE_state => err_request_IDLE_state, err_request_IDLE_not_Grants => err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => err_Grants_onehot_or_all_zero ); -- anything below here is pure combinational process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin grant_Y_N_sig <= '0'; grant_Y_E_sig <= '0'; grant_Y_W_sig <= '0'; grant_Y_S_sig <= '0'; grant_Y_L_sig <= '0'; case state is when IDLE => if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when North => if credit /= "00" and X_N_Y = '1' then grant_Y_N_sig <= '1'; end if; if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when East => if credit /= "00" and X_E_Y = '1' then grant_Y_E_sig <= '1'; end if; if X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; else state_in <= IDLE; end if; when West => if credit /= "00" and X_W_Y = '1' then grant_Y_W_sig <= '1'; end if; if X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; else state_in <= IDLE; end if; when South => if credit /= "00" and X_S_Y = '1' then grant_Y_S_sig <= '1'; end if; if X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; else state_in <= IDLE; end if; when others => if credit /= "00" and X_L_Y = '1' then grant_Y_L_sig <= '1'; end if; if X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; else state_in <= IDLE; end if; end case; end process; end;
--Copyright (C) 2016 Siavoosh Payandeh Azad library ieee; use ieee.std_logic_1164.all; use work.component_pack.all; entity arbiter_out is port ( reset: in std_logic; clk: in std_logic; X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y :in std_logic; -- From LBDR modules credit: in std_logic_vector(1 downto 0); grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : out std_logic; -- Grants given to LBDR requests (encoded as one-hot) -- fault injector shift register with serial input signals TCK: in std_logic; SE: in std_logic; -- shift enable UE: in std_logic; -- update enable SI: in std_logic; -- serial Input SO: out std_logic; -- serial output -- Checker outputs err_Requests_state_in_state_not_equal, err_IDLE_req_X_N, err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E, err_North_req_X_E, err_East_req_X_W, err_West_req_X_S, err_South_req_X_L, err_Local_req_X_N, err_IDLE_req_X_W, err_North_req_X_W, err_East_req_X_S, err_West_req_X_L, err_South_req_X_N, err_Local_req_X_E, err_IDLE_req_X_S, err_North_req_X_S, err_East_req_X_L, err_West_req_X_N, err_South_req_X_E, err_Local_req_X_W, err_IDLE_req_X_L, err_North_req_X_L, err_East_req_X_N, err_West_req_X_E, err_South_req_X_W, err_Local_req_X_S, err_state_in_onehot, err_no_request_grants, err_request_IDLE_state, err_request_IDLE_not_Grants, err_state_North_Invalid_Grant, err_state_East_Invalid_Grant, err_state_West_Invalid_Grant, err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero : out std_logic ); end; architecture behavior of arbiter_out is ---------------------------------------- -- Signals related to fault injection -- ---------------------------------------- -- Total: 7 bits signal FI_add_sta: std_logic_vector (6 downto 0); -- 5 bits for fault injection location address (ceil of log2(17) = 5) -- 2 bits for type of fault (SA0 or SA1) signal non_faulty_signals: std_logic_vector (16 downto 0); -- 17 bits for internal- and output-related signals (non-faulty) signal faulty_signals: std_logic_vector(16 downto 0); -- 17 bits for internal- and output-related signals (with single stuck-at fault injected in one of them) ---------------------------------------- --TYPE STATE_TYPE IS (IDLE, North, East, West, South, Local); SIGNAL state, state_in : std_logic_vector (5 downto 0) := IDLE; -- : STATE_TYPE := IDLE; SIGNAL grant_Y_N_sig, grant_Y_E_sig, grant_Y_W_sig, grant_Y_S_sig, grant_Y_L_sig : std_logic; -- needed for connecting output ports -- of Arbiter_out to checker inputs -- Signal(s) used for creating the chain of injected fault locations -- Total: 17 bits ??!! -- Arbiter_out internal-related signals signal state_faulty, state_in_faulty: std_logic_vector(5 downto 0); -- Arbiter_out output-related signals signal grant_Y_N_sig_faulty, grant_Y_E_sig_faulty, grant_Y_W_sig_faulty, grant_Y_S_sig_faulty, grant_Y_L_sig_faulty: std_logic; begin ------------------------------------- ---- Related to fault injection ----- ------------------------------------- -- Total: 17 bits -- for grant_Y_N, ... , grant_Y_L output signals, not sure whether to include them or the signals with _sig suffix in their names ??!! non_faulty_signals <= state & state_in & grant_Y_N_sig & grant_Y_E_sig & grant_Y_W_sig & grant_Y_S_sig & grant_Y_L_sig; -- Fault injector module instantiation FI: fault_injector generic map(DATA_WIDTH => 17, ADDRESS_WIDTH => 5) port map (data_in=> non_faulty_signals , address => FI_add_sta(6 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals ); -- Extracting faulty values for internal- and output-related signals -- Total: 17 bits state_faulty <= faulty_signals (16 downto 11); state_in_faulty <= faulty_signals (10 downto 5); grant_Y_N_sig_faulty <= faulty_signals (4); grant_Y_E_sig_faulty <= faulty_signals (3); grant_Y_W_sig_faulty <= faulty_signals (2); grant_Y_S_sig_faulty <= faulty_signals (1); grant_Y_L_sig_faulty <= faulty_signals (0); -- Total: 7 bits SR: shift_register_serial_in generic map(REG_WIDTH => 7) port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta ); ------------------------------------- ------------------------------------- -- We did this because of the checker outputs! grant_Y_N <= grant_Y_N_sig; grant_Y_E <= grant_Y_E_sig; grant_Y_W <= grant_Y_W_sig; grant_Y_S <= grant_Y_S_sig; grant_Y_L <= grant_Y_L_sig; -- Sequential part process (clk, reset)begin if reset = '0' then state <= IDLE; elsif clk'event and clk ='1' then state <= state_in; end if; end process; -- Arbiter_out checkers module instantiation ARBITER_OUT_ONE_HOT_CHECKERS: Arbiter_out_one_hot_pseudo_checkers port map ( credit => credit, req_X_N => X_N_Y, req_X_E => X_E_Y, req_X_W => X_W_Y, req_X_S => X_S_Y, req_X_L => X_L_Y, state => state_faulty, grant_Y_N => grant_Y_N_sig_faulty, grant_Y_E => grant_Y_E_sig_faulty, grant_Y_W => grant_Y_W_sig_faulty, grant_Y_S => grant_Y_S_sig_faulty, grant_Y_L => grant_Y_L_sig_faulty, state_in => state_in_faulty, -- Checker outputs err_Requests_state_in_state_not_equal => err_Requests_state_in_state_not_equal, err_IDLE_req_X_N => err_IDLE_req_X_N, err_North_req_X_N => err_North_req_X_N, err_North_credit_not_zero_req_X_N_grant_N => err_North_credit_not_zero_req_X_N_grant_N, err_North_credit_zero_or_not_req_X_N_not_grant_N => err_North_credit_zero_or_not_req_X_N_not_grant_N, err_East_req_X_E => err_East_req_X_E, err_East_credit_not_zero_req_X_E_grant_E => err_East_credit_not_zero_req_X_E_grant_E, err_East_credit_zero_or_not_req_X_E_not_grant_E => err_East_credit_zero_or_not_req_X_E_not_grant_E, err_West_req_X_W => err_West_req_X_W, err_West_credit_not_zero_req_X_W_grant_W => err_West_credit_not_zero_req_X_W_grant_W, err_West_credit_zero_or_not_req_X_W_not_grant_W => err_West_credit_zero_or_not_req_X_W_not_grant_W, err_South_req_X_S => err_South_req_X_S, err_South_credit_not_zero_req_X_S_grant_S => err_South_credit_not_zero_req_X_S_grant_S, err_South_credit_zero_or_not_req_X_S_not_grant_S => err_South_credit_zero_or_not_req_X_S_not_grant_S, err_Local_req_X_L => err_Local_req_X_L, err_Local_credit_not_zero_req_X_L_grant_L => err_Local_credit_not_zero_req_X_L_grant_L, err_Local_credit_zero_or_not_req_X_L_not_grant_L => err_Local_credit_zero_or_not_req_X_L_not_grant_L, err_IDLE_req_X_E => err_IDLE_req_X_E, err_North_req_X_E => err_North_req_X_E, err_East_req_X_W => err_East_req_X_W, err_West_req_X_S => err_West_req_X_S, err_South_req_X_L => err_South_req_X_L, err_Local_req_X_N => err_Local_req_X_N, err_IDLE_req_X_W => err_IDLE_req_X_W, err_North_req_X_W => err_North_req_X_W, err_East_req_X_S => err_East_req_X_S, err_West_req_X_L => err_West_req_X_L, err_South_req_X_N => err_South_req_X_N, err_Local_req_X_E => err_Local_req_X_E, err_IDLE_req_X_S => err_IDLE_req_X_S, err_North_req_X_S => err_North_req_X_S, err_East_req_X_L => err_East_req_X_L, err_West_req_X_N => err_West_req_X_N, err_South_req_X_E => err_South_req_X_E, err_Local_req_X_W => err_Local_req_X_W, err_IDLE_req_X_L => err_IDLE_req_X_L, err_North_req_X_L => err_North_req_X_L, err_East_req_X_N => err_East_req_X_N, err_West_req_X_E => err_West_req_X_E, err_South_req_X_W => err_South_req_X_W, err_Local_req_X_S => err_Local_req_X_S, err_state_in_onehot => err_state_in_onehot, err_no_request_grants => err_no_request_grants, err_request_IDLE_state => err_request_IDLE_state, err_request_IDLE_not_Grants => err_request_IDLE_not_Grants, err_state_North_Invalid_Grant => err_state_North_Invalid_Grant, err_state_East_Invalid_Grant => err_state_East_Invalid_Grant, err_state_West_Invalid_Grant => err_state_West_Invalid_Grant, err_state_South_Invalid_Grant => err_state_South_Invalid_Grant, err_state_Local_Invalid_Grant => err_state_Local_Invalid_Grant, err_Grants_onehot_or_all_zero => err_Grants_onehot_or_all_zero ); -- anything below here is pure combinational process(state, X_N_Y, X_E_Y, X_W_Y, X_S_Y, X_L_Y, credit) begin grant_Y_N_sig <= '0'; grant_Y_E_sig <= '0'; grant_Y_W_sig <= '0'; grant_Y_S_sig <= '0'; grant_Y_L_sig <= '0'; case state is when IDLE => if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when North => if credit /= "00" and X_N_Y = '1' then grant_Y_N_sig <= '1'; end if; if X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; else state_in <= IDLE; end if; when East => if credit /= "00" and X_E_Y = '1' then grant_Y_E_sig <= '1'; end if; if X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; else state_in <= IDLE; end if; when West => if credit /= "00" and X_W_Y = '1' then grant_Y_W_sig <= '1'; end if; if X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; else state_in <= IDLE; end if; when South => if credit /= "00" and X_S_Y = '1' then grant_Y_S_sig <= '1'; end if; if X_S_Y = '1' then state_in <= South; elsif X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; else state_in <= IDLE; end if; when others => if credit /= "00" and X_L_Y = '1' then grant_Y_L_sig <= '1'; end if; if X_L_Y = '1' then state_in <= Local; elsif X_N_Y ='1' then state_in <= North; elsif X_E_Y = '1' then state_in <= East; elsif X_W_Y = '1' then state_in <= West; elsif X_S_Y = '1' then state_in <= South; else state_in <= IDLE; end if; end case; end process; end;
---------------------------------------------------------------------------------- -- Company: NTU ATHENS - BNL -- Engineer: Paris Moschovakos -- -- Copyright Notice/Copying Permission: -- Copyright 2017 Paris Moschovakos -- -- This file is part of NTUA-BNL_VMM_firmware. -- -- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>. -- -- Create Date: 25.06.2016 -- Design Name: -- Module Name: packet_formation.vhd - Behavioral -- Project Name: MMFE8 -- Target Devices: Artix7 xc7a200t-2fbg484 and xc7a200t-3fbg484 -- Tool Versions: Vivado 2017.1 -- -- Changelog: -- 22.08.2016 Changed readout trigger pulse from 125 to 100 ns long (Reid Pinkham) -- 09.09.2016 Added two signals for ETR interconnection (Christos Bakalis) -- 26.02.2016 Moved to a global clock domain @125MHz (Paris) -- 06.04.2017 Hard setting latency to 300ns as configurable latency was moved to trigger module (Paris) -- 25.04.2017 Added vmm_driver module. (Christos Bakalis) -- 06.06.2017 Added ART header a handling (Paris) -- ---------------------------------------------------------------------------------- library IEEE; library UNISIM; use IEEE.STD_LOGIC_1164.ALL; use IEEE.std_logic_unsigned.all; use IEEE.NUMERIC_STD.ALL; use UNISIM.VComponents.all; entity packet_formation is Generic(is_mmfe8 : std_logic; vmmReadoutMode : std_logic; artEnabled : std_logic); Port( clk : in std_logic; newCycle : in std_logic; trigVmmRo : out std_logic; vmmId : out std_logic_vector(2 downto 0); vmmWord : in std_logic_vector(15 downto 0); vmmWordReady : in std_logic; vmmEventDone : in std_logic; UDPDone : in std_logic; pfBusy : out std_logic; -- Control signal to ETR glBCID : in std_logic_vector(11 downto 0); -- glBCID counter from ETR packLen : out std_logic_vector(11 downto 0); dataout : out std_logic_vector(15 downto 0); wrenable : out std_logic; end_packet : out std_logic; rd_ena_buff : out std_logic; rst_l0 : out std_logic; tr_hold : out std_logic; reset : in std_logic; rst_vmm : out std_logic; linkHealth_bmsk : in std_logic_vector(8 downto 1); rst_FIFO : out std_logic; latency : in std_logic_vector(15 downto 0); dbg_st_o : out std_logic_vector(4 downto 0); trraw_synced125 : in std_logic; vmmArtData125 : in std_logic_vector(5 downto 0); vmmArtReady : in std_logic ); end packet_formation; architecture Behavioral of packet_formation is signal artHeader : std_logic_vector(15 downto 0) := ( others => '0' ); signal header : std_logic_vector(63 downto 0) := ( others => '0' ); signal header_l0 : std_logic_vector(47 downto 0) := ( others => '0' ); signal vmmId_i : std_logic_vector(2 downto 0) := b"000"; signal globBcid : std_logic_vector(15 downto 0) := x"FFFF"; --( others => '0' ); signal precCnt : std_logic_vector(7 downto 0) := x"00"; --( others => '0' ); signal globBcid_i : std_logic_vector(15 downto 0); signal globBCID_etr : std_logic_vector(11 downto 0) := (others => '0'); --globBCID counter as it is coming from ETR signal eventCounter_i : unsigned(31 downto 0) := to_unsigned(0, 32); signal wait_Cnt : integer range 0 to 31 := 0; signal vmmId_cnt : integer range 0 to 7 := 0; signal trigLatencyCnt : integer := 0; signal trigLatency : integer := 140; -- 700ns (140x5ns) signal pfBusy_i : std_logic := '0'; -- control signal to be sent to ETR signal daqFIFO_wr_en_hdr : std_logic := '0'; signal daqFIFO_wr_en_drv : std_logic := '0'; signal sel_wrenable : std_logic := '0'; signal drv_enable : std_logic := '0'; signal drv_done : std_logic := '0'; signal daqFIFO_din : std_logic_vector(15 downto 0) := ( others => '0' ); signal triggerVmmReadout_i : std_logic := '0'; signal selectDataInput : std_logic_vector(2 downto 0) := (others => '0'); signal sel_cnt : unsigned(2 downto 0) := (others => '0'); signal vmmWord_i : std_logic_vector(15 downto 0) := ( others => '0' ); signal packLen_i : unsigned(11 downto 0) := x"000"; signal packLen_drv2pf_unsg : unsigned(11 downto 0) := x"000"; signal packLen_drv2pf : std_logic_vector(11 downto 0) := x"000"; signal packLen_cnt : unsigned(11 downto 0) := x"000"; signal end_packet_int : std_logic := '0'; signal artValid : std_logic := '0'; signal trraw_synced125_prev : std_logic := '0'; signal clearValid : std_logic := '0'; type stateType is (waitingForNewCycle, increaseCounter, waitForLatency, captureEventID, setEventID, sendHeaderStep1, sendHeaderStep2, sendHeaderStep3, triggerVmmReadout, waitForData, sendVmmDataStep1, sendVmmDataStep2, formTrailer, sendTrailer, packetDone, isUDPDone, isTriggerOff, S2, eventDone); signal state : stateType; -------------------- Debugging ------------------------------ signal probe0_out : std_logic_vector(132 downto 0); signal probe1_out : std_logic_vector(200 downto 0); signal debug_state : std_logic_vector(4 downto 0); ----------------------------------------------------------------- ---------------------- Debugging ------------------------------ -- attribute mark_debug : string; -- attribute mark_debug of header : signal is "true"; -- attribute mark_debug of globBcid : signal is "true"; -- attribute mark_debug of globBcid_i : signal is "true"; -- attribute mark_debug of precCnt : signal is "true"; -- attribute mark_debug of vmmId_i : signal is "true"; -- attribute mark_debug of daqFIFO_din : signal is "true"; -- attribute mark_debug of vmmWord_i : signal is "true"; -- attribute mark_debug of packLen_i : signal is "true"; -- attribute mark_debug of packLen_cnt : signal is "true"; -- attribute mark_debug of end_packet_int : signal is "true"; -- attribute mark_debug of triggerVmmReadout_i : signal is "true"; -- attribute mark_debug of debug_state : signal is "true"; -- attribute mark_debug of artValid : signal is "true"; -- attribute mark_debug of trraw_synced125 : signal is "true"; -- attribute mark_debug of vmmArtReady : signal is "true"; component ila_pf port ( clk : in std_logic; probe0 : in std_logic_vector(132 downto 0); probe1 : in std_logic_vector(200 downto 0) ); end component; component vio_0 port ( clk : in std_logic; probe_out0 : out std_logic_vector ( 11 downto 0 ) ); end component; component vmm_driver port( ------------------------------------ ------ General/PF Interface -------- clk : in std_logic; drv_enable : in std_logic; drv_done : out std_logic; pack_len_drv : out std_logic_vector(11 downto 0); ------------------------------------ ----- VMM_RO/FIFO2UDP Interface ---- wr_en_fifo2udp : out std_logic; rd_en_buff : out std_logic; vmmWordReady : in std_logic ); end component; ----------------------------------------------------------------- begin packetCaptureProc: process(clk, newCycle, vmmEventDone, vmmWordReady, wait_Cnt, UDPDone) begin if rising_edge(clk) then if reset = '1' then debug_state <= "11111"; eventCounter_i <= to_unsigned(0, 32); tr_hold <= '0'; pfBusy_i <= '0'; triggerVmmReadout_i <= '0'; rst_l0 <= '1'; sel_wrenable <= '0'; rst_FIFO <= '1'; daqFIFO_wr_en_hdr <= '0'; packLen_cnt <= x"000"; wait_Cnt <= 0; sel_cnt <= (others => '0'); drv_enable <= '0'; triggerVmmReadout_i <= '0'; end_packet_int <= '0'; state <= waitingForNewCycle; else case state is when waitingForNewCycle => debug_state <= "00000"; pfBusy_i <= '0'; triggerVmmReadout_i <= '0'; rst_l0 <= '0'; sel_wrenable <= '0'; drv_enable <= '0'; trigLatencyCnt <= 0; sel_cnt <= (others => '0'); rst_FIFO <= '0'; if newCycle = '1' then pfBusy_i <= '1'; state <= increaseCounter; end if; when increaseCounter => debug_state <= "00001"; eventCounter_i <= eventCounter_i + 1; state <= waitForLatency; when waitForLatency => debug_state <= "00010"; tr_hold <= '1'; -- Prevent new triggers if(trigLatencyCnt > trigLatency and is_mmfe8 = '1')then state <= S2; elsif(trigLatencyCnt > trigLatency and is_mmfe8 = '0')then state <= captureEventID; else trigLatencyCnt <= trigLatencyCnt + 1; end if; when S2 => -- wait for the header elements to be formed debug_state <= "00010"; -- --tr_hold <= '1'; -- Prevent new triggers packLen_cnt <= x"000"; -- Reset length count sel_wrenable <= '0'; vmmId_i <= std_logic_vector(to_unsigned(vmmId_cnt, 3)); state <= captureEventID; when captureEventID => -- Form Header debug_state <= "00011"; packLen_cnt <= x"000"; state <= setEventID; when setEventID => debug_state <= "00100"; rst_FIFO <= '0'; daqFIFO_wr_en_hdr <= '0'; if(wait_Cnt < 3)then wait_Cnt <= wait_Cnt + 1; state <= setEventID; else wait_Cnt <= 0; state <= sendHeaderStep1; end if; when sendHeaderStep1 => debug_state <= "00101"; daqFIFO_wr_en_hdr <= '1'; packLen_cnt <= packLen_cnt + 1; state <= sendHeaderStep2; when sendHeaderStep2 => debug_state <= "00110"; daqFIFO_wr_en_hdr <= '0'; if(wait_Cnt < 3)then wait_Cnt <= wait_Cnt + 1; state <= sendHeaderStep2; else wait_Cnt <= 0; state <= sendHeaderStep3; end if; when sendHeaderStep3 => if(sel_cnt < 5 and vmmReadoutMode = '0')then -- incr the counter to select the other parts of the header sel_cnt <= sel_cnt + 1; state <= setEventID; elsif(sel_cnt < 4 and vmmReadoutMode = '1')then sel_cnt <= sel_cnt + 1; state <= setEventID; else -- the whole header has been sent state <= triggerVmmReadout; end if; when triggerVmmReadout => -- Creates an 136ns pulse to trigger the readout if not at level0 mode debug_state <= "00111"; sel_cnt <= "110"; -- fix the counter to 4 to select the VMM data for the next steps sel_wrenable <= '1'; -- grant control to driver if wait_Cnt < 30 and vmmReadoutMode = '0' then wait_Cnt <= wait_Cnt + 1; triggerVmmReadout_i <= '1'; else triggerVmmReadout_i <= '0'; wait_Cnt <= 0; state <= waitForData; end if; when waitForData => debug_state <= "01000"; if (vmmWordReady = '1') then state <= sendVmmDataStep1; elsif (vmmEventDone = '1') then state <= sendTrailer; end if; when sendVmmDataStep1 => debug_state <= "01001"; drv_enable <= '1'; state <= sendVmmDataStep2; when sendVmmDataStep2 => debug_state <= "01010"; if(drv_done = '1')then state <= formTrailer; else state <= sendVmmDataStep2; end if; when formTrailer => debug_state <= "01011"; if (vmmEventDone = '1') then state <= sendTrailer; elsif (vmmEventDone = '0' and vmmWordReady = '0') then state <= waitForData; else -- (vmmWordReady = '1') then state <= formTrailer; end if; when sendTrailer => debug_state <= "01100"; packLen_i <= packLen_cnt + packLen_drv2pf_unsg; state <= packetDone; when packetDone => debug_state <= "01101"; end_packet_int <= '1'; if(is_mmfe8 = '1')then state <= eventDone; else state <= isUDPDone; end if; when eventDone => debug_state <= "01110"; end_packet_int <= '0'; drv_enable <= '0'; if vmmId_cnt = 7 then vmmId_cnt <= 0; state <= isUDPDone; else vmmId_cnt <= vmmId_cnt + 1; sel_cnt <= "000"; sel_wrenable <= '0'; state <= S2; end if; -- when resetVMMs => -- debug_state <= "01111"; -- rst_vmm <= '1'; -- state <= resetDone; -- when resetDone => -- debug_state <= "10000"; -- if resetting = '0' then -- rst_vmm <= '0'; -- state <= isUDPDone; -- rst_vmm <= '0'; -- Prevent from continuously resetting while waiting for UDP Packet -- end if; when isUDPDone => debug_state <= "01110"; drv_enable <= '0'; end_packet_int <= '0'; rst_l0 <= '1'; -- reset the level0 buffers and the interface with packet_formation -- pfBusy_i <= '0'; if (UDPDone = '1') then -- Wait for the UDP packet to be sent state <= isTriggerOff; end if; when isTriggerOff => -- Wait for whatever ongoing trigger pulse to go to 0 debug_state <= "01111"; if trraw_synced125 /= '1' then tr_hold <= '0'; -- Allow new triggers state <= waitingForNewCycle; end if; when others => tr_hold <= '0'; state <= waitingForNewCycle; end case; end if; end if; end process; muxFIFOData: process( sel_cnt, header, header_l0, vmmWord, vmmArtData125 ) begin case sel_cnt is when "000" => daqFIFO_din <= b"1111000" & artValid & "01" & vmmArtData125(0) & vmmArtData125(1) & vmmArtData125(2) & vmmArtData125(3) & vmmArtData125(4) & vmmArtData125(5); when "001" => daqFIFO_din <= b"0000000" & artValid & "00" & vmmArtData125(0) & vmmArtData125(1) & vmmArtData125(2) & vmmArtData125(3) & vmmArtData125(4) & vmmArtData125(5); when "010" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(63 downto 48); else daqFIFO_din <= header_l0(47 downto 32); end if; when "011" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(47 downto 32); else daqFIFO_din <= header_l0(31 downto 16); end if; when "100" => if (vmmReadoutMode = '0') then daqFIFO_din <= header(31 downto 16); else daqFIFO_din <= header_l0(15 downto 0); end if; when "101" => daqFIFO_din <= header(15 downto 0); when "110" => daqFIFO_din <= vmmWord; when others => daqFIFO_din <= (others => '0'); end case; end process; muxWrEn: process( sel_wrenable, daqFIFO_wr_en_hdr, daqFIFO_wr_en_drv ) begin case sel_wrenable is when '0' => wrenable <= daqFIFO_wr_en_hdr; when '1' => wrenable <= daqFIFO_wr_en_drv; when others => wrenable <= '0'; end case; end process; vmm_driver_inst: vmm_driver port map( ------------------------------------ ------ General/PF Interface -------- clk => clk, drv_enable => drv_enable, drv_done => drv_done, pack_len_drv => packLen_drv2pf, ------------------------------------ ----- VMM_RO/FIFO2UDP Interface ---- wr_en_fifo2udp => daqFIFO_wr_en_drv, rd_en_buff => rd_ena_buff, vmmWordReady => vmmWordReady ); triggerEdgeDetection: process(clk) --125 begin if rising_edge(clk) then if trraw_synced125_prev = '0' and trraw_synced125 = '1' then clearValid <= '1'; trraw_synced125_prev <= trraw_synced125; else clearValid <= '0'; trraw_synced125_prev <= trraw_synced125; end if; end if; end process; LDCE_inst : LDCE generic map ( INIT => '0') port map ( Q => artValid, CLR => clearValid, D => '1', G => vmmArtReady, GE => artEnabled ); globBcid_i <= globBcid; vmmWord_i <= vmmWord; dataout <= daqFIFO_din; packLen <= std_logic_vector(packLen_i); end_packet <= end_packet_int; trigVmmRo <= triggerVmmReadout_i; vmmId <= vmmId_i; trigLatency <= 37 + to_integer(unsigned(latency)); --(hard set to 300ns )--to_integer(unsigned(latency)); pfBusy <= pfBusy_i; globBCID_etr <= glBCID; artHeader <= b"0000000000" & vmmArtData125; -- header of level 0 has three 16-bit words from FPGA + one 16-bit word from VMM header_l0(47 downto 16) <= std_logic_vector(eventCounter_i); header_l0(15 downto 0) <= b"00000" & vmmId_i & linkHealth_bmsk; -- 5 & 3 & 8 ; header(63 downto 32) <= std_logic_vector(eventCounter_i); header(31 downto 0) <= precCnt & globBcid & b"00000" & vmmId_i; -- 8 & 16 & 5 & 3 dbg_st_o <= debug_state; packLen_drv2pf_unsg <= unsigned(packLen_drv2pf); --ilaPacketFormation: ila_pf --port map( -- clk => clk, -- probe0 => probe0_out, -- probe1 => probe1_out --); probe0_out(9 downto 0) <= std_logic_vector(to_unsigned(trigLatencyCnt, 10)); probe0_out(19 downto 10) <= std_logic_vector(to_unsigned(trigLatency, 10)); probe0_out(20) <= '0'; probe0_out(21) <= artValid; probe0_out(22) <= trraw_synced125; probe0_out(23) <= vmmArtReady; probe0_out(29 downto 24) <= vmmArtData125; probe0_out(132 downto 30) <= (others => '0');--vmmId_i; probe1_out(63 downto 0) <= (others => '0');--daqFIFO_din; probe1_out(64) <= vmmWordReady; probe1_out(65) <= vmmEventDone; probe1_out(66) <= '0'; probe1_out(67) <= newCycle; probe1_out(79 downto 68) <= std_logic_vector(packLen_i); probe1_out(91 downto 80) <= std_logic_vector(packLen_cnt); probe1_out(92) <= end_packet_int; probe1_out(93) <= triggerVmmReadout_i; probe1_out(109 downto 94) <= latency; probe1_out(110) <= '0'; probe1_out(142 downto 111) <= std_logic_vector(eventCounter_i); probe1_out(147 downto 143) <= debug_state; probe1_out(200 downto 148) <= (others => '0'); end Behavioral;
------------------------------------------------------------------------------- -- iic_pkg.vhd - Package ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2009 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** ------------------------------------------------------------------------------- -- Filename: iic_pkg.vhd -- Version: v1.01.b -- Description: This file contains the constants used in the design of the -- iic bus interface. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_iic.vhd -- -- iic.vhd -- -- axi_ipif_ssp1.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- soft_reset.vhd -- -- reg_interface.vhd -- -- filter.vhd -- -- debounce.vhd -- -- iic_control.vhd -- -- upcnt_n.vhd -- -- shift8.vhd -- -- dynamic_master.vhd -- -- iic_pkg.vhd -- ------------------------------------------------------------------------------- -- Author: USM -- -- USM 10/15/09 -- ^^^^^^ -- - Initial release of v1.00.a -- ~~~~~~ -- -- USM 09/06/10 -- ^^^^^^ -- - Release of v1.01.a -- ~~~~~~ -- -- NLR 01/07/11 -- ^^^^^^ -- - Release of v1.01.b -- ~~~~~~ -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package iic_pkg is ---------------------------------------------------------------------------- -- Constant Declarations ---------------------------------------------------------------------------- constant RESET_ACTIVE : std_logic := '1'; -- Reset Constant constant NUM_IIC_REGS : integer := 11; -- should be same as C_NUM_IIC_REGS in axi_iic top constant DATA_BITS : natural := 8; -- FIFO Width Generic constant TX_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits constant RC_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits --IPIF Generics that must remain at these values for the IIC constant INCLUDE_DEV_PENCODER : BOOLEAN := False; constant IPIF_ABUS_WIDTH : INTEGER := 32; constant INCLUDE_DEV_ISC : Boolean := false; type STD_LOGIC_VECTOR_ARRAY is array (0 to NUM_IIC_REGS-1) of std_logic_vector(24 to 31); type INTEGER_ARRAY is array (24 to 31) of integer; ---------------------------------------------------------------------------- -- Function and Procedure Declarations ---------------------------------------------------------------------------- function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer; C_IIC_FREQ : integer) return integer; function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector; function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector; function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY) return INTEGER_ARRAY; end package iic_pkg; ------------------------------------------------------------------------------- -- Package body ------------------------------------------------------------------------------- package body iic_pkg is ---------------------------------------------------------------------------- -- Function Definitions ---------------------------------------------------------------------------- -- Function num_ctr_bits -- -- This function returns the number of bits required to count 1/2 the period -- of the SCL clock. -- ---------------------------------------------------------------------------- function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer; C_IIC_FREQ : integer) return integer is variable num_bits : integer :=0; variable i : integer :=0; begin -- for loop used because XST service pack 2 does not support While loops if C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ > C_S_AXI_ACLK_FREQ_HZ/212766 then for i in 0 to 30 loop -- 30 is a magic number needed for for loops if 2**i < C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ then num_bits := num_bits + 1; end if; end loop; return (num_bits); else for i in 0 to 30 loop if 2**i < C_S_AXI_ACLK_FREQ_HZ/212766 then num_bits := num_bits + 1; end if; end loop; return (num_bits); end if; end function num_ctr_bits; ---------------------------------------------------------------------------- -- Function ten_bit_addr_used -- -- This function returns either b"00000000" for no ten bit addressing or -- b"00000111" for ten bit addressing -- ---------------------------------------------------------------------------- function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector is begin if C_TEN_BIT_ADR = 0 then return (b"00000000"); else return (b"00000111"); end if; end function ten_bit_addr_used; ---------------------------------------------------------------------------- -- Function gpo_bit_used -- -- This function returns b"00000000" up to b"11111111" depending on -- C_GPO_WIDTH -- ---------------------------------------------------------------------------- function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector is begin if C_GPO_WIDTH = 1 then return (b"00000001"); elsif C_GPO_WIDTH = 2 then return (b"00000011"); elsif C_GPO_WIDTH = 3 then return (b"00000111"); elsif C_GPO_WIDTH = 4 then return (b"00001111"); elsif C_GPO_WIDTH = 5 then return (b"00011111"); elsif C_GPO_WIDTH = 6 then return (b"00111111"); elsif C_GPO_WIDTH = 7 then return (b"01111111"); elsif C_GPO_WIDTH = 8 then return (b"11111111"); end if; end function gpo_bit_used; ---------------------------------------------------------------------------- -- Function count_reg_bits_used -- -- This function returns either b"00000000" for no ten bit addressing or -- b"00000111" for ten bit addressing -- ---------------------------------------------------------------------------- function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY) return INTEGER_ARRAY is variable count : INTEGER_ARRAY; begin for i in 24 to 31 loop count(i) := 0; for m in 0 to NUM_IIC_REGS-1 loop --IP_REG_NUM - 1 if (REG_BITS_USED(m)(i) = '1') then count(i) := count(i) + 1; end if; end loop; end loop; return count; end function count_reg_bits_used; end package body iic_pkg;
------------------------------------------------------------------------------- -- iic_pkg.vhd - Package ------------------------------------------------------------------------------- -- *************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2009 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- *************************************************************************** ------------------------------------------------------------------------------- -- Filename: iic_pkg.vhd -- Version: v1.01.b -- Description: This file contains the constants used in the design of the -- iic bus interface. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- -- axi_iic.vhd -- -- iic.vhd -- -- axi_ipif_ssp1.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- soft_reset.vhd -- -- reg_interface.vhd -- -- filter.vhd -- -- debounce.vhd -- -- iic_control.vhd -- -- upcnt_n.vhd -- -- shift8.vhd -- -- dynamic_master.vhd -- -- iic_pkg.vhd -- ------------------------------------------------------------------------------- -- Author: USM -- -- USM 10/15/09 -- ^^^^^^ -- - Initial release of v1.00.a -- ~~~~~~ -- -- USM 09/06/10 -- ^^^^^^ -- - Release of v1.01.a -- ~~~~~~ -- -- NLR 01/07/11 -- ^^^^^^ -- - Release of v1.01.b -- ~~~~~~ -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package iic_pkg is ---------------------------------------------------------------------------- -- Constant Declarations ---------------------------------------------------------------------------- constant RESET_ACTIVE : std_logic := '1'; -- Reset Constant constant NUM_IIC_REGS : integer := 11; -- should be same as C_NUM_IIC_REGS in axi_iic top constant DATA_BITS : natural := 8; -- FIFO Width Generic constant TX_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits constant RC_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits --IPIF Generics that must remain at these values for the IIC constant INCLUDE_DEV_PENCODER : BOOLEAN := False; constant IPIF_ABUS_WIDTH : INTEGER := 32; constant INCLUDE_DEV_ISC : Boolean := false; type STD_LOGIC_VECTOR_ARRAY is array (0 to NUM_IIC_REGS-1) of std_logic_vector(24 to 31); type INTEGER_ARRAY is array (24 to 31) of integer; ---------------------------------------------------------------------------- -- Function and Procedure Declarations ---------------------------------------------------------------------------- function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer; C_IIC_FREQ : integer) return integer; function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector; function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector; function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY) return INTEGER_ARRAY; end package iic_pkg; ------------------------------------------------------------------------------- -- Package body ------------------------------------------------------------------------------- package body iic_pkg is ---------------------------------------------------------------------------- -- Function Definitions ---------------------------------------------------------------------------- -- Function num_ctr_bits -- -- This function returns the number of bits required to count 1/2 the period -- of the SCL clock. -- ---------------------------------------------------------------------------- function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer; C_IIC_FREQ : integer) return integer is variable num_bits : integer :=0; variable i : integer :=0; begin -- for loop used because XST service pack 2 does not support While loops if C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ > C_S_AXI_ACLK_FREQ_HZ/212766 then for i in 0 to 30 loop -- 30 is a magic number needed for for loops if 2**i < C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ then num_bits := num_bits + 1; end if; end loop; return (num_bits); else for i in 0 to 30 loop if 2**i < C_S_AXI_ACLK_FREQ_HZ/212766 then num_bits := num_bits + 1; end if; end loop; return (num_bits); end if; end function num_ctr_bits; ---------------------------------------------------------------------------- -- Function ten_bit_addr_used -- -- This function returns either b"00000000" for no ten bit addressing or -- b"00000111" for ten bit addressing -- ---------------------------------------------------------------------------- function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector is begin if C_TEN_BIT_ADR = 0 then return (b"00000000"); else return (b"00000111"); end if; end function ten_bit_addr_used; ---------------------------------------------------------------------------- -- Function gpo_bit_used -- -- This function returns b"00000000" up to b"11111111" depending on -- C_GPO_WIDTH -- ---------------------------------------------------------------------------- function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector is begin if C_GPO_WIDTH = 1 then return (b"00000001"); elsif C_GPO_WIDTH = 2 then return (b"00000011"); elsif C_GPO_WIDTH = 3 then return (b"00000111"); elsif C_GPO_WIDTH = 4 then return (b"00001111"); elsif C_GPO_WIDTH = 5 then return (b"00011111"); elsif C_GPO_WIDTH = 6 then return (b"00111111"); elsif C_GPO_WIDTH = 7 then return (b"01111111"); elsif C_GPO_WIDTH = 8 then return (b"11111111"); end if; end function gpo_bit_used; ---------------------------------------------------------------------------- -- Function count_reg_bits_used -- -- This function returns either b"00000000" for no ten bit addressing or -- b"00000111" for ten bit addressing -- ---------------------------------------------------------------------------- function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY) return INTEGER_ARRAY is variable count : INTEGER_ARRAY; begin for i in 24 to 31 loop count(i) := 0; for m in 0 to NUM_IIC_REGS-1 loop --IP_REG_NUM - 1 if (REG_BITS_USED(m)(i) = '1') then count(i) := count(i) + 1; end if; end loop; end loop; return count; end function count_reg_bits_used; end package body iic_pkg;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: RxTstFIFO2K_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity RxTstFIFO2K_exdes is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end RxTstFIFO2K_exdes; architecture xilinx of RxTstFIFO2K_exdes is signal wr_clk_i : std_logic; signal rd_clk_i : std_logic; component RxTstFIFO2K is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin wr_clk_buf: bufg PORT map( i => WR_CLK, o => wr_clk_i ); rd_clk_buf: bufg PORT map( i => RD_CLK, o => rd_clk_i ); exdes_inst : RxTstFIFO2K PORT MAP ( WR_CLK => wr_clk_i, RD_CLK => rd_clk_i, RST => rst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core - core top file for implementation -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: RxTstFIFO2K_exdes.vhd -- -- Description: -- This is the FIFO core wrapper with BUFG instances for clock connections. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- Entity Declaration -------------------------------------------------------------------------------- entity RxTstFIFO2K_exdes is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end RxTstFIFO2K_exdes; architecture xilinx of RxTstFIFO2K_exdes is signal wr_clk_i : std_logic; signal rd_clk_i : std_logic; component RxTstFIFO2K is PORT ( WR_CLK : IN std_logic; RD_CLK : IN std_logic; RST : IN std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(8-1 DOWNTO 0); DOUT : OUT std_logic_vector(16-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); end component; begin wr_clk_buf: bufg PORT map( i => WR_CLK, o => wr_clk_i ); rd_clk_buf: bufg PORT map( i => RD_CLK, o => rd_clk_i ); exdes_inst : RxTstFIFO2K PORT MAP ( WR_CLK => wr_clk_i, RD_CLK => rd_clk_i, RST => rst, WR_EN => wr_en, RD_EN => rd_en, DIN => din, DOUT => dout, FULL => full, EMPTY => empty); end xilinx;
---------------------------------------------------------------------------------- -- Module Name: test_source_800_600_RGB_444 - Behavioral -- -- Description: Generate a valid DisplayPort symbol stream for testing. In this -- case 800x600 white screen. -- ---------------------------------------------------------------------------------- -- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort ------------------------------------------------------------------------------------ -- The MIT License (MIT) -- -- Copyright (c) 2015 Michael Alan Field <[email protected]> -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. ------------------------------------------------------------------------------------ ----- Want to say thanks? ---------------------------------------------------------- ------------------------------------------------------------------------------------ -- -- This design has taken many hours - 3 months of work. I'm more than happy -- to share it if you can make use of it. It is released under the MIT license, -- so you are not under any onus to say thanks, but.... -- -- If you what to say thanks for this design either drop me an email, or how about -- trying PayPal to my email ([email protected])? -- -- Educational use - Enough for a beer -- Hobbyist use - Enough for a pizza -- Research use - Enough to take the family out to dinner -- Commercial use - A weeks pay for an engineer (I wish!) -------------------------------------------------------------------------------------- -- Ver | Date | Change --------+------------+--------------------------------------------------------------- -- 0.1 | 2015-09-17 | Initial Version ---------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity test_source_800_600_RGB_444_ch1 is port ( ----------------------------------------------------- -- The MSA values (some are range reduced and could -- be 16 bits ins size) ----------------------------------------------------- M_value : out std_logic_vector(23 downto 0); N_value : out std_logic_vector(23 downto 0); H_visible : out std_logic_vector(11 downto 0); V_visible : out std_logic_vector(11 downto 0); H_total : out std_logic_vector(11 downto 0); V_total : out std_logic_vector(11 downto 0); H_sync_width : out std_logic_vector(11 downto 0); V_sync_width : out std_logic_vector(11 downto 0); H_start : out std_logic_vector(11 downto 0); V_start : out std_logic_vector(11 downto 0); H_vsync_active_high : out std_logic; V_vsync_active_high : out std_logic; flag_sync_clock : out std_logic; flag_YCCnRGB : out std_logic; flag_422n444 : out std_logic; flag_YCC_colour_709 : out std_logic; flag_range_reduced : out std_logic; flag_interlaced_even : out std_logic; flags_3d_Indicators : out std_logic_vector(1 downto 0); bits_per_colour : out std_logic_vector(4 downto 0); stream_channel_count : out std_logic_vector(2 downto 0); clk : in std_logic; ready : out std_logic; data : out std_logic_vector(72 downto 0) := (others => '0') ); end test_source_800_600_RGB_444_ch1; architecture arch of test_source_800_600_RGB_444_ch1 is type a_test_data_blocks is array (0 to 64*6-1) of std_logic_vector(8 downto 0); constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0xAA constant SPARE : std_logic_vector(8 downto 0) := "011111111"; -- 0xFF constant ZERO : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 constant PIX_80 : std_logic_vector(8 downto 0) := "011001100"; -- 0x80 constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2 constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7 constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7 constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5 constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0 constant FS : std_logic_vector(8 downto 0) := "111111110"; -- K30.7 constant FE : std_logic_vector(8 downto 0) := "111110111"; -- K23.7 constant VB_VS : std_logic_vector(8 downto 0) := "000000001"; -- 0x00 VB-ID with Vertical blank asserted constant VB_NVS : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 VB-ID without Vertical blank asserted constant Mvid : std_logic_vector(8 downto 0) := "001101000"; -- 0x68 constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 constant test_data_blocks : a_test_data_blocks := ( --- Block 0 - Junk DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, --- Block 1 - 8 white pixels and padding PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, --- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, BS, VB_NVS, MVID, MAUD, VB_NVS, MVID, MAUD, VB_NVS, MVID, MAUD, VB_NVS, MVID, MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, --- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, BS, VB_VS, MVID, MAUD, VB_VS, MVID, MAUD, VB_VS, MVID, MAUD, VB_VS, MVID, MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, --- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, BS, VB_VS, MVID, MAUD, VB_VS, MVID, MAUD, VB_VS, MVID, MAUD, VB_VS, MVID, MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, --- Block 5 - just blank end DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, BE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE); signal index : unsigned (8 downto 0) := (others => '0'); -- Index up to 32 x 64 symbol blocks signal d0: std_logic_vector(8 downto 0) := (others => '0'); signal d1: std_logic_vector(8 downto 0) := (others => '0'); signal line_count : unsigned(9 downto 0) := (others => '0'); signal row_count : unsigned(7 downto 0) := (others => '0'); signal switch_point : std_logic := '0'; begin M_value <= x"012F68"; N_value <= x"080000"; H_visible <= x"320"; -- 800 V_visible <= x"258"; -- 600 H_total <= x"420"; -- 1056 V_total <= x"274"; -- 628 H_sync_width <= x"080"; -- 128 V_sync_width <= x"004"; -- 4 H_start <= x"0D8"; -- 216 V_start <= x"01b"; -- 37 H_vsync_active_high <= '0'; V_vsync_active_high <= '0'; flag_sync_clock <= '1'; flag_YCCnRGB <= '0'; flag_422n444 <= '0'; flag_range_reduced <= '0'; flag_interlaced_even <= '0'; flag_YCC_colour_709 <= '0'; flags_3d_Indicators <= (others => '0'); bits_per_colour <= "01000"; stream_channel_count <= "001"; ready <= '1'; data(72) <= switch_point; data(71 downto 18) <= (others => '0'); data(17 downto 0) <= d1 & d0; process(clk) begin if rising_edge(clk) then d0 <= test_data_blocks(to_integer(index+0)); d1 <= test_data_blocks(to_integer(index+1)); if index(5 downto 0) = 52 then index(5 downto 0) <= (others => '0'); if row_count = 131 then row_count <= (others => '0'); if line_count = 627 then line_count <= (others => '0'); else line_count <= line_count + 1; end if; else row_count <= row_count +1; end if; --- Block 0 - Junk --- Block 1- 8 white pixels and padding --- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk --- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk --- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk --- Block 5 - just blank end index(8 downto 6) <= "000"; -- Dummy symbols switch_point <= '0'; if line_count < 599 then -- lines of active video (except first and last) if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill elsif row_count = 100 then index(8 downto 6) <= "010"; -- Pixels BS and VS-ID block (no VBLANK flag) end if; elsif line_count = 599 then -- Last line of active video if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill elsif row_count = 100 then index(8 downto 6) <= "011"; -- Pixels BS and VS-ID block (with VBLANK flag) end if; else ----------------------------------------------------------------- -- Allow switching to/from the idle pattern during the vertical blank ----------------------------------------------------------------- if row_count < 100 then switch_point <= '1'; elsif row_count = 100 then index(8 downto 6) <= "100"; -- Dummy symbols, BS and VS-ID block (with VBLANK flag) end if; end if; else index <= index + 2; end if; end if; end process; end architecture;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --library ims; --use ims.coprocessor.all; entity MINIMUM_32b is port ( INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0); INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0); OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0) ); end; architecture rtl of MINIMUM_32b is begin ------------------------------------------------------------------------- -- synthesis translate_off process begin wait for 1 ns; ASSERT false REPORT "(IMS) MINIMUM_32b : ALLOCATION OK !"; wait; end process; -- synthesis translate_on ------------------------------------------------------------------------- ------------------------------------------------------------------------- process (INPUT_1, INPUT_2) begin if( SIGNED(INPUT_1) < SIGNED(INPUT_2) ) then OUTPUT_1 <= INPUT_1; else OUTPUT_1 <= INPUT_2; end if; end process; ------------------------------------------------------------------------- end;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top_level is Port ( mclk : in std_logic; rst : in std_logic; CQ_write_en : in STD_LOGIC; VQ_read_en : in STD_LOGIC; -- switches : in STD_LOGIC_VECTOR(7 downto 0); memory_address_bus: inout std_logic_vector(22 downto 0); memory_data_bus : inout std_logic_vector(15 downto 0); anodes : out STD_LOGIC_VECTOR(3 downto 0); decoder_out : out STD_LOGIC_VECTOR(6 downto 0); RAM_oe : out std_logic; RAM_we : out std_logic; RAM_adv : out std_logic; RAM_clk : out std_logic; RAM_ub : out std_logic; RAM_lb : out std_logic; RAM_ce : out std_logic; RAM_cre : out std_logic; RAM_wait : in std_logic; LEDs : out std_logic_vector(7 downto 0) ); end top_level; architecture Behavioral of top_level is component DCMi_80 is port ( CLKIN_IN : in std_logic; CLKFX_OUT : out std_logic; CLK0_OUT : out std_logic); end component; component four_dig_7seg is Port ( clock : in STD_LOGIC; display_data : in STD_LOGIC_VECTOR (15 downto 0); anodes : out STD_LOGIC_VECTOR (3 downto 0); to_display : out STD_LOGIC_VECTOR (6 downto 0)); end component; component memory is Port ( clk80 : in std_logic; rst : in std_logic; cam_vs : in STD_LOGIC; vid_vs : in STD_LOGIC; empty : out STD_LOGIC; full : out STD_LOGIC; CQ_write_en : in STD_LOGIC; -- CQ_write_clk : in STD_LOGIC; CQ_data_in : in STD_LOGIC_VECTOR(15 downto 0); VQ_read_en : in STD_LOGIC; -- VQ_read_clk : in STD_LOGIC; VQ_data_out : out STD_LOGIC_VECTOR(15 downto 0); -- VQ_data_out_dumb : out STD_LOGIC_VECTOR(15 downto 0); RAM_addr : out std_logic_vector(22 downto 0); RAM_data_out : out std_logic_vector(15 downto 0); RAM_data_in : in std_logic_vector(15 downto 0); RAM_oe : out std_logic; RAM_we : out std_logic; RAM_adv : out std_logic; RAM_clk_en : out std_logic; RAM_ub : out std_logic; RAM_lb : out std_logic; RAM_ce : out std_logic; RAM_cre : out std_logic; RAM_wait : in std_logic; led : out std_logic_vector(7 downto 0) ); end component; signal clk80, dcm_clk_25, RAM_clk_en : std_logic; signal count : std_logic_vector(24 downto 0); signal CQ_write_clk : STD_LOGIC; signal VQ_read_clk : STD_LOGIC; signal display_data : STD_LOGIC_VECTOR(15 downto 0); signal RAM_addr_s : std_logic_vector(22 downto 0); signal RAM_data_in, RAM_data_out, RAM_data_reg : std_logic_vector(15 downto 0); signal RAM_oe_s, RAM_oe_reg, RAM_we_s, RAM_adv_s, RAM_ub_s, RAM_lb_s, RAM_ce_s, RAM_cre_s : std_logic; signal pclk25, clk25:std_logic; signal clk_625 : STD_LOGIC; signal CQ_data_in_sig : STD_LOGIC_VECTOR(15 downto 0); begin clk25 <= count(0); pclk25 <= clk25; RAM_clk <= clk80; --when RAM_clk_en='1' else 'Z'; --CQ_write_clk <= count(3); --VQ_read_clk <= count(3); LEDs(0) <= count(24); --50 MHz clock divider mclk_proc: process(mclk, rst) begin if rst = '1' then count <= (others => '0'); elsif mclk'event and mclk = '1' then count <= count + 1; end if; end process; --Note, clk80 is now at 100 MHz, not 80 DCM1: DCMi_80 port map ( CLKIN_IN => pclk25, CLKFX_OUT => clk80, CLK0_OUT => dcm_clk_25 ); display: four_dig_7seg port map( clock => mclk, display_data => display_data, anodes => anodes, to_display => decoder_out); MainMem: memory Port map ( clk80 => clk80, rst => rst, empty => LEDs(1), full => LEDs(2), cam_vs => '0', vid_vs => '1', CQ_write_en => CQ_write_en, --CQ_write_clk => CQ_write_clk, CQ_data_in => CQ_data_in_sig, VQ_read_en => VQ_read_en, --VQ_read_clk => VQ_read_clk, VQ_data_out => display_data, RAM_addr => RAM_addr_s, RAM_data_out => RAM_data_out, RAM_data_in => RAM_data_in, RAM_oe => RAM_oe_s, RAM_we => RAM_we_s, RAM_adv => RAM_adv_s, RAM_clk_en => RAM_clk_en, RAM_ub => RAM_ub_s, RAM_lb => RAM_lb_s, RAM_ce => RAM_ce_s, RAM_cre => RAM_cre_s, RAM_wait => RAM_wait ); OutputRegs: process(clk80, rst) begin if rst='1' then memory_address_bus <= (others=>'0'); RAM_data_reg <= (others=>'0'); RAM_oe_reg <= '1'; RAM_we <= '1'; RAM_adv <= '1'; RAM_ub <= '1'; RAM_lb <= '1'; RAM_ce <= '1'; RAM_cre <= '0'; elsif clk80'event and clk80='0' then memory_address_bus <= RAM_addr_s; RAM_data_reg <= RAM_data_out; RAM_oe_reg <= RAM_oe_s; RAM_we <= RAM_we_s; RAM_adv <= RAM_adv_s; RAM_ub <= RAM_ub_s; RAM_lb <= RAM_lb_s; RAM_ce <= RAM_ce_s; RAM_cre <= RAM_cre_s; end if; end process; RAM_oe <= RAM_oe_reg; memory_data_bus <= RAM_data_reg when RAM_oe_reg='1' else (others=>'Z'); RAM_data_in <= memory_data_bus; CQ_data_in_sig <= x"6E6E"; LEDs(7 downto 3) <= (others => '0'); end Behavioral;
------------------------------------------------------------------------------ ---- ---- ---- Testbench for the ZPU Wishbone bridge ---- ---- ---- ---- Description: ---- ---- ---- ---- To Do: ---- ---- - ---- ---- ---- ---- Author: ---- ---- - Koen Martens, gmc sonologic.nl ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Copyright (c) ---- ---- ---- Distributed under the BSD license ---- ---- ---- ------------------------------------------------------------------------------ ---- ---- ---- Design unit: ---- File name: ---- Note: None ---- ---- Limitations: None known ---- ---- Errors: None known ---- ---- Library: work ---- ---- Dependencies: IEEE.std_logic_1164 ---- ---- IEEE.numeric_std ---- ---- Target FPGA: ---- Language: VHDL ---- ---- Wishbone: No ---- ---- Synthesis tools: N/A ---- ---- Simulation tools: ---- Text editor: ---- ---- ------------------------------------------------------------------------------ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library zpu; use zpu.wishbone.all; entity zpu_wishbone_intercon_tb is end entity zpu_wishbone_intercon_tb; architecture Behave of zpu_wishbone_intercon_tb is constant ADR_MSB : natural:=31; constant ADR_LSB : natural:=0; constant PAGE_BIT : natural:=4; constant NUNITS : natural:=8; constant CLK_FREQ : positive:=50; -- 50 MHz clock constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period -- testbench signal break : std_logic:='0'; signal clk : std_logic; -- wishbone signal wb_rst : std_logic; signal wb_stb : std_logic; signal wb_cyc : std_logic; signal wb_adr_i : std_logic_vector(ADR_MSB downto ADR_LSB); signal wb_adr_o : std_logic_vector(PAGE_BIT-1 downto 0); signal stb : std_logic_vector(NUNITS-1 downto 0); begin INTERCON : zpu_wishbone_intercon generic map( ADR_MSB => ADR_MSB, ADR_LSB => ADR_LSB, PAGE_BIT => PAGE_BIT, NUNITS => NUNITS ) port map( rst_i => wb_rst, stb_i => wb_stb, cyc_i => wb_cyc, adr_i => wb_adr_i, adr_o => wb_adr_o, stb_o => stb ); do_clock: process begin clk <= '0'; wait for CLK_S_PER; clk <= '1'; wait for CLK_S_PER; if break='1' then -- print("* Break asserted, end of test"); wait; end if; end process do_clock; do_sim: process begin wb_rst <= '0'; wb_stb <= '0'; wb_cyc <= '0'; wait for 1 us; wb_adr_i <= std_logic_vector(to_unsigned(10, 32)); wb_stb <= '1'; wb_cyc <= '1'; wait for 1 us; wb_stb <= '0'; wait for 1 us; wb_cyc <= '0'; wait for 1 us; wb_adr_i <= std_logic_vector(to_unsigned(54, 32)); wb_stb <= '1'; wb_cyc <= '1'; wait for 1 us; wb_stb <= '0'; wait for 1 us; wb_cyc <= '0'; wait for 1 us; end process do_sim; end architecture Behave; -- Entity: zpu_wishbone_bridge_tb
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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block GVgRO7Dr/KsjnVa35ieIUqOl4nqUKmu8XsjgW4UckaPlmajxFL9W0N5oPN2UnA3cGV8L7ALNikVv 1kAPCg6Bvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bkWq8f+reSrHy52xcAyiQE0oA2m9qup51X/HDFvssQqEzJrKhDENiv8uQSLbpPulVdR4ZmnTWeOs v9PQfvYyDJxEX1pdb2tbbhp8NIfz7u/RByiC3xydeBPYUxtIWUZ6VrLYI6eYb7AFTUFRLXxKi+W7 MBjtq0jooJMKYMxl7JM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block GVgRO7Dr/KsjnVa35ieIUqOl4nqUKmu8XsjgW4UckaPlmajxFL9W0N5oPN2UnA3cGV8L7ALNikVv 1kAPCg6Bvg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bkWq8f+reSrHy52xcAyiQE0oA2m9qup51X/HDFvssQqEzJrKhDENiv8uQSLbpPulVdR4ZmnTWeOs v9PQfvYyDJxEX1pdb2tbbhp8NIfz7u/RByiC3xydeBPYUxtIWUZ6VrLYI6eYb7AFTUFRLXxKi+W7 MBjtq0jooJMKYMxl7JM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
--------------------------------------------------------------------- -- TITLE: Memory Controller -- AUTHOR: Steve Rhoads ([email protected]) -- DATE CREATED: 1/31/01 -- FILENAME: mem_ctrl.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Memory controller for the Plasma CPU. -- Supports Big or Little Endian mode. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.mlite_pack.all; entity mem_ctrl is port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end; --entity mem_ctrl architecture logic of mem_ctrl is --"00" = big_endian; "11" = little_endian constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00"; signal opcode_reg : std_logic_vector(31 downto 0); signal next_opcode_reg : std_logic_vector(31 downto 0); signal address_reg : std_logic_vector(31 downto 2); signal byte_we_reg : std_logic_vector(3 downto 0); signal mem_state_reg : std_logic; constant STATE_ADDR : std_logic := '0'; constant STATE_ACCESS : std_logic := '1'; begin mem_proc: process(clk, reset_in, pause_in, nullify_op, address_pc, address_in, mem_source, data_write, data_r, opcode_reg, next_opcode_reg, mem_state_reg, address_reg, byte_we_reg) variable address_var : std_logic_vector(31 downto 2); variable data_read_var : std_logic_vector(31 downto 0); variable data_write_var : std_logic_vector(31 downto 0); variable opcode_next : std_logic_vector(31 downto 0); variable byte_we_var : std_logic_vector(3 downto 0); variable mem_state_next : std_logic; variable pause_var : std_logic; variable bits : std_logic_vector(1 downto 0); begin byte_we_var := "0000"; pause_var := '0'; data_read_var := ZERO; data_write_var := ZERO; mem_state_next := mem_state_reg; opcode_next := opcode_reg; case mem_source is when MEM_READ32 => data_read_var := data_r; when MEM_READ16 | MEM_READ16S => if address_in(1) = ENDIAN_MODE(1) then data_read_var(15 downto 0) := data_r(31 downto 16); else data_read_var(15 downto 0) := data_r(15 downto 0); end if; if mem_source = MEM_READ16 or data_read_var(15) = '0' then data_read_var(31 downto 16) := ZERO(31 downto 16); else data_read_var(31 downto 16) := ONES(31 downto 16); end if; when MEM_READ8 | MEM_READ8S => bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => data_read_var(7 downto 0) := data_r(31 downto 24); when "01" => data_read_var(7 downto 0) := data_r(23 downto 16); when "10" => data_read_var(7 downto 0) := data_r(15 downto 8); when others => data_read_var(7 downto 0) := data_r(7 downto 0); end case; if mem_source = MEM_READ8 or data_read_var(7) = '0' then data_read_var(31 downto 8) := ZERO(31 downto 8); else data_read_var(31 downto 8) := ONES(31 downto 8); end if; when MEM_WRITE32 => data_write_var := data_write; byte_we_var := "1111"; when MEM_WRITE16 => data_write_var := data_write(15 downto 0) & data_write(15 downto 0); if address_in(1) = ENDIAN_MODE(1) then byte_we_var := "1100"; else byte_we_var := "0011"; end if; when MEM_WRITE8 => data_write_var := data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0) & data_write(7 downto 0); bits := address_in(1 downto 0) xor ENDIAN_MODE; case bits is when "00" => byte_we_var := "1000"; when "01" => byte_we_var := "0100"; when "10" => byte_we_var := "0010"; when others => byte_we_var := "0001"; end case; when others => end case; if mem_source = MEM_FETCH then --opcode fetch address_var := address_pc; opcode_next := data_r; mem_state_next := STATE_ADDR; else if mem_state_reg = STATE_ADDR then if pause_in = '0' then address_var := address_in(31 downto 2); mem_state_next := STATE_ACCESS; pause_var := '1'; else address_var := address_pc; byte_we_var := "0000"; end if; else --STATE_ACCESS if pause_in = '0' then address_var := address_pc; opcode_next := next_opcode_reg; mem_state_next := STATE_ADDR; byte_we_var := "0000"; else address_var := address_in(31 downto 2); byte_we_var := "0000"; end if; end if; end if; if nullify_op = '1' and pause_in = '0' then opcode_next := ZERO; --NOP after beql end if; if reset_in = '1' then mem_state_reg <= STATE_ADDR; opcode_reg <= ZERO; next_opcode_reg <= ZERO; address_reg <= ZERO(31 downto 2); byte_we_reg <= "0000"; elsif rising_edge(clk) then if pause_in = '0' then address_reg <= address_var; byte_we_reg <= byte_we_var; mem_state_reg <= mem_state_next; opcode_reg <= opcode_next; if mem_state_reg = STATE_ADDR then next_opcode_reg <= data_r; end if; end if; end if; opcode_out <= opcode_reg; data_read <= data_read_var; pause_out <= pause_var; address_next <= address_var; byte_we_next <= byte_we_var; address <= address_reg; byte_we <= byte_we_reg; data_w <= data_write_var; end process; --data_proc end; --architecture logic
------------------------------------------------------------------------------- -- -- (C) COPYRIGHT 2010 Gideon's Logic Architectures' -- ------------------------------------------------------------------------------- -- -- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com) -- -- Note that this file is copyrighted, and is not supposed to be used in other -- projects without written permission from the author. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.my_math_pkg.all; entity sid_filter is generic ( g_divider : natural := 221 ); port ( clock : in std_logic; reset : in std_logic; enable : in std_logic; filt_co : in unsigned(10 downto 0); filt_res : in unsigned(3 downto 0); valid_in : in std_logic := '0'; error_out : out std_logic; input : in signed(17 downto 0); high_pass : out signed(17 downto 0); band_pass : out signed(17 downto 0); low_pass : out signed(17 downto 0); valid_out : out std_logic ); end sid_filter; architecture dsvf of sid_filter is signal filter_q : signed(17 downto 0); signal filter_f : signed(17 downto 0); signal input_sc : signed(17 downto 0); signal filt_ram : std_logic_vector(15 downto 0); signal xa : signed(17 downto 0); signal xb : signed(17 downto 0); signal sum_b : signed(17 downto 0); signal sub_a : signed(17 downto 0); signal sub_b : signed(17 downto 0); signal x_reg : signed(17 downto 0) := (others => '0'); signal bp_reg : signed(17 downto 0); signal hp_reg : signed(17 downto 0); signal lp_reg : signed(17 downto 0); signal temp_reg : signed(17 downto 0); signal error : std_logic := '0'; signal divider : integer range 0 to g_divider-1; signal instruction : std_logic_vector(7 downto 0); type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0); constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20"); type t_word_array is array(1023 downto 0) of signed(15 downto 0); constant coef : t_word_array := ( X"fff6", X"ffe5", X"ffd4", X"ffc3", X"ffb2", X"ffa0", X"ff8f", X"ff7e", X"ff6d", X"ff5c", X"ff4a", X"ff39", X"ff28", X"ff17", X"ff06", X"fef4", X"fee3", X"fed2", X"fec1", X"feb0", X"fe9e", X"fe8d", X"fe7c", X"fe6b", X"fe5a", X"fe48", X"fe37", X"fe26", X"fe15", X"fe04", X"fdf2", X"fde1", X"fdd0", X"fdbf", X"fdae", X"fd9c", X"fd8b", X"fd7a", X"fd69", X"fd58", X"fd46", X"fd35", X"fd24", X"fd13", X"fd02", X"fcf0", X"fcdf", X"fcce", X"fcbd", X"fcac", X"fc9a", X"fc89", X"fc78", X"fc67", X"fc56", X"fc44", X"fc33", X"fc22", X"fc11", X"fc00", X"fbee", X"fbdd", X"fbcc", X"fbbb", X"fb99", X"fb76", X"fb54", X"fb32", X"fb10", X"faee", X"facc", X"faaa", X"fa88", X"fa65", X"fa43", X"fa21", X"f9ff", X"f9dd", X"f9bb", X"f999", X"f976", X"f954", X"f932", X"f910", X"f8ee", X"f8cc", X"f8aa", X"f888", X"f865", X"f843", X"f821", X"f7ff", X"f7dd", X"f7bb", X"f799", X"f776", X"f754", X"f732", X"f710", X"f6ee", X"f6cc", X"f6aa", X"f688", X"f665", X"f643", X"f621", X"f5ff", X"f5dd", X"f5bb", X"f599", X"f576", X"f554", X"f532", X"f510", X"f4ee", X"f4cc", X"f4aa", X"f488", X"f465", X"f443", X"f421", X"f3ff", X"f3dd", X"f3bb", X"f399", X"f376", X"f354", X"f332", X"f2f4", X"f2b5", X"f276", X"f238", X"f1f9", X"f1bb", X"f17c", X"f13e", X"f0ff", X"f0c0", X"f082", X"f043", X"f005", X"efc6", X"ef88", X"ef49", X"ef0a", X"eecc", X"ee8d", X"ee4f", X"ee10", X"edd2", X"ed93", X"ed54", X"ed16", X"ecd7", X"ec99", X"ec5a", X"ec1b", X"ebdd", X"eb9e", X"eb60", X"eb21", X"eae3", X"eaa4", X"ea65", X"ea27", X"e9e8", X"e9aa", X"e96b", X"e92d", X"e8ee", X"e8af", X"e871", X"e832", X"e7f4", X"e7b5", X"e777", X"e738", X"e6f9", X"e6bb", X"e67c", X"e63e", X"e5ff", X"e5c0", X"e582", X"e543", X"e505", X"e4c6", X"e488", X"e449", X"e40a", X"e3cc", X"e38d", X"e338", X"e2e3", X"e28d", X"e238", X"e1e3", X"e18d", X"e138", X"e0e3", X"e08d", X"e038", X"dfe3", X"df8d", X"df38", X"dee3", X"de8d", X"de38", X"dde3", X"dd8d", X"dd38", X"dce3", X"dc8d", X"dc38", X"dbe3", X"db8d", X"db38", X"dae3", X"da8d", X"da38", X"d9e3", X"d98d", X"d938", X"d8e3", X"d88d", X"d838", X"d7e3", X"d78d", X"d738", X"d6e3", X"d68d", X"d638", X"d5e3", X"d58d", X"d538", X"d4e3", X"d48d", X"d438", X"d3e3", X"d38d", X"d338", X"d2e3", X"d28d", X"d238", X"d1e3", X"d18d", X"d138", X"d0e3", X"d08d", X"d038", X"cfe3", X"cf8d", X"cf38", X"cee3", X"ce8d", X"ce38", X"cdaa", X"cd1c", X"cc8d", X"cbff", X"cb71", X"cae3", X"ca54", X"c9c6", X"c938", X"c8aa", X"c81c", X"c78d", X"c6ff", X"c671", X"c5e3", X"c554", X"c4c6", X"c438", X"c3aa", X"c31c", X"c28d", X"c1ff", X"c171", X"c0e3", X"c054", X"bfc6", X"bf38", X"beaa", X"be1c", X"bd8d", X"bcff", X"bc71", X"bbe3", X"bb54", X"bac6", X"ba38", X"b9aa", X"b91c", X"b88d", X"b7ff", X"b771", X"b6e3", X"b654", X"b5c6", X"b538", X"b4aa", X"b41c", X"b38d", X"b2ff", X"b271", X"b1e3", X"b154", X"b0c6", X"b038", X"afaa", X"af1c", X"ae8d", X"adff", X"ad71", X"ace3", X"ac54", X"abc6", X"ab38", X"aaaa", X"aa1c", X"a98d", X"a8ff", X"a871", X"a7e3", X"a755", X"a6c6", X"a638", X"a5aa", X"a51c", X"a48d", X"a3ff", X"a371", X"a2e3", X"a255", X"a1c6", X"a138", X"a0aa", X"a01c", X"9f8d", X"9eff", X"9e71", X"9de3", X"9d55", X"9cc6", X"9c38", X"9baa", X"9b1c", X"9a8d", X"99ff", X"9971", X"98e3", X"9855", X"97c6", X"9738", X"96aa", X"961c", X"958d", X"94ff", X"9471", X"93e3", X"9355", X"92c6", X"9238", X"91aa", X"911c", X"908d", X"8fff", X"8f71", X"8ee3", X"8e55", X"8dc6", X"8d38", X"8caa", X"8c1c", X"8b8d", X"8aff", X"8a71", X"89e3", X"8955", X"88c6", X"8838", X"87aa", X"871c", X"8699", X"8616", X"8593", X"8510", X"848d", X"840b", X"8388", X"8305", X"8282", X"81ff", X"817c", X"80fa", X"8077", X"7ff4", X"7f71", X"7eee", X"7e6b", X"7de8", X"7d66", X"7ce3", X"7c60", X"7bdd", X"7b5a", X"7ad7", X"7a55", X"79d2", X"794f", X"78cc", X"7849", X"77c6", X"7744", X"76c1", X"763e", X"75bb", X"7538", X"74b5", X"7432", X"73b0", X"732d", X"72aa", X"7227", X"71a4", X"7121", X"709f", X"701c", X"6f99", X"6f16", X"6e93", X"6e10", X"6d8e", X"6d0b", X"6c88", X"6c05", X"6b82", X"6aff", X"6a7c", X"69fa", X"6977", X"68f4", X"6871", X"67ee", X"676b", X"66e9", X"6666", X"65dd", X"6555", X"64cc", X"6444", X"63bb", X"6333", X"62aa", X"6221", X"6199", X"6110", X"6088", X"5fff", X"5f77", X"5eee", X"5e66", X"5ddd", X"5d55", X"5ccc", X"5c44", X"5bbb", X"5b33", X"5aaa", X"5a21", X"5999", X"5910", X"5888", X"57ff", X"5777", X"56ee", X"5666", X"55dd", X"5555", X"54b5", X"5416", X"5377", X"52d8", X"5238", X"5199", X"50fa", X"505a", X"4fbb", X"4f1c", X"4e7d", X"4ddd", X"4d3e", X"4c9f", X"4bff", X"4b60", X"4ac8", X"4a31", X"4999", X"4901", X"486a", X"47d2", X"473a", X"46a2", X"460b", X"4573", X"44db", X"4444", X"438e", X"42d8", X"4222", X"416b", X"54b9", X"5381", X"5248", X"5110", X"4fff", X"4eee", X"4ddd", X"4ccc", X"4c16", X"4b60", X"4aaa", X"49f4", X"493e", X"4888", X"47d2", X"471c", X"467d", X"45dd", X"453e", X"449f", X"43ff", X"4360", X"42c1", X"4222", X"4182", X"40e3", X"4044", X"3fa4", X"3f05", X"3e66", X"3dc6", X"3d27", X"3caa", X"3c2d", X"3bb0", X"3b33", X"3ab5", X"3a38", X"39bb", X"393e", X"38c1", X"3844", X"37c7", X"3749", X"36cc", X"364f", X"35d2", X"3555", X"34d8", X"345a", X"33dd", X"3360", X"32e3", X"3266", X"31e9", X"316b", X"30ee", X"3071", X"2ff4", X"2f77", X"2efa", X"2e7d", X"2dff", X"2d82", X"2d1c", X"2cb5", X"2c4f", X"2be9", X"2b82", X"2b1c", X"2ab5", X"2a4f", X"29e9", X"2982", X"291c", X"28b5", X"284f", X"27e9", X"2782", X"271c", X"26b5", X"264f", X"25e9", X"2582", X"251c", X"24b5", X"244f", X"23e9", X"2382", X"231c", X"22b5", X"224f", X"21e9", X"2182", X"211c", X"20b5", X"2066", X"2016", X"1fc7", X"1f77", X"1f27", X"1ed8", X"1e88", X"1e38", X"1de9", X"1d99", X"1d49", X"1cfa", X"1caa", X"1c5a", X"1c0b", X"1bbb", X"1b6c", X"1b1c", X"1acc", X"1a7d", X"1a2d", X"19dd", X"198e", X"193e", X"18ee", X"189f", X"184f", X"17ff", X"17b0", X"1760", X"1711", X"16c1", X"1692", X"1664", X"1635", X"1606", X"15d8", X"15a9", X"157a", X"154c", X"151d", X"14ee", X"14c0", X"1491", X"1462", X"1434", X"1405", X"13d7", X"13a8", X"1379", X"134b", X"131c", X"12ed", X"12bf", X"1290", X"1261", X"1233", X"1204", X"11d5", X"11a7", X"1178", X"1149", X"111b", X"10ec", X"10bd", X"108f", X"1060", X"1032", X"1003", X"0fd4", X"0fa6", X"0f77", X"0f48", X"0f1a", X"0eeb", X"0ebc", X"0e8e", X"0e5f", X"0e30", X"0e02", X"0dd3", X"0da4", X"0d76", X"0d47", X"0d19", X"0cea", X"0cbb", X"0c8d", X"0c5e", X"0c2f", X"0c01", X"0bd2", X"0ba3", X"0b75", X"0b46", X"0b17", X"0b03", X"0aee", X"0ada", X"0ac5", X"0ab1", X"0a9c", X"0a88", X"0a74", X"0a5f", X"0a4b", X"0a36", X"0a22", X"0a0d", X"09f9", X"09e4", X"09d0", X"09bb", X"09a7", X"0992", X"097e", X"0969", X"0955", X"0940", X"092c", X"0917", X"0903", X"08ee", X"08da", X"08c5", X"08b1", X"089c", X"0888", X"0874", X"085f", X"084b", X"0836", X"0822", X"080d", X"07f9", X"07e4", X"07d0", X"07bb", X"07a7", X"0792", X"077e", X"0769", X"0755", X"0740", X"072c", X"0717", X"0703", X"06ee", X"06da", X"06c5", X"06b1", X"069d", X"0688", X"0674", X"065f", X"064b", X"0636", X"0622", X"060d", X"05f9", X"05f2", X"05eb", X"05e4", X"05dd", X"05d7", X"05d0", X"05c9", X"05c2", X"05bb", X"05b4", X"05ae", X"05a7", X"05a0", X"0599", X"0592", X"058b", X"0585", X"057e", X"0577", X"0570", X"0569", X"0562", X"055c", X"0555", X"054e", X"0547", X"0540", X"053a", X"0533", X"052c", X"0525", X"051e", X"0517", X"0511", X"050a", X"0503", X"04fc", X"04f5", X"04ee", X"04e8", X"04e1", X"04da", X"04d3", X"04cc", X"04c5", X"04bf", X"04b8", X"04b1", X"04aa", X"04a3", X"049d", X"0496", X"048f", X"0488", X"0481", X"047a", X"0474", X"046d", X"0466", X"045f", X"0458", X"0451", X"044b", X"0444", X"0441", X"043e", X"043b", X"0438", X"0436", X"0433", X"0430", X"042d", X"042a", X"0427", X"0424", X"0422", X"041f", X"041c", X"0419", X"0416", X"0413", X"0411", X"040e", X"040b", X"0408", X"0405", X"0402", X"03ff", X"03fd", X"03fa", X"03f7", X"03f4", X"03f1", X"03ee", X"03ec", X"03e9", X"03e6", X"03e3", X"03e0", X"03dd", X"03db", X"03d8", X"03d5", X"03d2", X"03cf", X"03cc", X"03c9", X"03c7", X"03c4", X"03c1", X"03be", X"03bb", X"03b8", X"03b6", X"03b3", X"03b0", X"03ad", X"03aa", X"03a7", X"03a4", X"03a2", X"039f", X"039c", X"0399", X"0396", X"0393", X"0391", X"038e", X"038d", X"038b", X"038a", X"0389", X"0388", X"0387", X"0386", X"0385", X"0383", X"0382", X"0381", X"0380", X"037f", X"037e", X"037d", X"037c", X"037a", X"0379", X"0378", X"0377", X"0376", X"0375", X"0374", X"0372", X"0371", X"0370", X"036f", X"036e", X"036d", X"036c", X"036a", X"0369", X"0368", X"0367", X"0366", X"0365", X"0364", X"0362", X"0361", X"0360", X"035f", X"035e", X"035d", X"035c", X"035b", X"0359", X"0358", X"0357", X"0356", X"0355", X"0354", X"0353", X"0351", X"0350", X"034f", X"034e", X"034d", X"034c", X"034b", X"0349", X"0348", X"0347", X"0346", X"0345", X"0344", X"0344", X"0343", X"0343", X"0342", X"0341", X"0341", X"0340", X"0340", X"033f", X"033f", X"033e", X"033e", X"033d", X"033c", X"033c", X"033b", X"033b", X"033a", X"033a", X"0339", X"0338", X"0338", X"0337", X"0337", X"0336", X"0336", X"0335", X"0334", X"0334", X"0333", X"0333", X"0332", X"0332", X"0331", X"0330", X"0330", X"032f", X"032f", X"032e", X"032e", X"032d", X"032c", X"032c", X"032b", X"032b", X"032a", X"032a", X"0329", X"0328", X"0328", X"0327", X"0327", X"0326", X"0326", X"0325", X"0324", X"0324", X"0323", X"0323", X"0322", X"0322", X"0321", X"0320" ); alias xa_select : std_logic is instruction(0); alias xb_select : std_logic is instruction(1); alias sub_a_sel : std_logic is instruction(2); alias sub_b_sel : std_logic is instruction(3); alias sum_to_lp : std_logic is instruction(4); alias sum_to_bp : std_logic is instruction(5); alias sub_to_hp : std_logic is instruction(6); alias mult_enable : std_logic is instruction(7); begin -- Derive the actual 'f' and 'q' parameters i_q_table: entity work.Q_table port map ( Q_reg => filt_res, filter_q => filter_q ); -- 2.16 format process(clock) begin if rising_edge(clock) then if(enable = '1') then filter_f <= "00" & coef(to_integer(filt_co(10 downto 1))); else filter_f <= "001111111111111111"; end if; end if; end process; --input_sc <= input; input_sc <= shift_right(input, 1); -- operations to execute the filter: -- bp_f = f * bp_reg -- q_contrib = q * bp_reg -- lp = bp_f + lp_reg -- temp = input - lp -- hp = temp - q_contrib -- hp_f = f * hp -- bp = hp_f + bp_reg -- bp_reg = bp -- lp_reg = lp -- x_reg = f * bp_reg -- 10000000 -- 80 -- lp_reg = x_reg + lp_reg -- 00010010 -- 12 -- q_contrib = q * bp_reg -- 10000001 -- 81 -- temp = input - lp -- 00000000 -- 00 (can be merged with previous!) -- hp_reg = temp - q_contrib -- 01001100 -- 4C -- x_reg = f * hp_reg -- 10000010 -- 82 -- bp_reg = x_reg + bp_reg -- 00100000 -- 20 -- now perform the arithmetic xa <= filter_f when xa_select='0' else filter_q; xb <= bp_reg when xb_select='0' else hp_reg; sum_b <= bp_reg when xb_select='0' else lp_reg; sub_a <= input_sc when sub_a_sel='0' else temp_reg; sub_b <= lp_reg when sub_b_sel='0' else x_reg; process(clock) variable x_result : signed(35 downto 0); variable sum_result : signed(17 downto 0); variable sub_result : signed(17 downto 0); begin if rising_edge(clock) then x_result := xa * xb; if mult_enable='1' then x_reg <= x_result(33 downto 16); if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then error <= not error; end if; end if; sum_result := sum_limit(x_reg, sum_b); temp_reg <= sum_result; if sum_to_lp='1' then lp_reg <= sum_result; end if; if sum_to_bp='1' then bp_reg <= sum_result; end if; sub_result := sub_limit(sub_a, sub_b); temp_reg <= sub_result; if sub_to_hp='1' then hp_reg <= sub_result; end if; -- control part instruction <= (others => '0'); if reset='1' then hp_reg <= (others => '0'); lp_reg <= (others => '0'); bp_reg <= (others => '0'); divider <= 0; elsif divider = g_divider-1 then divider <= 0; else divider <= divider + 1; if divider < c_program'length then instruction <= c_program(divider); end if; end if; if divider = c_program'length then valid_out <= '1'; else valid_out <= '0'; end if; end if; end process; high_pass <= hp_reg; band_pass <= bp_reg; low_pass <= lp_reg; error_out <= error; end dsvf;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mem_bus_pkg.all; -- This module performs the memory operations that are instructed -- by the nano_cpu. This controller copies data to or from a -- designated BRAM, and notifies the nano_cpu that the transfer -- is complete. entity usb_memory_ctrl is generic ( g_tag : std_logic_vector(7 downto 0) := X"55" ); port ( clock : in std_logic; reset : in std_logic; -- cmd interface cmd_addr : in std_logic_vector(3 downto 0); cmd_valid : in std_logic; cmd_write : in std_logic; cmd_wdata : in std_logic_vector(15 downto 0); cmd_ack : out std_logic; cmd_done : out std_logic; cmd_ready : out std_logic; -- BRAM interface ram_addr : out std_logic_vector(10 downto 2); ram_en : out std_logic; ram_we : out std_logic_vector(3 downto 0); ram_wdata : out std_logic_vector(31 downto 0); ram_rdata : in std_logic_vector(31 downto 0); -- memory interface mem_req : out t_mem_req_32; mem_resp : in t_mem_resp_32 ); end entity; architecture gideon of usb_memory_ctrl is type t_state is (idle, reading, writing, init); signal state : t_state; signal mem_addr_r : unsigned(25 downto 0) := (others => '0'); signal mem_addr_i : unsigned(25 downto 2) := (others => '0'); signal ram_addr_i : unsigned(8 downto 2) := (others => '0'); signal mreq : std_logic := '0'; signal rwn : std_logic := '1'; signal addr_do_load : std_logic := '0'; signal new_addr : std_logic := '0'; signal addr_do_inc : std_logic := '0'; signal rem_do_load : std_logic; signal rem_do_dec : std_logic; signal remain_is_0 : std_logic; signal remain_is_1 : std_logic; signal buffer_idx : std_logic_vector(10 downto 9) := "00"; signal ram_we_i : std_logic_vector(3 downto 0); signal ram_wnext : std_logic; signal rdata_valid : std_logic; signal first_req : std_logic; signal last_req : std_logic; begin mem_req.tag(7) <= last_req; mem_req.tag(6) <= first_req; mem_req.tag(5 downto 0) <= g_tag(5 downto 0); mem_req.request <= mreq; mem_req.address <= mem_addr_i & mem_addr_r(1 downto 0); mem_req.read_writen <= rwn; mem_req.data <= ram_rdata; mem_req.byte_en <= "1111"; -- pop from fifo when we process the access cmd_ack <= '1' when (state = idle) and (cmd_valid='1') else '0'; process(buffer_idx, state, mreq, mem_resp, ram_addr_i) begin ram_addr <= buffer_idx & std_logic_vector(ram_addr_i); ram_en <= '0'; -- for writing to memory, we enable the BRAM only when we are going to set -- the request, such that the data and the request comes at the same time case state is when writing => if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) or (mreq = '0') then ram_en <= '1'; end if; when others => null; end case; -- for reading from memory, it doesn't matter in which state we are: if ram_we_i /= "0000" then ram_en <= '1'; end if; end process; ram_we <= ram_we_i; process(clock) begin if rising_edge(clock) then rem_do_dec <= '0'; case state is when idle => rwn <= '1'; if cmd_valid='1' then if cmd_write='1' then cmd_done <= '0'; case cmd_addr is when X"0" => mem_addr_r(15 downto 0) <= unsigned(cmd_wdata(15 downto 0)); new_addr <= '1'; when X"1" => mem_addr_r(25 downto 16) <= unsigned(cmd_wdata(9 downto 0)); new_addr <= '1'; when X"2" => rwn <= '0'; state <= init; when X"3" => state <= init; when X"4" => buffer_idx <= cmd_wdata(15 downto 14); when others => null; end case; end if; end if; when init => new_addr <= '0'; ram_addr_i <= (others => '0'); if rwn='1' then state <= reading; else state <= writing; end if; when reading => rwn <= '1'; if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) or (mreq = '0') then if remain_is_0 = '1' then state <= idle; cmd_done <= '1'; mreq <= '0'; else first_req <= not mreq; last_req <= remain_is_1; mreq <= '1'; rem_do_dec <= '1'; end if; end if; when writing => rwn <= '0'; if (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) or (mreq = '0') then ram_addr_i <= ram_addr_i + 1; if remain_is_0 = '1' then state <= idle; cmd_done <= '1'; mreq <= '0'; else first_req <= not mreq; last_req <= remain_is_1; mreq <= '1'; rem_do_dec <= '1'; end if; end if; when others => null; end case; if ram_wnext = '1' then ram_addr_i <= ram_addr_i + 1; end if; if reset='1' then state <= idle; mreq <= '0'; cmd_done <= '0'; new_addr <= '0'; first_req <= '0'; end if; end if; end process; cmd_ready <= '1' when (state = idle) else '0'; addr_do_load <= new_addr when (state = init) else '0'; addr_do_inc <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(5 downto 0) = g_tag(5 downto 0)) else '0'; i_addr: entity work.mem_addr_counter port map ( clock => clock, load_value => mem_addr_r(25 downto 2), do_load => addr_do_load, do_inc => addr_do_inc, address => mem_addr_i ); rem_do_load <= '1' when cmd_valid='1' and cmd_write='1' and cmd_addr(3 downto 1)="001" else '0'; i_rem: entity work.mem_remain_counter port map ( clock => clock, load_value => unsigned(cmd_wdata(9 downto 2)), do_load => rem_do_load, do_dec => rem_do_dec, remain => open, remain_is_1 => remain_is_1, remain_is_0 => remain_is_0 ); rdata_valid <= '1' when mem_resp.dack_tag(5 downto 0) = g_tag(5 downto 0) else '0'; i_align: entity work.align_read_to_bram port map ( clock => clock, rdata => mem_resp.data, rdata_valid => rdata_valid, first_word => mem_resp.dack_tag(6), last_word => mem_resp.dack_tag(7), offset => mem_addr_r(1 downto 0), wdata => ram_wdata, wmask => ram_we_i, wnext => ram_wnext ); end architecture;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1826.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01826ent IS type small_int is range 0 to 7; END c07s01b00x00p08n01i01826ent; ARCHITECTURE c07s01b00x00p08n01i01826arch OF c07s01b00x00p08n01i01826ent IS signal s_int : small_int := c07s01b00x00p08n01i01826ent; --entity name illegal here BEGIN TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01826 - Entity name are not permitted as primaries in an initialization expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01826arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1826.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01826ent IS type small_int is range 0 to 7; END c07s01b00x00p08n01i01826ent; ARCHITECTURE c07s01b00x00p08n01i01826arch OF c07s01b00x00p08n01i01826ent IS signal s_int : small_int := c07s01b00x00p08n01i01826ent; --entity name illegal here BEGIN TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01826 - Entity name are not permitted as primaries in an initialization expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01826arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1826.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s01b00x00p08n01i01826ent IS type small_int is range 0 to 7; END c07s01b00x00p08n01i01826ent; ARCHITECTURE c07s01b00x00p08n01i01826arch OF c07s01b00x00p08n01i01826ent IS signal s_int : small_int := c07s01b00x00p08n01i01826ent; --entity name illegal here BEGIN TESTING : PROCESS BEGIN wait for 5 ns; assert FALSE report "***FAILED TEST: c07s01b00x00p08n01i01826 - Entity name are not permitted as primaries in an initialization expression." severity ERROR; wait; END PROCESS TESTING; END c07s01b00x00p08n01i01826arch;
-- ------------------------------------------------------------- -- -- Entity Declaration for ent_b -- -- Generated -- by: wig -- on: Tue Nov 29 13:29:43 2005 -- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: ent_b-e.vhd,v 1.3 2005/11/30 14:04:01 wig Exp $ -- $Date: 2005/11/30 14:04:01 $ -- $Log: ent_b-e.vhd,v $ -- Revision 1.3 2005/11/30 14:04:01 wig -- Updated testcase references -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.42 , [email protected] -- (C) 2003,2005 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity ent_b -- entity ent_b is -- Generics: -- No Generated Generics for Entity ent_b -- Generated Port Declaration: port( -- Generated Port for Entity ent_b port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false! sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name) -- End of Generated Port for Entity ent_b ); end ent_b; -- -- End of Generated Entity ent_b -- -- --!End of Entity/ies -- --------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter_1_6 is port(clk_50m,roll:in bit; out_count:inout std_logic_vector(3 downto 0)); end counter_1_6; architecture count of counter_1_6 is signal count:std_logic_vector(3 downto 0):="0000"; begin process(clk_50m,roll,count) begin if roll='1' then if clk_50m'event and clk_50m='0' then if count>"0100" then count<="0001"; else count<=count+1; end if; end if; else out_count<=count; end if; end process; end count;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sm.vhd -- Description: This entity contains the S2MM DMA Controller State Machine -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sm is generic ( C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Width of Buffer Length, Transferred Bytes, and BTT fields C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1 -- Depth of DataMover command FIFO ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- -- S2MM Control and Status -- s2mm_run_stop : in std_logic ; -- s2mm_keyhole : in std_logic ; -- s2mm_ftch_idle : in std_logic ; -- s2mm_desc_flush : in std_logic ; -- s2mm_cmnd_idle : out std_logic ; -- s2mm_sts_idle : out std_logic ; -- s2mm_eof_set : out std_logic ; -- s2mm_eof_micro : in std_logic ; -- s2mm_sof_micro : in std_logic ; -- -- -- S2MM Descriptor Fetch Request -- desc_fetch_req : out std_logic ; -- desc_fetch_done : in std_logic ; -- desc_update_done : in std_logic ; -- updt_pending : in std_logic ; desc_available : in std_logic ; -- -- -- S2MM Status Stream RX Length -- s2mm_rxlength_valid : in std_logic ; -- s2mm_rxlength_clr : out std_logic ; -- s2mm_rxlength : in std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- -- DataMover Command -- s2mm_cmnd_wr : out std_logic ; -- s2mm_cmnd_data : out std_logic_vector -- ((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); -- s2mm_cmnd_pending : in std_logic ; -- -- -- Descriptor Fields -- s2mm_desc_info : in std_logic_vector -- (31 downto 0); -- s2mm_desc_baddress : in std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_blength : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_v : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_s : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) -- ); end axi_dma_s2mm_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0'); -- DataMover Command Destination Stream Offset constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant S2MM_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH) := (others => '0'); -- Queued commands counter width constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1); -- Queued commands zero count constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); -- Zero buffer length error - compare value constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- State Machine Signals signal desc_fetch_req_cmb : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal s2mm_rxlength_clr_cmb : std_logic := '0'; signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_rxlength_set : std_logic := '0'; signal blength_grtr_rxlength : std_logic := '0'; signal rxlength_fetched : std_logic := '0'; signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0'); signal count_incr : std_logic := '0'; signal count_decr : std_logic := '0'; signal desc_fetch_done_d1 : std_logic := '0'; signal zero_length_error : std_logic := '0'; signal s2mm_eof_set_i : std_logic := '0'; signal queue_more : std_logic := '0'; signal burst_type : std_logic; signal eof_micro : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin EN_MICRO_DMA : if C_MICRO_DMA = 1 generate begin eof_micro <= s2mm_eof_micro; end generate EN_MICRO_DMA; NO_MICRO_DMA : if C_MICRO_DMA = 0 generate begin eof_micro <= '0'; end generate NO_MICRO_DMA; s2mm_eof_set <= s2mm_eof_set_i; burst_type <= '1' and (not s2mm_keyhole); -- A 0 s2mm_keyhole means incremental burst -- a 1 s2mm_keyhole means fixed burst ------------------------------------------------------------------------------- -- Not using rx length from status stream - (indeterminate length mode) ------------------------------------------------------------------------------- GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, -- EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin -- For no status stream or not using length in status app field then eof set is -- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd) s2mm_eof_set_i <= '0'; ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_fetch_done, desc_update_done, s2mm_cmnd_pending, s2mm_stop, s2mm_desc_flush, updt_pending -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => -- fetch descriptor if desc available, not stopped and running -- if (updt_pending = '1') then -- s2mm_ns <= WAIT_STATUS; if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 1) then s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; else s2mm_ns <= WAIT_STATUS; write_cmnd_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- exit if error or descriptor flushed if(s2mm_desc_flush = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; -- wait until fetch complete then execute -- elsif(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; -- s2mm_ns <= EXECUTE_XFER; elsif (s2mm_cmnd_pending = '0')then desc_fetch_req_cmb <= '0'; if (updt_pending = '0') then if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; write_cmnd_cmb <= '1'; else -- coverage off s2mm_ns <= WAIT_STATUS; -- coverage on end if; end if; else s2mm_ns <= FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- -- when EXECUTE_XFER => -- -- if error exit -- if(s2mm_stop = '1')then -- s2mm_ns <= IDLE; -- -- Write another command if there is not one already pending -- elsif(s2mm_cmnd_pending = '0')then -- if (updt_pending = '0') then -- write_cmnd_cmb <= '1'; -- end if; -- if(C_SG_INCLUDE_DESC_QUEUE = 1)then -- s2mm_ns <= IDLE; -- else -- s2mm_ns <= WAIT_STATUS; -- end if; -- else -- s2mm_ns <= EXECUTE_XFER; -- end if; ------------------------------------------------------------------- when WAIT_STATUS => -- for no Q wait until desc updated if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register State Machine Statues ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register State Machine Signalse ------------------------------------------------------------------------------- -- SM_SIG_REGISTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- desc_fetch_req <= '0' ; -- else -- if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- desc_fetch_req <= '1'; -- else -- desc_fetch_req <= desc_fetch_req_cmb ; -- end if; -- end if; -- end if; -- end process SM_SIG_REGISTER; desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else desc_fetch_req_cmb ; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For Indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & PAD_VALUE -- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro --'0' -- For Indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & s2mm_desc_blength; else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro -- For indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; end generate GEN_CMD_BTT_EQL_23; -- Drive unused output to zero s2mm_rxlength_clr <= '0'; end generate GEN_SM_FOR_NO_LENGTH; ------------------------------------------------------------------------------- -- Generate state machine and support logic for Using RX Length from Status -- Stream ------------------------------------------------------------------------------- -- this would not hold good for MCDMA GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, GET_RXLENGTH, CMPR_LENGTH, EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_update_done, -- desc_fetch_done, updt_pending, s2mm_rxlength_valid, rxlength_fetched, s2mm_cmnd_pending, zero_length_error, s2mm_stop, s2mm_desc_flush -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; s2mm_rxlength_clr_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_rxlength_set <= '0'; --rxlength_fetched_clr <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 0) then if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; else s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; --FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => desc_fetch_req_cmb <= '0'; -- exit if error or descriptor flushed if(s2mm_desc_flush = '1')then s2mm_ns <= IDLE; -- Descriptor fetch complete else --if(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; -- else -- desc_fetch_req_cmb <= '1'; end if; ------------------------------------------------------------------- WHEN GET_RXLENGTH => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- Buffer length zero, do not compare lengths, execute -- command to force datamover to issue interror elsif(zero_length_error = '1')then s2mm_ns <= EXECUTE_XFER; elsif(s2mm_rxlength_valid = '1')then s2mm_rxlength_set <= '1'; s2mm_rxlength_clr_cmb <= '1'; s2mm_ns <= CMPR_LENGTH; else s2mm_ns <= GET_RXLENGTH; end if; ------------------------------------------------------------------- WHEN CMPR_LENGTH => s2mm_ns <= EXECUTE_XFER; ------------------------------------------------------------------- when EXECUTE_XFER => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- write new command if one is not already pending elsif(s2mm_cmnd_pending = '0')then write_cmnd_cmb <= '1'; -- If descriptor queuing enabled then -- do NOT need to wait for status if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; -- No queuing therefore must wait for -- status before issuing next command else s2mm_ns <= WAIT_STATUS; end if; else s2mm_ns <= EXECUTE_XFER; end if; ------------------------------------------------------------------- -- coverage off when WAIT_STATUS => if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; -- coverage on ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register state machine states ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register state machine signals ------------------------------------------------------------------------------- SM_SIG_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_req <= '0' ; s2mm_rxlength_clr <= '0' ; else if (C_SG_INCLUDE_DESC_QUEUE = 0) then desc_fetch_req <= '1'; else desc_fetch_req <= desc_fetch_req_cmb ; end if; s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb; end if; end if; end process SM_SIG_REGISTER; ------------------------------------------------------------------------------- -- Check for a ZERO value in descriptor buffer length. If there is -- then flag an error and skip waiting for valid rxlength. cmnd will -- get written to datamover with BTT=0 and datamover will flag dmaint error -- which will be logged in desc, reset required to clear error ------------------------------------------------------------------------------- REG_ALIGN_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_done_d1 <= '0'; else desc_fetch_done_d1 <= desc_fetch_done; end if; end if; end process REG_ALIGN_DONE; ------------------------------------------------------------------------------- -- Zero length error detection - for determinate mode, detect early to prevent -- rxlength calcuation from first taking place. This will force a 0 BTT -- command to be issued to the datamover causing an internal error. ------------------------------------------------------------------------------- REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then zero_length_error <= '0'; elsif(desc_fetch_done_d1 = '1' and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then zero_length_error <= '1'; end if; end if; end process REG_ZERO_LNGTH_ERR; ------------------------------------------------------------------------------- -- Capture/Hold receive length from status stream. Also decrement length -- based on if received length is greater than descriptor buffer size. (i.e. is -- the case where multiple descriptors/buffers are used to describe one packet) ------------------------------------------------------------------------------- REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then rxlength <= (others => '0'); -- If command register rxlength from status stream fifo elsif(s2mm_rxlength_set = '1')then rxlength <= s2mm_rxlength; -- On command write if current desc buffer size not greater -- than current rxlength then decrement rxlength in preperations -- for subsequent commands elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0)) - unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0))); end if; end if; end process REG_RXLENGTH; ------------------------------------------------------------------------------- -- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To' -- Received Length value ------------------------------------------------------------------------------- REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then blength_grtr_rxlength <= '0'; elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then blength_grtr_rxlength <= '1'; else blength_grtr_rxlength <= '0'; end if; end if; end process REG_BLENGTH_GRTR_RXLNGTH; ------------------------------------------------------------------------------- -- On command assert rxlength fetched flag indicating length grabbed from -- status stream fifo ------------------------------------------------------------------------------- RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then rxlength_fetched <= '0'; elsif(s2mm_rxlength_set = '1')then rxlength_fetched <= '1'; end if; end if; end process RXLENGTH_FTCHED_PROCESS; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '0' -- Cat. EOF=0 to CMD Tag & '0' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '1' -- Cat. EOF=1 to CMD Tag & '1' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- Set EOF=1 & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '0' -- Cat. EOF='0' to CMD Tag & '0' -- Cat. IOC='0' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '1' -- Cat. EOF='1' to CMD Tag & '1' -- Cat. IOC='1' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_EQL_23; end generate GEN_SM_FOR_LENGTH; ------------------------------------------------------------------------------- -- Counter for keepting track of pending commands/status in primary datamover -- Use this to determine if primary datamover for s2mm is Idle. ------------------------------------------------------------------------------- -- Increment queue count for each command written if not occuring at -- same time a status from DM being updated to SG engine count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0' else '0'; -- Decrement queue count for each status update to SG engine if not occuring -- at same time as command being written to DM count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1' else '0'; -- keep track of number queue commands --CMD2STS_COUNTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then -- cmnds_queued <= (others => '0'); -- elsif(count_incr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1); -- elsif(count_decr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1); -- end if; -- end if; -- end process CMD2STS_COUNTER; QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift <= (others => '0'); elsif(count_incr = '1')then cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1'; elsif(count_decr = '1')then cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1); end if; end if; end process CMD2STS_COUNTER1; end generate QUEUE_COUNT; NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift (0) <= '0'; elsif(count_incr = '1')then cmnds_queued_shift (0) <= '1'; elsif(count_decr = '1')then cmnds_queued_shift (0) <= '0'; end if; end if; end process CMD2STS_COUNTER1; end generate NOQUEUE_COUNT; -- indicate idle when no more queued commands --s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000" -- else '0'; s2mm_sts_idle <= not cmnds_queued_shift(0); ------------------------------------------------------------------------------- -- Queue only the amount of commands that can be queued on descriptor update -- else lock up can occur. Note datamover command fifo depth is set to number -- of descriptors to queue. ------------------------------------------------------------------------------- --QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; -- else -- queue_more <= '0'; -- end if; -- end if; -- end process QUEUE_MORE_PROCESS; QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; else queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0'; end if; end if; end process QUEUE_MORE_PROCESS; end implementation;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sm.vhd -- Description: This entity contains the S2MM DMA Controller State Machine -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sm is generic ( C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Width of Buffer Length, Transferred Bytes, and BTT fields C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1 -- Depth of DataMover command FIFO ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- -- S2MM Control and Status -- s2mm_run_stop : in std_logic ; -- s2mm_keyhole : in std_logic ; -- s2mm_ftch_idle : in std_logic ; -- s2mm_desc_flush : in std_logic ; -- s2mm_cmnd_idle : out std_logic ; -- s2mm_sts_idle : out std_logic ; -- s2mm_eof_set : out std_logic ; -- s2mm_eof_micro : in std_logic ; -- s2mm_sof_micro : in std_logic ; -- -- -- S2MM Descriptor Fetch Request -- desc_fetch_req : out std_logic ; -- desc_fetch_done : in std_logic ; -- desc_update_done : in std_logic ; -- updt_pending : in std_logic ; desc_available : in std_logic ; -- -- -- S2MM Status Stream RX Length -- s2mm_rxlength_valid : in std_logic ; -- s2mm_rxlength_clr : out std_logic ; -- s2mm_rxlength : in std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- -- DataMover Command -- s2mm_cmnd_wr : out std_logic ; -- s2mm_cmnd_data : out std_logic_vector -- ((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); -- s2mm_cmnd_pending : in std_logic ; -- -- -- Descriptor Fields -- s2mm_desc_info : in std_logic_vector -- (31 downto 0); -- s2mm_desc_baddress : in std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_blength : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_v : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_s : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) -- ); end axi_dma_s2mm_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0'); -- DataMover Command Destination Stream Offset constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant S2MM_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH) := (others => '0'); -- Queued commands counter width constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1); -- Queued commands zero count constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); -- Zero buffer length error - compare value constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- State Machine Signals signal desc_fetch_req_cmb : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal s2mm_rxlength_clr_cmb : std_logic := '0'; signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_rxlength_set : std_logic := '0'; signal blength_grtr_rxlength : std_logic := '0'; signal rxlength_fetched : std_logic := '0'; signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0'); signal count_incr : std_logic := '0'; signal count_decr : std_logic := '0'; signal desc_fetch_done_d1 : std_logic := '0'; signal zero_length_error : std_logic := '0'; signal s2mm_eof_set_i : std_logic := '0'; signal queue_more : std_logic := '0'; signal burst_type : std_logic; signal eof_micro : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin EN_MICRO_DMA : if C_MICRO_DMA = 1 generate begin eof_micro <= s2mm_eof_micro; end generate EN_MICRO_DMA; NO_MICRO_DMA : if C_MICRO_DMA = 0 generate begin eof_micro <= '0'; end generate NO_MICRO_DMA; s2mm_eof_set <= s2mm_eof_set_i; burst_type <= '1' and (not s2mm_keyhole); -- A 0 s2mm_keyhole means incremental burst -- a 1 s2mm_keyhole means fixed burst ------------------------------------------------------------------------------- -- Not using rx length from status stream - (indeterminate length mode) ------------------------------------------------------------------------------- GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, -- EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin -- For no status stream or not using length in status app field then eof set is -- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd) s2mm_eof_set_i <= '0'; ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_fetch_done, desc_update_done, s2mm_cmnd_pending, s2mm_stop, s2mm_desc_flush, updt_pending -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => -- fetch descriptor if desc available, not stopped and running -- if (updt_pending = '1') then -- s2mm_ns <= WAIT_STATUS; if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 1) then s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; else s2mm_ns <= WAIT_STATUS; write_cmnd_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- exit if error or descriptor flushed if(s2mm_desc_flush = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; -- wait until fetch complete then execute -- elsif(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; -- s2mm_ns <= EXECUTE_XFER; elsif (s2mm_cmnd_pending = '0')then desc_fetch_req_cmb <= '0'; if (updt_pending = '0') then if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; write_cmnd_cmb <= '1'; else -- coverage off s2mm_ns <= WAIT_STATUS; -- coverage on end if; end if; else s2mm_ns <= FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- -- when EXECUTE_XFER => -- -- if error exit -- if(s2mm_stop = '1')then -- s2mm_ns <= IDLE; -- -- Write another command if there is not one already pending -- elsif(s2mm_cmnd_pending = '0')then -- if (updt_pending = '0') then -- write_cmnd_cmb <= '1'; -- end if; -- if(C_SG_INCLUDE_DESC_QUEUE = 1)then -- s2mm_ns <= IDLE; -- else -- s2mm_ns <= WAIT_STATUS; -- end if; -- else -- s2mm_ns <= EXECUTE_XFER; -- end if; ------------------------------------------------------------------- when WAIT_STATUS => -- for no Q wait until desc updated if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register State Machine Statues ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register State Machine Signalse ------------------------------------------------------------------------------- -- SM_SIG_REGISTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- desc_fetch_req <= '0' ; -- else -- if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- desc_fetch_req <= '1'; -- else -- desc_fetch_req <= desc_fetch_req_cmb ; -- end if; -- end if; -- end if; -- end process SM_SIG_REGISTER; desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else desc_fetch_req_cmb ; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For Indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & PAD_VALUE -- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro --'0' -- For Indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & s2mm_desc_blength; else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro -- For indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; end generate GEN_CMD_BTT_EQL_23; -- Drive unused output to zero s2mm_rxlength_clr <= '0'; end generate GEN_SM_FOR_NO_LENGTH; ------------------------------------------------------------------------------- -- Generate state machine and support logic for Using RX Length from Status -- Stream ------------------------------------------------------------------------------- -- this would not hold good for MCDMA GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, GET_RXLENGTH, CMPR_LENGTH, EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_update_done, -- desc_fetch_done, updt_pending, s2mm_rxlength_valid, rxlength_fetched, s2mm_cmnd_pending, zero_length_error, s2mm_stop, s2mm_desc_flush -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; s2mm_rxlength_clr_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_rxlength_set <= '0'; --rxlength_fetched_clr <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 0) then if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; else s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; --FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => desc_fetch_req_cmb <= '0'; -- exit if error or descriptor flushed if(s2mm_desc_flush = '1')then s2mm_ns <= IDLE; -- Descriptor fetch complete else --if(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; -- else -- desc_fetch_req_cmb <= '1'; end if; ------------------------------------------------------------------- WHEN GET_RXLENGTH => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- Buffer length zero, do not compare lengths, execute -- command to force datamover to issue interror elsif(zero_length_error = '1')then s2mm_ns <= EXECUTE_XFER; elsif(s2mm_rxlength_valid = '1')then s2mm_rxlength_set <= '1'; s2mm_rxlength_clr_cmb <= '1'; s2mm_ns <= CMPR_LENGTH; else s2mm_ns <= GET_RXLENGTH; end if; ------------------------------------------------------------------- WHEN CMPR_LENGTH => s2mm_ns <= EXECUTE_XFER; ------------------------------------------------------------------- when EXECUTE_XFER => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- write new command if one is not already pending elsif(s2mm_cmnd_pending = '0')then write_cmnd_cmb <= '1'; -- If descriptor queuing enabled then -- do NOT need to wait for status if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; -- No queuing therefore must wait for -- status before issuing next command else s2mm_ns <= WAIT_STATUS; end if; else s2mm_ns <= EXECUTE_XFER; end if; ------------------------------------------------------------------- -- coverage off when WAIT_STATUS => if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; -- coverage on ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register state machine states ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register state machine signals ------------------------------------------------------------------------------- SM_SIG_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_req <= '0' ; s2mm_rxlength_clr <= '0' ; else if (C_SG_INCLUDE_DESC_QUEUE = 0) then desc_fetch_req <= '1'; else desc_fetch_req <= desc_fetch_req_cmb ; end if; s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb; end if; end if; end process SM_SIG_REGISTER; ------------------------------------------------------------------------------- -- Check for a ZERO value in descriptor buffer length. If there is -- then flag an error and skip waiting for valid rxlength. cmnd will -- get written to datamover with BTT=0 and datamover will flag dmaint error -- which will be logged in desc, reset required to clear error ------------------------------------------------------------------------------- REG_ALIGN_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_done_d1 <= '0'; else desc_fetch_done_d1 <= desc_fetch_done; end if; end if; end process REG_ALIGN_DONE; ------------------------------------------------------------------------------- -- Zero length error detection - for determinate mode, detect early to prevent -- rxlength calcuation from first taking place. This will force a 0 BTT -- command to be issued to the datamover causing an internal error. ------------------------------------------------------------------------------- REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then zero_length_error <= '0'; elsif(desc_fetch_done_d1 = '1' and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then zero_length_error <= '1'; end if; end if; end process REG_ZERO_LNGTH_ERR; ------------------------------------------------------------------------------- -- Capture/Hold receive length from status stream. Also decrement length -- based on if received length is greater than descriptor buffer size. (i.e. is -- the case where multiple descriptors/buffers are used to describe one packet) ------------------------------------------------------------------------------- REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then rxlength <= (others => '0'); -- If command register rxlength from status stream fifo elsif(s2mm_rxlength_set = '1')then rxlength <= s2mm_rxlength; -- On command write if current desc buffer size not greater -- than current rxlength then decrement rxlength in preperations -- for subsequent commands elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0)) - unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0))); end if; end if; end process REG_RXLENGTH; ------------------------------------------------------------------------------- -- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To' -- Received Length value ------------------------------------------------------------------------------- REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then blength_grtr_rxlength <= '0'; elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then blength_grtr_rxlength <= '1'; else blength_grtr_rxlength <= '0'; end if; end if; end process REG_BLENGTH_GRTR_RXLNGTH; ------------------------------------------------------------------------------- -- On command assert rxlength fetched flag indicating length grabbed from -- status stream fifo ------------------------------------------------------------------------------- RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then rxlength_fetched <= '0'; elsif(s2mm_rxlength_set = '1')then rxlength_fetched <= '1'; end if; end if; end process RXLENGTH_FTCHED_PROCESS; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '0' -- Cat. EOF=0 to CMD Tag & '0' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '1' -- Cat. EOF=1 to CMD Tag & '1' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- Set EOF=1 & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '0' -- Cat. EOF='0' to CMD Tag & '0' -- Cat. IOC='0' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '1' -- Cat. EOF='1' to CMD Tag & '1' -- Cat. IOC='1' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_EQL_23; end generate GEN_SM_FOR_LENGTH; ------------------------------------------------------------------------------- -- Counter for keepting track of pending commands/status in primary datamover -- Use this to determine if primary datamover for s2mm is Idle. ------------------------------------------------------------------------------- -- Increment queue count for each command written if not occuring at -- same time a status from DM being updated to SG engine count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0' else '0'; -- Decrement queue count for each status update to SG engine if not occuring -- at same time as command being written to DM count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1' else '0'; -- keep track of number queue commands --CMD2STS_COUNTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then -- cmnds_queued <= (others => '0'); -- elsif(count_incr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1); -- elsif(count_decr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1); -- end if; -- end if; -- end process CMD2STS_COUNTER; QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift <= (others => '0'); elsif(count_incr = '1')then cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1'; elsif(count_decr = '1')then cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1); end if; end if; end process CMD2STS_COUNTER1; end generate QUEUE_COUNT; NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift (0) <= '0'; elsif(count_incr = '1')then cmnds_queued_shift (0) <= '1'; elsif(count_decr = '1')then cmnds_queued_shift (0) <= '0'; end if; end if; end process CMD2STS_COUNTER1; end generate NOQUEUE_COUNT; -- indicate idle when no more queued commands --s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000" -- else '0'; s2mm_sts_idle <= not cmnds_queued_shift(0); ------------------------------------------------------------------------------- -- Queue only the amount of commands that can be queued on descriptor update -- else lock up can occur. Note datamover command fifo depth is set to number -- of descriptors to queue. ------------------------------------------------------------------------------- --QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; -- else -- queue_more <= '0'; -- end if; -- end if; -- end process QUEUE_MORE_PROCESS; QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; else queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0'; end if; end if; end process QUEUE_MORE_PROCESS; end implementation;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sm.vhd -- Description: This entity contains the S2MM DMA Controller State Machine -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sm is generic ( C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Width of Buffer Length, Transferred Bytes, and BTT fields C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1 -- Depth of DataMover command FIFO ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- -- S2MM Control and Status -- s2mm_run_stop : in std_logic ; -- s2mm_keyhole : in std_logic ; -- s2mm_ftch_idle : in std_logic ; -- s2mm_desc_flush : in std_logic ; -- s2mm_cmnd_idle : out std_logic ; -- s2mm_sts_idle : out std_logic ; -- s2mm_eof_set : out std_logic ; -- s2mm_eof_micro : in std_logic ; -- s2mm_sof_micro : in std_logic ; -- -- -- S2MM Descriptor Fetch Request -- desc_fetch_req : out std_logic ; -- desc_fetch_done : in std_logic ; -- desc_update_done : in std_logic ; -- updt_pending : in std_logic ; desc_available : in std_logic ; -- -- -- S2MM Status Stream RX Length -- s2mm_rxlength_valid : in std_logic ; -- s2mm_rxlength_clr : out std_logic ; -- s2mm_rxlength : in std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- -- DataMover Command -- s2mm_cmnd_wr : out std_logic ; -- s2mm_cmnd_data : out std_logic_vector -- ((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); -- s2mm_cmnd_pending : in std_logic ; -- -- -- Descriptor Fields -- s2mm_desc_info : in std_logic_vector -- (31 downto 0); -- s2mm_desc_baddress : in std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_blength : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_v : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_s : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) -- ); end axi_dma_s2mm_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0'); -- DataMover Command Destination Stream Offset constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant S2MM_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH) := (others => '0'); -- Queued commands counter width constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1); -- Queued commands zero count constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); -- Zero buffer length error - compare value constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- State Machine Signals signal desc_fetch_req_cmb : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal s2mm_rxlength_clr_cmb : std_logic := '0'; signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_rxlength_set : std_logic := '0'; signal blength_grtr_rxlength : std_logic := '0'; signal rxlength_fetched : std_logic := '0'; signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0'); signal count_incr : std_logic := '0'; signal count_decr : std_logic := '0'; signal desc_fetch_done_d1 : std_logic := '0'; signal zero_length_error : std_logic := '0'; signal s2mm_eof_set_i : std_logic := '0'; signal queue_more : std_logic := '0'; signal burst_type : std_logic; signal eof_micro : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin EN_MICRO_DMA : if C_MICRO_DMA = 1 generate begin eof_micro <= s2mm_eof_micro; end generate EN_MICRO_DMA; NO_MICRO_DMA : if C_MICRO_DMA = 0 generate begin eof_micro <= '0'; end generate NO_MICRO_DMA; s2mm_eof_set <= s2mm_eof_set_i; burst_type <= '1' and (not s2mm_keyhole); -- A 0 s2mm_keyhole means incremental burst -- a 1 s2mm_keyhole means fixed burst ------------------------------------------------------------------------------- -- Not using rx length from status stream - (indeterminate length mode) ------------------------------------------------------------------------------- GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, -- EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin -- For no status stream or not using length in status app field then eof set is -- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd) s2mm_eof_set_i <= '0'; ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_fetch_done, desc_update_done, s2mm_cmnd_pending, s2mm_stop, s2mm_desc_flush, updt_pending -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => -- fetch descriptor if desc available, not stopped and running -- if (updt_pending = '1') then -- s2mm_ns <= WAIT_STATUS; if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 1) then s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; else s2mm_ns <= WAIT_STATUS; write_cmnd_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- exit if error or descriptor flushed if(s2mm_desc_flush = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; -- wait until fetch complete then execute -- elsif(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; -- s2mm_ns <= EXECUTE_XFER; elsif (s2mm_cmnd_pending = '0')then desc_fetch_req_cmb <= '0'; if (updt_pending = '0') then if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; write_cmnd_cmb <= '1'; else -- coverage off s2mm_ns <= WAIT_STATUS; -- coverage on end if; end if; else s2mm_ns <= FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- -- when EXECUTE_XFER => -- -- if error exit -- if(s2mm_stop = '1')then -- s2mm_ns <= IDLE; -- -- Write another command if there is not one already pending -- elsif(s2mm_cmnd_pending = '0')then -- if (updt_pending = '0') then -- write_cmnd_cmb <= '1'; -- end if; -- if(C_SG_INCLUDE_DESC_QUEUE = 1)then -- s2mm_ns <= IDLE; -- else -- s2mm_ns <= WAIT_STATUS; -- end if; -- else -- s2mm_ns <= EXECUTE_XFER; -- end if; ------------------------------------------------------------------- when WAIT_STATUS => -- for no Q wait until desc updated if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register State Machine Statues ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register State Machine Signalse ------------------------------------------------------------------------------- -- SM_SIG_REGISTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- desc_fetch_req <= '0' ; -- else -- if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- desc_fetch_req <= '1'; -- else -- desc_fetch_req <= desc_fetch_req_cmb ; -- end if; -- end if; -- end if; -- end process SM_SIG_REGISTER; desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else desc_fetch_req_cmb ; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For Indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & PAD_VALUE -- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro --'0' -- For Indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & s2mm_desc_blength; else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro -- For indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; end generate GEN_CMD_BTT_EQL_23; -- Drive unused output to zero s2mm_rxlength_clr <= '0'; end generate GEN_SM_FOR_NO_LENGTH; ------------------------------------------------------------------------------- -- Generate state machine and support logic for Using RX Length from Status -- Stream ------------------------------------------------------------------------------- -- this would not hold good for MCDMA GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, GET_RXLENGTH, CMPR_LENGTH, EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_update_done, -- desc_fetch_done, updt_pending, s2mm_rxlength_valid, rxlength_fetched, s2mm_cmnd_pending, zero_length_error, s2mm_stop, s2mm_desc_flush -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; s2mm_rxlength_clr_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_rxlength_set <= '0'; --rxlength_fetched_clr <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 0) then if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; else s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; --FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => desc_fetch_req_cmb <= '0'; -- exit if error or descriptor flushed if(s2mm_desc_flush = '1')then s2mm_ns <= IDLE; -- Descriptor fetch complete else --if(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; -- else -- desc_fetch_req_cmb <= '1'; end if; ------------------------------------------------------------------- WHEN GET_RXLENGTH => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- Buffer length zero, do not compare lengths, execute -- command to force datamover to issue interror elsif(zero_length_error = '1')then s2mm_ns <= EXECUTE_XFER; elsif(s2mm_rxlength_valid = '1')then s2mm_rxlength_set <= '1'; s2mm_rxlength_clr_cmb <= '1'; s2mm_ns <= CMPR_LENGTH; else s2mm_ns <= GET_RXLENGTH; end if; ------------------------------------------------------------------- WHEN CMPR_LENGTH => s2mm_ns <= EXECUTE_XFER; ------------------------------------------------------------------- when EXECUTE_XFER => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- write new command if one is not already pending elsif(s2mm_cmnd_pending = '0')then write_cmnd_cmb <= '1'; -- If descriptor queuing enabled then -- do NOT need to wait for status if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; -- No queuing therefore must wait for -- status before issuing next command else s2mm_ns <= WAIT_STATUS; end if; else s2mm_ns <= EXECUTE_XFER; end if; ------------------------------------------------------------------- -- coverage off when WAIT_STATUS => if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; -- coverage on ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register state machine states ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register state machine signals ------------------------------------------------------------------------------- SM_SIG_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_req <= '0' ; s2mm_rxlength_clr <= '0' ; else if (C_SG_INCLUDE_DESC_QUEUE = 0) then desc_fetch_req <= '1'; else desc_fetch_req <= desc_fetch_req_cmb ; end if; s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb; end if; end if; end process SM_SIG_REGISTER; ------------------------------------------------------------------------------- -- Check for a ZERO value in descriptor buffer length. If there is -- then flag an error and skip waiting for valid rxlength. cmnd will -- get written to datamover with BTT=0 and datamover will flag dmaint error -- which will be logged in desc, reset required to clear error ------------------------------------------------------------------------------- REG_ALIGN_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_done_d1 <= '0'; else desc_fetch_done_d1 <= desc_fetch_done; end if; end if; end process REG_ALIGN_DONE; ------------------------------------------------------------------------------- -- Zero length error detection - for determinate mode, detect early to prevent -- rxlength calcuation from first taking place. This will force a 0 BTT -- command to be issued to the datamover causing an internal error. ------------------------------------------------------------------------------- REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then zero_length_error <= '0'; elsif(desc_fetch_done_d1 = '1' and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then zero_length_error <= '1'; end if; end if; end process REG_ZERO_LNGTH_ERR; ------------------------------------------------------------------------------- -- Capture/Hold receive length from status stream. Also decrement length -- based on if received length is greater than descriptor buffer size. (i.e. is -- the case where multiple descriptors/buffers are used to describe one packet) ------------------------------------------------------------------------------- REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then rxlength <= (others => '0'); -- If command register rxlength from status stream fifo elsif(s2mm_rxlength_set = '1')then rxlength <= s2mm_rxlength; -- On command write if current desc buffer size not greater -- than current rxlength then decrement rxlength in preperations -- for subsequent commands elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0)) - unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0))); end if; end if; end process REG_RXLENGTH; ------------------------------------------------------------------------------- -- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To' -- Received Length value ------------------------------------------------------------------------------- REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then blength_grtr_rxlength <= '0'; elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then blength_grtr_rxlength <= '1'; else blength_grtr_rxlength <= '0'; end if; end if; end process REG_BLENGTH_GRTR_RXLNGTH; ------------------------------------------------------------------------------- -- On command assert rxlength fetched flag indicating length grabbed from -- status stream fifo ------------------------------------------------------------------------------- RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then rxlength_fetched <= '0'; elsif(s2mm_rxlength_set = '1')then rxlength_fetched <= '1'; end if; end if; end process RXLENGTH_FTCHED_PROCESS; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '0' -- Cat. EOF=0 to CMD Tag & '0' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '1' -- Cat. EOF=1 to CMD Tag & '1' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- Set EOF=1 & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '0' -- Cat. EOF='0' to CMD Tag & '0' -- Cat. IOC='0' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '1' -- Cat. EOF='1' to CMD Tag & '1' -- Cat. IOC='1' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_EQL_23; end generate GEN_SM_FOR_LENGTH; ------------------------------------------------------------------------------- -- Counter for keepting track of pending commands/status in primary datamover -- Use this to determine if primary datamover for s2mm is Idle. ------------------------------------------------------------------------------- -- Increment queue count for each command written if not occuring at -- same time a status from DM being updated to SG engine count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0' else '0'; -- Decrement queue count for each status update to SG engine if not occuring -- at same time as command being written to DM count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1' else '0'; -- keep track of number queue commands --CMD2STS_COUNTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then -- cmnds_queued <= (others => '0'); -- elsif(count_incr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1); -- elsif(count_decr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1); -- end if; -- end if; -- end process CMD2STS_COUNTER; QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift <= (others => '0'); elsif(count_incr = '1')then cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1'; elsif(count_decr = '1')then cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1); end if; end if; end process CMD2STS_COUNTER1; end generate QUEUE_COUNT; NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift (0) <= '0'; elsif(count_incr = '1')then cmnds_queued_shift (0) <= '1'; elsif(count_decr = '1')then cmnds_queued_shift (0) <= '0'; end if; end if; end process CMD2STS_COUNTER1; end generate NOQUEUE_COUNT; -- indicate idle when no more queued commands --s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000" -- else '0'; s2mm_sts_idle <= not cmnds_queued_shift(0); ------------------------------------------------------------------------------- -- Queue only the amount of commands that can be queued on descriptor update -- else lock up can occur. Note datamover command fifo depth is set to number -- of descriptors to queue. ------------------------------------------------------------------------------- --QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; -- else -- queue_more <= '0'; -- end if; -- end if; -- end process QUEUE_MORE_PROCESS; QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; else queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0'; end if; end if; end process QUEUE_MORE_PROCESS; end implementation;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_s2mm_sm.vhd -- Description: This entity contains the S2MM DMA Controller State Machine -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_8; use axi_dma_v7_1_8.axi_dma_pkg.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; ------------------------------------------------------------------------------- entity axi_dma_s2mm_sm is generic ( C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for S2MM Write Port C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1; -- Enable or Disable use of Status Stream Rx Length. Only valid -- if C_SG_INCLUDE_STSCNTRL_STRM = 1 -- 0 = Don't use Rx Length -- 1 = Use Rx Length C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14; -- Width of Buffer Length, Transferred Bytes, and BTT fields C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0; -- Include or Exclude Scatter Gather Descriptor Queuing -- 0 = Exclude SG Descriptor Queuing -- 1 = Include SG Descriptor Queuing C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1 -- Depth of DataMover command FIFO ); port ( m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- s2mm_stop : in std_logic ; -- -- -- S2MM Control and Status -- s2mm_run_stop : in std_logic ; -- s2mm_keyhole : in std_logic ; -- s2mm_ftch_idle : in std_logic ; -- s2mm_desc_flush : in std_logic ; -- s2mm_cmnd_idle : out std_logic ; -- s2mm_sts_idle : out std_logic ; -- s2mm_eof_set : out std_logic ; -- s2mm_eof_micro : in std_logic ; -- s2mm_sof_micro : in std_logic ; -- -- -- S2MM Descriptor Fetch Request -- desc_fetch_req : out std_logic ; -- desc_fetch_done : in std_logic ; -- desc_update_done : in std_logic ; -- updt_pending : in std_logic ; desc_available : in std_logic ; -- -- -- S2MM Status Stream RX Length -- s2mm_rxlength_valid : in std_logic ; -- s2mm_rxlength_clr : out std_logic ; -- s2mm_rxlength : in std_logic_vector -- (C_SG_LENGTH_WIDTH - 1 downto 0) ; -- -- -- DataMover Command -- s2mm_cmnd_wr : out std_logic ; -- s2mm_cmnd_data : out std_logic_vector -- ((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); -- s2mm_cmnd_pending : in std_logic ; -- -- -- Descriptor Fields -- s2mm_desc_info : in std_logic_vector -- (31 downto 0); -- s2mm_desc_baddress : in std_logic_vector -- (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- s2mm_desc_blength : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_v : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0); -- s2mm_desc_blength_s : in std_logic_vector -- (BUFFER_LENGTH_WIDTH-1 downto 0) -- ); end axi_dma_s2mm_sm; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_s2mm_sm is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- DataMover Commmand TAG constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0'); -- DataMover Command Destination Stream Offset constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0'); -- DataMover Cmnd Reserved Bits constant S2MM_CMD_RSVD : std_logic_vector( DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH) := (others => '0'); -- Queued commands counter width constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1); -- Queued commands zero count constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); -- Zero buffer length error - compare value constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- State Machine Signals signal desc_fetch_req_cmb : std_logic := '0'; signal write_cmnd_cmb : std_logic := '0'; signal s2mm_rxlength_clr_cmb : std_logic := '0'; signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0'); signal s2mm_rxlength_set : std_logic := '0'; signal blength_grtr_rxlength : std_logic := '0'; signal rxlength_fetched : std_logic := '0'; signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0'); signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0'); signal count_incr : std_logic := '0'; signal count_decr : std_logic := '0'; signal desc_fetch_done_d1 : std_logic := '0'; signal zero_length_error : std_logic := '0'; signal s2mm_eof_set_i : std_logic := '0'; signal queue_more : std_logic := '0'; signal burst_type : std_logic; signal eof_micro : std_logic; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin EN_MICRO_DMA : if C_MICRO_DMA = 1 generate begin eof_micro <= s2mm_eof_micro; end generate EN_MICRO_DMA; NO_MICRO_DMA : if C_MICRO_DMA = 0 generate begin eof_micro <= '0'; end generate NO_MICRO_DMA; s2mm_eof_set <= s2mm_eof_set_i; burst_type <= '1' and (not s2mm_keyhole); -- A 0 s2mm_keyhole means incremental burst -- a 1 s2mm_keyhole means fixed burst ------------------------------------------------------------------------------- -- Not using rx length from status stream - (indeterminate length mode) ------------------------------------------------------------------------------- GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, -- EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin -- For no status stream or not using length in status app field then eof set is -- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd) s2mm_eof_set_i <= '0'; ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_fetch_done, desc_update_done, s2mm_cmnd_pending, s2mm_stop, s2mm_desc_flush, updt_pending -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => -- fetch descriptor if desc available, not stopped and running -- if (updt_pending = '1') then -- s2mm_ns <= WAIT_STATUS; if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 1) then s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; else s2mm_ns <= WAIT_STATUS; write_cmnd_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => -- exit if error or descriptor flushed if(s2mm_desc_flush = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; -- wait until fetch complete then execute -- elsif(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; -- s2mm_ns <= EXECUTE_XFER; elsif (s2mm_cmnd_pending = '0')then desc_fetch_req_cmb <= '0'; if (updt_pending = '0') then if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; write_cmnd_cmb <= '1'; else -- coverage off s2mm_ns <= WAIT_STATUS; -- coverage on end if; end if; else s2mm_ns <= FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- -- when EXECUTE_XFER => -- -- if error exit -- if(s2mm_stop = '1')then -- s2mm_ns <= IDLE; -- -- Write another command if there is not one already pending -- elsif(s2mm_cmnd_pending = '0')then -- if (updt_pending = '0') then -- write_cmnd_cmb <= '1'; -- end if; -- if(C_SG_INCLUDE_DESC_QUEUE = 1)then -- s2mm_ns <= IDLE; -- else -- s2mm_ns <= WAIT_STATUS; -- end if; -- else -- s2mm_ns <= EXECUTE_XFER; -- end if; ------------------------------------------------------------------- when WAIT_STATUS => -- for no Q wait until desc updated if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register State Machine Statues ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register State Machine Signalse ------------------------------------------------------------------------------- -- SM_SIG_REGISTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- desc_fetch_req <= '0' ; -- else -- if (C_SG_INCLUDE_DESC_QUEUE = 0) then -- desc_fetch_req <= '1'; -- else -- desc_fetch_req <= desc_fetch_req_cmb ; -- end if; -- end if; -- end if; -- end process SM_SIG_REGISTER; desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else desc_fetch_req_cmb ; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For Indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & PAD_VALUE -- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro --'0' -- For Indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; -- s2mm_cmnd_data <= (others => '0'); -- Fetch SM issued a command write elsif(write_cmnd_cmb = '1')then s2mm_cmnd_wr <= '1'; -- s2mm_cmnd_data <= s2mm_desc_info -- & s2mm_desc_blength_v -- & s2mm_desc_blength_s -- & S2MM_CMD_RSVD -- & "0000" -- Cat IOC to CMD TAG -- & s2mm_desc_baddress -- & '1' -- Always reset DRE -- & '0' -- For indeterminate BTT mode do not set EOF -- & S2MM_CMD_DSA -- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 -- & s2mm_desc_blength; else s2mm_cmnd_wr <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; s2mm_cmnd_data <= s2mm_desc_info & s2mm_desc_blength_v & s2mm_desc_blength_s & S2MM_CMD_RSVD & "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG & s2mm_desc_baddress & '1' -- Always reset DRE & eof_micro -- For indeterminate BTT mode do not set EOF & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; end generate GEN_CMD_BTT_EQL_23; -- Drive unused output to zero s2mm_rxlength_clr <= '0'; end generate GEN_SM_FOR_NO_LENGTH; ------------------------------------------------------------------------------- -- Generate state machine and support logic for Using RX Length from Status -- Stream ------------------------------------------------------------------------------- -- this would not hold good for MCDMA GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate type SG_S2MM_STATE_TYPE is ( IDLE, FETCH_DESCRIPTOR, GET_RXLENGTH, CMPR_LENGTH, EXECUTE_XFER, WAIT_STATUS ); signal s2mm_cs : SG_S2MM_STATE_TYPE; signal s2mm_ns : SG_S2MM_STATE_TYPE; begin ------------------------------------------------------------------------------- -- S2MM Transfer State Machine ------------------------------------------------------------------------------- S2MM_MACHINE : process(s2mm_cs, s2mm_run_stop, desc_available, desc_update_done, -- desc_fetch_done, updt_pending, s2mm_rxlength_valid, rxlength_fetched, s2mm_cmnd_pending, zero_length_error, s2mm_stop, s2mm_desc_flush -- queue_more ) begin -- Default signal assignment desc_fetch_req_cmb <= '0'; s2mm_rxlength_clr_cmb <= '0'; write_cmnd_cmb <= '0'; s2mm_cmnd_idle <= '0'; s2mm_rxlength_set <= '0'; --rxlength_fetched_clr <= '0'; s2mm_ns <= s2mm_cs; case s2mm_cs is ------------------------------------------------------------------- when IDLE => if(s2mm_run_stop = '1' and desc_available = '1' -- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then and s2mm_stop = '0' and updt_pending = '0')then if (C_SG_INCLUDE_DESC_QUEUE = 0) then if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; else s2mm_ns <= FETCH_DESCRIPTOR; desc_fetch_req_cmb <= '1'; end if; else s2mm_cmnd_idle <= '1'; s2mm_ns <= IDLE; --FETCH_DESCRIPTOR; end if; ------------------------------------------------------------------- when FETCH_DESCRIPTOR => desc_fetch_req_cmb <= '0'; -- exit if error or descriptor flushed if(s2mm_desc_flush = '1')then s2mm_ns <= IDLE; -- Descriptor fetch complete else --if(desc_fetch_done = '1')then -- desc_fetch_req_cmb <= '0'; if(rxlength_fetched = '0')then s2mm_ns <= GET_RXLENGTH; else s2mm_ns <= CMPR_LENGTH; end if; -- else -- desc_fetch_req_cmb <= '1'; end if; ------------------------------------------------------------------- WHEN GET_RXLENGTH => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- Buffer length zero, do not compare lengths, execute -- command to force datamover to issue interror elsif(zero_length_error = '1')then s2mm_ns <= EXECUTE_XFER; elsif(s2mm_rxlength_valid = '1')then s2mm_rxlength_set <= '1'; s2mm_rxlength_clr_cmb <= '1'; s2mm_ns <= CMPR_LENGTH; else s2mm_ns <= GET_RXLENGTH; end if; ------------------------------------------------------------------- WHEN CMPR_LENGTH => s2mm_ns <= EXECUTE_XFER; ------------------------------------------------------------------- when EXECUTE_XFER => if(s2mm_stop = '1')then s2mm_ns <= IDLE; -- write new command if one is not already pending elsif(s2mm_cmnd_pending = '0')then write_cmnd_cmb <= '1'; -- If descriptor queuing enabled then -- do NOT need to wait for status if(C_SG_INCLUDE_DESC_QUEUE = 1)then s2mm_ns <= IDLE; -- No queuing therefore must wait for -- status before issuing next command else s2mm_ns <= WAIT_STATUS; end if; else s2mm_ns <= EXECUTE_XFER; end if; ------------------------------------------------------------------- -- coverage off when WAIT_STATUS => if(desc_update_done = '1' or s2mm_stop = '1')then s2mm_ns <= IDLE; else s2mm_ns <= WAIT_STATUS; end if; -- coverage on ------------------------------------------------------------------- -- coverage off when others => s2mm_ns <= IDLE; -- coverage on end case; end process S2MM_MACHINE; ------------------------------------------------------------------------------- -- Register state machine states ------------------------------------------------------------------------------- REGISTER_STATE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cs <= IDLE; else s2mm_cs <= s2mm_ns; end if; end if; end process REGISTER_STATE; ------------------------------------------------------------------------------- -- Register state machine signals ------------------------------------------------------------------------------- SM_SIG_REGISTER : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_req <= '0' ; s2mm_rxlength_clr <= '0' ; else if (C_SG_INCLUDE_DESC_QUEUE = 0) then desc_fetch_req <= '1'; else desc_fetch_req <= desc_fetch_req_cmb ; end if; s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb; end if; end if; end process SM_SIG_REGISTER; ------------------------------------------------------------------------------- -- Check for a ZERO value in descriptor buffer length. If there is -- then flag an error and skip waiting for valid rxlength. cmnd will -- get written to datamover with BTT=0 and datamover will flag dmaint error -- which will be logged in desc, reset required to clear error ------------------------------------------------------------------------------- REG_ALIGN_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then desc_fetch_done_d1 <= '0'; else desc_fetch_done_d1 <= desc_fetch_done; end if; end if; end process REG_ALIGN_DONE; ------------------------------------------------------------------------------- -- Zero length error detection - for determinate mode, detect early to prevent -- rxlength calcuation from first taking place. This will force a 0 BTT -- command to be issued to the datamover causing an internal error. ------------------------------------------------------------------------------- REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then zero_length_error <= '0'; elsif(desc_fetch_done_d1 = '1' and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then zero_length_error <= '1'; end if; end if; end process REG_ZERO_LNGTH_ERR; ------------------------------------------------------------------------------- -- Capture/Hold receive length from status stream. Also decrement length -- based on if received length is greater than descriptor buffer size. (i.e. is -- the case where multiple descriptors/buffers are used to describe one packet) ------------------------------------------------------------------------------- REG_RXLENGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then rxlength <= (others => '0'); -- If command register rxlength from status stream fifo elsif(s2mm_rxlength_set = '1')then rxlength <= s2mm_rxlength; -- On command write if current desc buffer size not greater -- than current rxlength then decrement rxlength in preperations -- for subsequent commands elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0)) - unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0))); end if; end if; end process REG_RXLENGTH; ------------------------------------------------------------------------------- -- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To' -- Received Length value ------------------------------------------------------------------------------- REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then blength_grtr_rxlength <= '0'; elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then blength_grtr_rxlength <= '1'; else blength_grtr_rxlength <= '0'; end if; end if; end process REG_BLENGTH_GRTR_RXLNGTH; ------------------------------------------------------------------------------- -- On command assert rxlength fetched flag indicating length grabbed from -- status stream fifo ------------------------------------------------------------------------------- RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then rxlength_fetched <= '0'; elsif(s2mm_rxlength_set = '1')then rxlength_fetched <= '1'; end if; end if; end process RXLENGTH_FTCHED_PROCESS; ------------------------------------------------------------------------------- -- Build DataMover command ------------------------------------------------------------------------------- -- If Bytes To Transfer (BTT) width less than 23, need to add pad GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0) := (others => '0'); begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '0' -- Cat. EOF=0 to CMD Tag & '0' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD -- Command Tag & '0' & '0' & '1' -- Cat. EOF=1 to CMD Tag & '1' -- Cat. IOC to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- Set EOF=1 & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & PAD_VALUE & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_LESS_23; -- If Bytes To Transfer (BTT) width equal 23, no required pad GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate begin -- When command by sm, drive command to s2mm_cmdsts_if GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s2mm_cmnd_wr <= '0'; s2mm_cmnd_data <= (others => '0'); s2mm_eof_set_i <= '0'; -- Current Desc Buffer will NOT hold entire rxlength of data therefore -- set EOF = based on Desc.EOF and pass buffer length for BTT elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '0' -- Cat. EOF='0' to CMD Tag & '0' -- Cat. IOC='0' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '0' -- Not End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & s2mm_desc_blength; s2mm_eof_set_i <= '0'; -- Current Desc Buffer will hold entire rxlength of data therefore -- set EOF = 1 and pass rxlength for BTT -- -- Note: change to mode where EOF generates IOC interrupt as -- opposed to a IOC bit in the descriptor negated need for an -- EOF and IOC tag. Given time, these two bits could be combined -- into 1. Associated logic in SG engine would also need to be -- modified as well as in s2mm_sg_if. elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then s2mm_cmnd_wr <= '1'; s2mm_cmnd_data <= s2mm_desc_info & ZERO_BUFFER & ZERO_BUFFER & S2MM_CMD_RSVD --& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG -- Command Tag & '0' & '0' & '1' -- Cat. EOF='1' to CMD Tag & '1' -- Cat. IOC='1' to CMD TAG -- Command & s2mm_desc_baddress & '1' -- Always reset DRE & '1' -- End of Frame & S2MM_CMD_DSA & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697 & rxlength; s2mm_eof_set_i <= '1'; else -- s2mm_cmnd_data <= (others => '0'); s2mm_cmnd_wr <= '0'; s2mm_eof_set_i <= '0'; end if; end if; end process GEN_DATAMOVER_CMND; end generate GEN_CMD_BTT_EQL_23; end generate GEN_SM_FOR_LENGTH; ------------------------------------------------------------------------------- -- Counter for keepting track of pending commands/status in primary datamover -- Use this to determine if primary datamover for s2mm is Idle. ------------------------------------------------------------------------------- -- Increment queue count for each command written if not occuring at -- same time a status from DM being updated to SG engine count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0' else '0'; -- Decrement queue count for each status update to SG engine if not occuring -- at same time as command being written to DM count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1' else '0'; -- keep track of number queue commands --CMD2STS_COUNTER : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then -- cmnds_queued <= (others => '0'); -- elsif(count_incr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1); -- elsif(count_decr = '1')then -- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1); -- end if; -- end if; -- end process CMD2STS_COUNTER; QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift <= (others => '0'); elsif(count_incr = '1')then cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1'; elsif(count_decr = '1')then cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1); end if; end if; end process CMD2STS_COUNTER1; end generate QUEUE_COUNT; NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate begin CMD2STS_COUNTER1 : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then cmnds_queued_shift (0) <= '0'; elsif(count_incr = '1')then cmnds_queued_shift (0) <= '1'; elsif(count_decr = '1')then cmnds_queued_shift (0) <= '0'; end if; end if; end process CMD2STS_COUNTER1; end generate NOQUEUE_COUNT; -- indicate idle when no more queued commands --s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000" -- else '0'; s2mm_sts_idle <= not cmnds_queued_shift(0); ------------------------------------------------------------------------------- -- Queue only the amount of commands that can be queued on descriptor update -- else lock up can occur. Note datamover command fifo depth is set to number -- of descriptors to queue. ------------------------------------------------------------------------------- --QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- if(m_axi_sg_aresetn = '0')then -- queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; -- else -- queue_more <= '0'; -- end if; -- end if; -- end process QUEUE_MORE_PROCESS; QUEUE_MORE_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then queue_more <= '0'; -- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then -- queue_more <= '1'; else queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0'; end if; end if; end process QUEUE_MORE_PROCESS; end implementation;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01:52:46 06/02/2011 -- Design Name: -- Module Name: sha256_e0 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sha256_e0 is Port ( d : in STD_LOGIC_VECTOR (31 downto 0); q : out STD_LOGIC_VECTOR (31 downto 0)); end sha256_e0; architecture Behavioral of sha256_e0 is begin q <= (d(1 downto 0) & d(31 downto 2)) xor (d(12 downto 0) & d(31 downto 13)) xor (d(21 downto 0) & d(31 downto 22)); end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01:52:46 06/02/2011 -- Design Name: -- Module Name: sha256_e0 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sha256_e0 is Port ( d : in STD_LOGIC_VECTOR (31 downto 0); q : out STD_LOGIC_VECTOR (31 downto 0)); end sha256_e0; architecture Behavioral of sha256_e0 is begin q <= (d(1 downto 0) & d(31 downto 2)) xor (d(12 downto 0) & d(31 downto 13)) xor (d(21 downto 0) & d(31 downto 22)); end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01:52:46 06/02/2011 -- Design Name: -- Module Name: sha256_e0 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sha256_e0 is Port ( d : in STD_LOGIC_VECTOR (31 downto 0); q : out STD_LOGIC_VECTOR (31 downto 0)); end sha256_e0; architecture Behavioral of sha256_e0 is begin q <= (d(1 downto 0) & d(31 downto 2)) xor (d(12 downto 0) & d(31 downto 13)) xor (d(21 downto 0) & d(31 downto 22)); end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 01:52:46 06/02/2011 -- Design Name: -- Module Name: sha256_e0 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sha256_e0 is Port ( d : in STD_LOGIC_VECTOR (31 downto 0); q : out STD_LOGIC_VECTOR (31 downto 0)); end sha256_e0; architecture Behavioral of sha256_e0 is begin q <= (d(1 downto 0) & d(31 downto 2)) xor (d(12 downto 0) & d(31 downto 13)) xor (d(21 downto 0) & d(31 downto 22)); end Behavioral;
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:user:vga_split_controller:1.0 -- IP Revision: 4 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY system_vga_split_controller_0_0 IS PORT ( rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clock : IN STD_LOGIC; hsync : IN STD_LOGIC; rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END system_vga_split_controller_0_0; ARCHITECTURE system_vga_split_controller_0_0_arch OF system_vga_split_controller_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT vga_split_controller IS GENERIC ( HALF_ROW : INTEGER ); PORT ( rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clock : IN STD_LOGIC; hsync : IN STD_LOGIC; rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT vga_split_controller; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "vga_split_controller,Vivado 2016.4"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_split_controller_0_0_arch : ARCHITECTURE IS "system_vga_split_controller_0_0,vga_split_controller,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "system_vga_split_controller_0_0,vga_split_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_split_controller,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,HALF_ROW=320}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clock: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; BEGIN U0 : vga_split_controller GENERIC MAP ( HALF_ROW => 320 ) PORT MAP ( rgb_0 => rgb_0, rgb_1 => rgb_1, clock => clock, hsync => hsync, rgb => rgb ); END system_vga_split_controller_0_0_arch;
-- NEED RESULT: ENT00010: Unassociated composite generics with static subtypes take on default expression failed ------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00010 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.1 (1) -- -- DESIGN UNIT ORDERING: -- -- ENT00010(ARCH00010) -- ENT00010_Test_Bench(ARCH00010_Test_Bench) -- -- REVISION HISTORY: -- -- 26-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES.all ; entity ENT00010 is generic ( i_bit_vector_1, i_bit_vector_2 : bit_vector := c_st_bit_vector_1 ; i_string_1, i_string_2 : string := c_st_string_1 ; i_t_rec1_1, i_t_rec1_2 : t_rec1 := c_st_rec1_1 ; i_st_rec1_1, i_st_rec1_2 : st_rec1 := c_st_rec1_1 ; i_t_rec2_1, i_t_rec2_2 : t_rec2 := c_st_rec2_1 ; i_st_rec2_1, i_st_rec2_2 : st_rec2 := c_st_rec2_1 ; i_t_rec3_1, i_t_rec3_2 : t_rec3 := c_st_rec3_1 ; i_st_rec3_1, i_st_rec3_2 : st_rec3 := c_st_rec3_1 ; i_t_arr1_1, i_t_arr1_2 : t_arr1 := c_st_arr1_1 ; i_st_arr1_1, i_st_arr1_2 : st_arr1 := c_st_arr1_1 ; i_t_arr2_1, i_t_arr2_2 : t_arr2 := c_st_arr2_1 ; i_st_arr2_1, i_st_arr2_2 : st_arr2 := c_st_arr2_1 ; i_t_arr3_1, i_t_arr3_2 : t_arr3 := c_st_arr3_1 ; i_st_arr3_1, i_st_arr3_2 : st_arr3 := c_st_arr3_1 ) ; begin end ENT00010 ; -- architecture ARCH00010 of ENT00010 is begin process variable correct : boolean := true ; begin correct := correct and i_bit_vector_1 = c_st_bit_vector_1 and i_bit_vector_2 = c_st_bit_vector_1 ; correct := correct and i_string_1 = c_st_string_1 and i_string_2 = c_st_string_1 ; correct := correct and i_t_rec1_1 = c_st_rec1_1 and i_t_rec1_2 = c_st_rec1_1 ; correct := correct and i_st_rec1_1 = c_st_rec1_1 and i_st_rec1_2 = c_st_rec1_1 ; correct := correct and i_t_rec2_1 = c_st_rec2_1 and i_t_rec2_2 = c_st_rec2_1 ; correct := correct and i_st_rec2_1 = c_st_rec2_1 and i_st_rec2_2 = c_st_rec2_1 ; correct := correct and i_t_rec3_1 = c_st_rec3_1 and i_t_rec3_2 = c_st_rec3_1 ; correct := correct and i_st_rec3_1 = c_st_rec3_1 and i_st_rec3_2 = c_st_rec3_1 ; correct := correct and i_t_arr1_1 = c_st_arr1_1 and i_t_arr1_2 = c_st_arr1_1 ; correct := correct and i_st_arr1_1 = c_st_arr1_1 and i_st_arr1_2 = c_st_arr1_1 ; correct := correct and i_t_arr2_1 = c_st_arr2_1 and i_t_arr2_2 = c_st_arr2_1 ; correct := correct and i_st_arr2_1 = c_st_arr2_1 and i_st_arr2_2 = c_st_arr2_1 ; correct := correct and i_t_arr3_1 = c_st_arr3_1 and i_t_arr3_2 = c_st_arr3_1 ; correct := correct and i_st_arr3_1 = c_st_arr3_1 and i_st_arr3_2 = c_st_arr3_1 ; test_report ( "ENT00010" , "Unassociated composite generics with static subtypes" & " take on default expression" , correct) ; wait ; end process ; end ARCH00010 ; -- entity ENT00010_Test_Bench is end ENT00010_Test_Bench ; -- architecture ARCH00010_Test_Bench of ENT00010_Test_Bench is begin L1: block component UUT end component ; for CIS1 : UUT use entity WORK.ENT00010 ( ARCH00010 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00010_Test_Bench ;
---------------------------------------------------------------------------------- -- Company: Trenz Electronic GmbH -- Engineer: Antti Lukats -- -- Create Date: 13.11.2013 09:58:03 -- Design Name: -- Module Name: SC0720 - Behavioral -- Project Name: -- Target Devices: TE0720 SoM -- Tool Versions: 2014.4 -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.4 -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity SC0720 is Port ( -- -- External I2C -- ext_sda_i : in std_logic; ext_sda_o : out std_logic; ext_sda_t : out std_logic; ext_scl_i : in std_logic; ext_scl_o : out std_logic; ext_scl_t : out std_logic; -- -- -- PHY_LED0: out std_logic; PHY_LED1: out std_logic; PHY_LED2: out std_logic; -- -- Connect to same name PL pin -- PL_pin_K16 : in std_logic; -- PUDC PL_pin_K19 : in std_logic; -- XCLK PL_pin_L16 : out std_logic; -- X1 SCL out PL_pin_M15 : in std_logic; -- X2 PL_pin_N15 : in std_logic; -- X3 PL_pin_P16 : in std_logic; -- X4 PL_pin_P22 : in std_logic; -- X5 SDA in PL_pin_K20 : out std_logic; -- X6 PL_pin_N22 : out std_logic; -- X7 SDA out -- -- Connect to EMIO I2C1 -- sda_i : out std_logic; sda_o : in std_logic; sda_t : in std_logic; scl_i : out std_logic; scl_o : in std_logic; scl_t : in std_logic ); end SC0720; architecture Behavioral of SC0720 is signal sda: std_logic; signal scl: std_logic; begin PL_pin_K20 <= '0'; -- TE0720-00 compat! -- I2C bus merger ext_sda_o <= sda_o; ext_sda_t <= sda_t; ext_scl_t <= scl_t; -- SDA readback from SC to I2C core sda_i <= PL_pin_P22 and ext_sda_i; -- SDA/SCL pass through to SC PL_pin_N22 <= sda; PL_pin_L16 <= scl; -- internal signals sda <= sda_o or sda_t; scl <= scl_o or scl_t; -- SCL feedback to I2C core scl_i <= scl; -- -- -- PHY_LED0 <= PL_pin_M15; PHY_LED1 <= PL_pin_N15; PHY_LED2 <= PL_pin_P16; end Behavioral;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc343.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c03s02b01x00p09n03i00343ent IS END c03s02b01x00p09n03i00343ent; ARCHITECTURE c03s02b01x00p09n03i00343arch OF c03s02b01x00p09n03i00343ent IS type M1 is array (1 to 4) of BIT; signal X1 : M1; BEGIN TESTING: PROCESS BEGIN X1(1) <= '0' after 10 ns; X1(2) <= '1' after 20 ns; X1(3) <= '1' after 30 ns; X1(4) <= '0' after 40 ns; -- No_failure_here wait for 50 ns; assert NOT(X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0') report "***PASSED TEST: c03s02b01x00p09n03i00343" severity NOTE; assert (X1(4)='0' and X1(3)='1' and X1(2)='1' and X1(1)='0') report "***FAILED TEST: c03s02b01x00p09n03i00343 - The values in the given index range are not the values that belong to the corresponding range." severity ERROR; wait; END PROCESS TESTING; END c03s02b01x00p09n03i00343arch;