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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pong is
port
(
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0)
);
end entity pong;
architecture rtl of pong is
begin
dout <= din(23 downto 16) & din(23 downto 16) & din(7 downto 0) & din(7 downto 0);
end architecture rtl;
|
-- ======================================================================
-- TDES encryption/decryption
-- algorithm according to FIPS 46-3 specification
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.des_pkg.all;
entity tdes is
port (
reset_i : in std_logic; -- async reset
clk_i : in std_logic; -- clock
mode_i : in std_logic; -- tdes-modus: 0 = encrypt, 1 = decrypt
key1_i : in std_logic_vector(0 to 63); -- key input
key2_i : in std_logic_vector(0 to 63); -- key input
key3_i : in std_logic_vector(0 to 63); -- key input
data_i : in std_logic_vector(0 to 63); -- data input
valid_i : in std_logic; -- input key/data valid flag
accept_o : out std_logic;
data_o : out std_logic_vector(0 to 63); -- data output
valid_o : out std_logic; -- output data valid flag
accept_i : in std_logic
);
end entity tdes;
architecture rtl of tdes is
signal s_mode : std_logic;
signal s_des1_validout : std_logic;
signal s_des2_validout : std_logic;
signal s_des2_acceptout : std_logic;
signal s_des3_acceptout : std_logic;
signal s_key1 : std_logic_vector(0 to 63);
signal s_key2 : std_logic_vector(0 to 63);
signal s_key3 : std_logic_vector(0 to 63);
signal s_des1_key : std_logic_vector(0 to 63);
signal s_des3_key : std_logic_vector(0 to 63);
signal s_des1_dataout : std_logic_vector(0 to 63);
signal s_des2_dataout : std_logic_vector(0 to 63);
begin
s_des1_key <= key1_i when mode_i = '0' else key3_i;
s_des3_key <= s_key3 when s_mode = '0' else s_key1;
inputregister : process (clk_i, reset_i) is
begin
if (reset_i = '0') then
s_mode <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
elsif(rising_edge(clk_i)) then
if (valid_i = '1' and accept_o = '1') then
s_mode <= mode_i;
s_key1 <= key1_i;
s_key2 <= key2_i;
s_key3 <= key3_i;
end if;
end if;
end process inputregister;
i1_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => mode_i,
key_i => s_des1_key,
data_i => data_i,
valid_i => valid_i,
accept_o => accept_o,
data_o => s_des1_dataout,
valid_o => s_des1_validout,
accept_i => s_des2_acceptout
);
i2_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => not s_mode,
key_i => s_key2,
data_i => s_des1_dataout,
valid_i => s_des1_validout,
accept_o => s_des2_acceptout,
data_o => s_des2_dataout,
valid_o => s_des2_validout,
accept_i => s_des3_acceptout
);
i3_des : des
port map (
reset_i => reset_i,
clk_i => clk_i,
mode_i => s_mode,
key_i => s_des3_key,
data_i => s_des2_dataout,
valid_i => s_des2_validout,
accept_o => s_des3_acceptout,
data_o => data_o,
valid_o => valid_o,
accept_i => accept_i
);
end architecture rtl;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32;
prefix_GENERIC_SUFFIX : integer := 20
);
port (
i_port1 : in std_logic := '0';
i_port2 : out std_logic :='1'
);
end entity FIFO;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.mechanical_systems.all;
entity inline_21a is
end entity inline_21a;
architecture test of inline_21a is
-- code from book
quantity d : displacement;
limit d : displacement with 0.001;
--
quantity drive_shaft_av, axle_av, wheel_av : angular_velocity;
--
limit drive_shaft_av, axle_av, wheel_av : angular_velocity with 0.01;
--
limit all : angular_velocity with 0.01;
--
quantity input, preamp_out, mixer_out, agc_out : voltage;
limit input, preamp_out : voltage with 1.0E-9;
limit others : voltage with 1.0E-7;
--
terminal bus1 : electrical_vector(1 to 8);
terminal bus2 : electrical_vector(1 to 8);
quantity v_bus across bus1 to bus2;
limit v_bus : voltage_vector with 1.0E-3;
-- end code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.mechanical_systems.all;
entity inline_21a is
end entity inline_21a;
architecture test of inline_21a is
-- code from book
quantity d : displacement;
limit d : displacement with 0.001;
--
quantity drive_shaft_av, axle_av, wheel_av : angular_velocity;
--
limit drive_shaft_av, axle_av, wheel_av : angular_velocity with 0.01;
--
limit all : angular_velocity with 0.01;
--
quantity input, preamp_out, mixer_out, agc_out : voltage;
limit input, preamp_out : voltage with 1.0E-9;
limit others : voltage with 1.0E-7;
--
terminal bus1 : electrical_vector(1 to 8);
terminal bus2 : electrical_vector(1 to 8);
quantity v_bus across bus1 to bus2;
limit v_bus : voltage_vector with 1.0E-3;
-- end code from book
begin
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed;
use ieee_proposed.electrical_systems.all;
use ieee_proposed.mechanical_systems.all;
entity inline_21a is
end entity inline_21a;
architecture test of inline_21a is
-- code from book
quantity d : displacement;
limit d : displacement with 0.001;
--
quantity drive_shaft_av, axle_av, wheel_av : angular_velocity;
--
limit drive_shaft_av, axle_av, wheel_av : angular_velocity with 0.01;
--
limit all : angular_velocity with 0.01;
--
quantity input, preamp_out, mixer_out, agc_out : voltage;
limit input, preamp_out : voltage with 1.0E-9;
limit others : voltage with 1.0E-7;
--
terminal bus1 : electrical_vector(1 to 8);
terminal bus2 : electrical_vector(1 to 8);
quantity v_bus across bus1 to bus2;
limit v_bus : voltage_vector with 1.0E-3;
-- end code from book
begin
end architecture test;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity RegistersPipeline is
port(
RR1, RR2, WR: in std_logic_vector(4 downto 0);
WD: in std_logic_vector(31 downto 0);
RegWrite: in std_logic;
RD1, RD2: out std_logic_vector(31 downto 0)
);
end RegistersPipeline;
Architecture Structural of RegistersPipeline is
type mem_array is array(0 to 31) of std_logic_vector(31 downto 0);
signal reg_mem: mem_array := (
X"00000000", --0 $zero (constant value 0)
X"00000000", -- $at (reserved for the assembler)
X"00000000", -- $v0 (value for results and expression)
X"00000000", -- $v1
X"00000000", -- $a0 (arguments)
X"00000000", --5 $a1
X"00000000", -- $a2
X"00000000", -- $a3
X"00000000", -- $t0 (temporaries)
X"00000004", -- $t1
X"00000004", --10 $t2
X"00000000", -- $t3
X"00000000", -- $t4
X"00000000", -- $t5
X"00000000", -- $t6
X"00000000", --15 $t7
X"00000000", -- $s0 (saved)
X"00000000", -- $s1
X"00000000", -- $s2
X"00000000", -- $s3
X"0000000E", --20 $s4
X"00000005", -- $s5
X"00000008", -- $s6
X"00000003", -- $s7
X"00000000", -- $t8 (more temporaries)
X"00000000", --25 $t9
X"00000000", -- $k0 (reserved for the operating system)
X"00000000", -- $k1
X"00000000", -- $gp (global pointer)
X"00000000", -- $sp (stack pointer)
X"00000000", --30 $fp (frame pointer)
X"00000000" -- $ra (return address)
);
signal temp_data: std_logic_vector(31 downto 0) := X"00000000";
begin
RD1 <= reg_mem(to_integer(unsigned(RR1)));
RD2 <= reg_mem(to_integer(unsigned(RR2)));
process(WD, WR, RegWrite)
begin
if RegWrite = '1' then
reg_mem(to_integer(unsigned(WR))) <= WD;
end if;
end process;
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc905.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00905ent IS
constant C : INTEGER := C; -- Failure_here
-- entity is not visible until end of declaration
END c10s03b00x00p05n01i00905ent;
ARCHITECTURE c10s03b00x00p05n01i00905arch OF c10s03b00x00p05n01i00905ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00905 - Declaration is not visible until the end of the declaration.
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00905arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc905.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00905ent IS
constant C : INTEGER := C; -- Failure_here
-- entity is not visible until end of declaration
END c10s03b00x00p05n01i00905ent;
ARCHITECTURE c10s03b00x00p05n01i00905arch OF c10s03b00x00p05n01i00905ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00905 - Declaration is not visible until the end of the declaration.
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00905arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc905.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00905ent IS
constant C : INTEGER := C; -- Failure_here
-- entity is not visible until end of declaration
END c10s03b00x00p05n01i00905ent;
ARCHITECTURE c10s03b00x00p05n01i00905arch OF c10s03b00x00p05n01i00905ent IS
BEGIN
TESTING: PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00905 - Declaration is not visible until the end of the declaration.
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00905arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: arith
-- File: arith.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Declaration of mul/div components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package arith is
type div32_in_type is record
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
op1 : std_logic_vector(32 downto 0); -- operand 1 (LSB divident)
op2 : std_logic_vector(32 downto 0); -- operand 2 (divisor)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul32_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
acc : std_logic_vector(39 downto 0);
--y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
--asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul32_out_type is record
ready : std_logic;
nready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
component div32
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
divi : in div32_in_type;
divo : out div32_out_type
);
end component;
component mul32
generic (
tech : integer := 0;
multype : integer := 0;
pipe : integer := 0;
mac : integer := 0;
arch : integer range 0 to 3 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
holdn : in std_ulogic;
muli : in mul32_in_type;
mulo : out mul32_out_type
);
end component;
function smult ( a, b : in std_logic_vector) return std_logic_vector;
function umult ( a, b : in std_logic_vector) return std_logic_vector;
end;
package body arith is
function smult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : signed (a'length-1 downto 0);
variable sb : signed (b'length-1 downto 0);
variable sc : signed ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := signed(a); sb := signed(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
function umult ( a, b : in std_logic_vector) return std_logic_vector is
variable sa : unsigned (a'length-1 downto 0);
variable sb : unsigned (b'length-1 downto 0);
variable sc : unsigned ((a'length + b'length) -1 downto 0);
variable res : std_logic_vector ((a'length + b'length) -1 downto 0);
begin
sa := unsigned(a); sb := unsigned(b);
-- pragma translate_off
if is_x(a) or is_x(b) then
sc := (others => 'X');
else
-- pragma translate_on
sc := sa * sb;
-- pragma translate_off
end if;
-- pragma translate_on
res := std_logic_vector(sc);
return(res);
end;
end;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
package adaptations_pkg is
constant C_ALERT_FILE_NAME : string := "_Alert.txt";
constant C_LOG_FILE_NAME : string := "_Log.txt";
constant C_SHOW_UVVM_UTILITY_LIBRARY_INFO : boolean := true; -- Set this to false when you no longer need the initial info
constant C_SHOW_UVVM_UTILITY_LIBRARY_RELEASE_INFO : boolean := true; -- Set this to false when you no longer need the release info
-------------------------------------------------------------------------------
-- Log format
-------------------------------------------------------------------------------
--UVVM: [<ID>] <time> <Scope> Msg
--PPPPPPPPIIIIII TTTTTTTT SSSSSSSSSSSSSS MMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMMM
constant C_LOG_PREFIX : string := "UVVM: "; -- Note: ': ' is recommended as final characters
constant C_LOG_PREFIX_WIDTH : natural := C_LOG_PREFIX'length;
constant C_LOG_MSG_ID_WIDTH : natural := 24;
constant C_LOG_TIME_WIDTH : natural := 16; -- 3 chars used for unit eg. " ns"
constant C_LOG_TIME_BASE : time := ns; -- Unit in which time is shown in log (ns | ps)
constant C_LOG_TIME_DECIMALS : natural := 1; -- Decimals to show for given C_LOG_TIME_BASE
constant C_LOG_SCOPE_WIDTH : natural := 20;
constant C_LOG_LINE_WIDTH : natural := 175;
constant C_LOG_INFO_WIDTH : natural := C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH;
constant C_USE_BACKSLASH_N_AS_LF : boolean := true; -- If true interprets '\n' as Line feed
constant C_USE_BACKSLASH_R_AS_LF : boolean := true; -- If true, inserts an empty line if '\r'
-- is the first character of the string.
-- All others '\r' will be printed as is.
constant C_SINGLE_LINE_ALERT : boolean := false; -- If true prints alerts on a single line.
constant C_SINGLE_LINE_LOG : boolean := false; -- If true prints log messages on a single line.
constant C_TB_SCOPE_DEFAULT : string := "TB seq."; -- Default scope in test sequencer
constant C_LOG_TIME_TRUNC_WARNING : boolean := true; -- Yields a single TB_WARNING if time stamp truncated. Otherwise none
constant C_SHOW_LOG_ID : boolean := true; -- This constant has replaced the global_show_log_id
constant C_SHOW_LOG_SCOPE : boolean := true; -- This constant has replaced the global_show_log_scope
constant C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME : boolean := false;
shared variable shared_default_log_destination : t_log_destination := CONSOLE_AND_LOG;
-------------------------------------------------------------------------------
-- Verbosity control
-- NOTE: Do not enter new IDs without proper evaluation:
-- 1. Is it - or could it be covered by an existing ID
-- 2. Could it be combined with other needs for a more general new ID
-- Feel free to suggest new ID for future versions of UVVM Utility Library ([email protected])
-------------------------------------------------------------------------------
type t_msg_id is (
-- Bitvis utility methods
NO_ID, -- Used as default prior to setting actual ID when transfering ID as a field in a record
ID_UTIL_BURIED, -- Used for buried log messages where msg and scope cannot be modified from outside
ID_BITVIS_DEBUG, -- Bitvis internal ID used for UVVM debugging
ID_UTIL_SETUP, -- Used for Utility setup
ID_LOG_MSG_CTRL, -- Used inside Utility library only - when enabling/disabling msg IDs.
ID_ALERT_CTRL, -- Used inside Utility library only - when setting IGNORE or REGARD on various alerts.
ID_NEVER, -- Used for avoiding log entry. Cannot be enabled.
ID_FINISH_OR_STOP, -- Used when terminating the complete simulation - independent of why
ID_CLOCK_GEN, -- Used for logging when clock generators are enabled or disabled
ID_GEN_PULSE, -- Used for logging when a gen_pulse procedure starts pulsing a signal
ID_BLOCKING, -- Used for logging when using synchronisation flags
-- General
ID_POS_ACK, -- To write a positive acknowledge on a check
-- Directly inside test sequencers
ID_LOG_HDR, -- ONLY allowed in test sequencer, Log section headers
ID_LOG_HDR_LARGE, -- ONLY allowed in test sequencer, Large log section headers
ID_LOG_HDR_XL, -- ONLY allowed in test sequencer, Extra large log section headers
ID_SEQUENCER, -- ONLY allowed in test sequencer, Normal log (not log headers)
ID_SEQUENCER_SUB, -- ONLY allowed in test sequencer, Subprograms defined in sequencer
-- BFMs
ID_BFM, -- Used inside a BFM (to log BFM access)
ID_BFM_WAIT, -- Used inside a BFM to indicate that it is waiting for something (e.g. for ready)
ID_BFM_POLL, -- Used inside a BFM when polling until reading a given value. I.e. to show all reads until expected value found (e.g. for sbi_poll_until())
ID_BFM_POLL_SUMMARY, -- Used inside a BFM when showing the summary of data that has been received while waiting for expected data.
ID_TERMINATE_CMD, -- Typically used inside a loop in a procedure to end the loop (e.g. for sbi_poll_until() or any looped generation of random stimuli
-- Packet related data Ids with three levels of granularity, for differentiating between frames, packets and segments.
-- Segment Ids, finest granularity of packet data
ID_SEGMENT_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_SEGMENT_COMPLETE, -- Notify that a packet has been transmitted or received
ID_SEGMENT_HDR, -- AS ID_SEGMENT_COMPLETE, but also writes header info
ID_SEGMENT_DATA, -- AS ID_SEGMENT_COMPLETE, but also writes packet data (could be huge)
-- Packet Ids, medium granularity of packet data
ID_PACKET_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_PACKET_COMPLETE, -- Notify that a packet has been transmitted or received
ID_PACKET_HDR, -- AS ID_PACKET_COMPLETED, but also writes header info
ID_PACKET_DATA, -- AS ID_PACKET_COMPLETED, but also writes packet data (could be huge)
-- Frame Ids, roughest granularity of packet data
ID_FRAME_INITIATE, -- Notify that a packet is about to be transmitted or received
ID_FRAME_COMPLETE, -- Notify that a packet has been transmitted or received
ID_FRAME_HDR, -- AS ID_FRAME_COMPLETE, but also writes header info
ID_FRAME_DATA, -- AS ID_FRAME_COMPLETE, but also writes packet data (could be huge)
-- OSVVM Ids
ID_COVERAGE_MAKEBIN, -- Log messages from MakeBin (IllegalBin/GenBin/IgnoreBin)
ID_COVERAGE_ADDBIN, -- Log messages from AddBin/AddCross
ID_COVERAGE_ICOVER, -- ICover logging, NB: Very low level debugging. Can result in large amount of data.
ID_COVERAGE_CONFIG, -- Logging of configuration in the coverage package
ID_COVERAGE_SUMMARY, -- Report logging : Summary of coverage, with both covered bins and holes
ID_COVERAGE_HOLES, -- Report logging : Holes only
-- Distributed command systems
ID_UVVM_SEND_CMD,
ID_UVVM_CMD_ACK,
ID_UVVM_CMD_RESULT,
ID_CMD_INTERPRETER, -- Message from VVC interpreter about correctly received and queued/issued command
ID_CMD_INTERPRETER_WAIT, -- Message from VVC interpreter that it is actively waiting for a command
ID_IMMEDIATE_CMD, -- Message from VVC interpreter that an IMMEDIATE command has been executed
ID_IMMEDIATE_CMD_WAIT, -- Message from VVC interpreter that an IMMEDIATE command is waiting for command to complete
ID_CMD_EXECUTOR, -- Message from VVC executor about correctly received command - prior to actual execution
ID_CMD_EXECUTOR_WAIT, -- Message from VVC executor that it is actively waiting for a command
ID_INSERTED_DELAY, -- Message from VVC executor that it is waiting a given delay
-- Distributed data
ID_UVVM_DATA_QUEUE, -- Information about UVVM data FIFO/stack (initialization, put, get, etc)
-- VVC system
ID_CONSTRUCTOR, -- Constructor message from VVCs (or other components/process when needed)
ID_CONSTRUCTOR_SUB, -- Constructor message for lower level constructor messages (like Queue-information and other limitations)
-- Special purpose - Not really IDs
ALL_MESSAGES -- Applies to ALL message ID apart from ID_NEVER
);
type t_msg_id_panel is array (t_msg_id'left to t_msg_id'right) of t_enabled;
-- Default message Id panel to be used for all message Id panels, except:
-- - VVC message Id panels, see constant C_VVC_MSG_ID_PANEL_DEFAULT
constant C_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
ID_BITVIS_DEBUG => DISABLED,
ID_COVERAGE_MAKEBIN => DISABLED,
ID_COVERAGE_ADDBIN => DISABLED,
ID_COVERAGE_ICOVER => DISABLED,
others => ENABLED
);
-- If false, OSVVM uses the default message id panel. If true, it uses a separate message id panel.
constant C_USE_LOCAL_OSVVM_MSG_ID_PANELS : boolean := TRUE;
type t_msg_id_indent is array (t_msg_id'left to t_msg_id'right) of string(1 to 4);
constant C_MSG_ID_INDENT : t_msg_id_indent := (
ID_IMMEDIATE_CMD_WAIT => " ..",
ID_CMD_INTERPRETER => " " & NUL & NUL,
ID_CMD_INTERPRETER_WAIT => " ..",
ID_CMD_EXECUTOR => " " & NUL & NUL,
ID_CMD_EXECUTOR_WAIT => " ..",
ID_UVVM_SEND_CMD => "->" & NUL & NUL,
ID_UVVM_CMD_ACK => " ",
others => "" & NUL & NUL & NUL & NUL
);
constant C_MSG_DELIMITER : character := ''';
-------------------------------------------------------------------------
-- Alert counters
-------------------------------------------------------------------------
-- Default values. These can be overwritten in each sequencer by using
-- set_alert_attention or set_alert_stop_limit (see quick ref).
constant C_DEFAULT_ALERT_ATTENTION : t_alert_attention := (others => REGARD);
-- 0 = Never stop
constant C_DEFAULT_STOP_LIMIT : t_alert_counters := (note to manual_check => 0,
others => 1);
-------------------------------------------------------------------------
-- Hierarchical alerts
-------------------------------------------------------------------------
constant C_ENABLE_HIERARCHICAL_ALERTS : boolean := false;
constant C_BASE_HIERARCHY_LEVEL : string(1 to 5) := "Total";
constant C_EMPTY_NODE : t_hierarchy_node := (" ",
(others => (others => 0)),
(others => 0),
(others => true));
-------------------------------------------------------------------------
-- Deprecate
-------------------------------------------------------------------------
-- These values are used to indicate outdated sub-programs
constant C_DEPRECATE_SETTING : t_deprecate_setting := DEPRECATE_ONCE;
shared variable deprecated_subprogram_list : t_deprecate_list := (others=>(others => ' '));
------------------------------------------------------------------------
-- UVVM VVC Framework adaptations
------------------------------------------------------------------------
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
signal global_show_msg_for_uvvm_cmd : boolean := true;
constant C_CMD_QUEUE_COUNT_MAX : natural := 20; -- (VVC Command queue) May be overwritten for dedicated VVC
constant C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_CMD_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_RESULT_QUEUE_COUNT_MAX : natural := 20; -- (VVC Result queue) May be overwritten for dedicated VVC
constant C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
constant C_RESULT_QUEUE_COUNT_THRESHOLD : natural := 18;
constant C_MAX_VVC_INSTANCE_NUM : natural := 8;
constant C_MAX_NUM_SEQUENCERS : natural := 10; -- Max number of sequencers
constant C_TOTAL_NUMBER_OF_BITS_IN_DATA_BUFFER : natural := 2048;
constant C_NUMBER_OF_DATA_BUFFERS : natural := 10;
-- Default message Id panel intended for use in the VVCs
constant C_VVC_MSG_ID_PANEL_DEFAULT : t_msg_id_panel := (
ID_NEVER => DISABLED,
ID_UTIL_BURIED => DISABLED,
others => ENABLED
);
type t_data_source is ( -- May add more types of random ++ later
NA,
FROM_BUFFER,
RANDOM,
RANDOM_TO_BUFFER
);
type t_error_injection is ( -- May add more controlled error injection later
NA,
RANDOM_BIT_ERROR,
RANDOM_DATA_ERROR,
RANDOM_ADDRESS_ERROR
);
constant C_CMD_IDX_PREFIX : string := " [";
constant C_CMD_IDX_SUFFIX : string := "]";
type t_channel is ( -- NOTE: Add more types of channels when needed for a VVC
NA, -- When channel is not relevant
ALL_CHANNELS, -- When command shall be received by all channels
RX,
TX);
constant C_VVCT_ALL_INSTANCES : integer := -2;
constant C_NUM_SEMAPHORE_LOCK_TRIES : natural := 500;
end package adaptations_pkg;
package body adaptations_pkg is
end package body adaptations_pkg;
|
-- VHDL projekt - Hodiny + budík na VGA výstup pomocí zaøízení FitKit 2.0
-- Aplikace po nahrání do FitKitu zobrazuje na VGA výstupu hodiny.
-- Ty na zaèátku poèítají od 00:00:00. Hodiny lze nastavit pomocí klávesnice na FitKitu.
-- Aplikace té umí funkci budíku (pouze vizuální). Po nastavení èasu pro budík kontroluje,
-- zda se ji shoduje aktuální èas s tím budíkovým. Pokud ano, hodiny blikají s periodou 0.5 s.
-- Ovládání:
-- # - vstup do nastavení hodin, potvrzení nastavení hodin, potvrzení nastavení budíku
-- * - vstup do nastavení budíku
-- A - zapnutí/vypnutí budíku (indikace teèkou nalevo od hodin) + vypnutí blikání budíku
-- 0-9 - nastavení konkrétní hodnoty na zvýraznìné pozici pøi editaci
-- Aplikace byla vytvoøena jako semestrální projekt do pøedmìtu IVH na FIT VUT, 2012/2013.
-- Náleí k ní i dokumentace s podrobnìjími informacemi.
-- Datum vytvoøení: 1.5.2013
-- Datum poslední editace: 26.5.2013
-- Vytvoøili:
-- Michal Kozubík, xkozub03, student 1BIA FIT VUT Brno, [email protected]
-- Marek Hurta, xhurta01, student 1BIA FIT VUT Brno, [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.vga_controller_cfg.all;
use work.clkgen_cfg.all;
entity fsm is
port(
CLK : in std_logic;
RESET : in std_logic;
KEY : in std_logic_vector(15 downto 0);
value : out integer range 0 to 15;
CNTS : out std_logic_vector(13 downto 0)
);
end entity fsm;
architecture main of tlv_pc_ifc is
-- perioda pro èítaè, který pøi pouitém CLK generuje signál s periodou 1 sekunda
constant period: integer := 7372800;
-- vektor pro data z klávesnice
signal kb_data_out: std_logic_vector(15 downto 0);
-- hodnoty jednotlivých èíslic hodin a budíku
subtype small is integer range 0 to 10;
signal cnt: integer := 0;
signal cnt_sj: small := 0;
signal cnt_mj: small := 0;
signal cnt_hj: small := 0;
signal cnt_sd: small := 0;
signal cnt_md: small := 0;
signal cnt_hd: small := 0;
signal al_sj: small := 0;
signal al_sd: small := 0;
signal al_mj: small := 0;
signal al_md: small := 0;
signal al_hj: small := 0;
signal al_hd: small := 0;
-- signaly znaèící vygenerování sekundy, minuty, hodiny
signal sec : std_logic := '0';
signal min: std_logic := '0';
signal hour: std_logic := '0';
-- hodnota zmáèknuté klávesy pøijata z koneèného automatu
signal value: integer range 0 to 15 := 0;
-- signály pro identifikaci práce koneèného automatu (ve které fázi se nachází)
-- CNTS(0) = '1' => zápis do desítkové pozice hodin (cnt_hd nebo al_hd)
-- CNTS(1) = '1' => zápis do jednotkové pozice hodin (cnt_hj nebo al_hj)
-- CNTS(2) = '1' => zápis do desítkové pozice minut (cnt_md nebo al_md)
-- CNTS(3) = '1' => zápis do jednotkové pozice minut (cnt_mj nebo al_mj)
-- CNTS(4) = '1' => zápis do desítkové pozice sekund (cnt_sd nebo al_sd)
-- CNTS(5) = '1' => zápis do jednotkové pozice sekund (cnt_sj nebo al_sj)
-- CNTS(6) = '1' => èekání na zápis na desítkovou pozici hodin (zvýraznìna první pozice na VGA výstupu)
-- CNTS(7) = '1' => èekání na zápis na jednotkovou pozici hodin (zvýraznìna druhá pozice na VGA výstupu)
-- CNTS(8) = '1' => èekání na zápis na desítkovou pozici minut (zvýraznìna tøetí pozice na VGA výstupu)
-- CNTS(9) = '1' => èekání na zápis na jednotkovou pozici minut (zvýraznìna ètvrtá pozice na VGA výstupu)
-- CNTS(10) = '1' => èekání na zápis na desítkovou pozici sekund (zvýraznìna pátá pozice na VGA výstupu)
-- CNTS(11) = '1' => èekání na zápis na jednotkovou pozici sekund (zvýraznìna está pozice na VGA výstupu)
-- CNTS(12) => '0' => probíhá nastavování hodin, '1' => probíhá nastavování budíku
-- CNTS(13) => '0' => budík je neaktivní, '1' => budík je aktivován
signal CNTS: std_logic_vector(13 downto 0) := (others => '0');
-- BLINK(0) => blikání hodin ('0' viditelné na výstupu, '1' výstup prázdný)
-- BLINK(1) = '1' => blikání hodin zapnuto
signal BLINK: std_logic_vector(1 downto 0) := (others => '1');
-- signály potøebné pro práci s VGA výstupem
signal vga_mode: std_logic_vector (60 downto 0);
signal red: std_logic_vector (2 downto 0);
signal green: std_logic_vector (2 downto 0);
signal blue: std_logic_vector (2 downto 0);
signal rgb_sj: std_logic_vector (8 downto 0);
signal rgb_mj: std_logic_vector (8 downto 0);
signal rgb_hj: std_logic_vector (8 downto 0);
signal rgb_sd: std_logic_vector (8 downto 0);
signal rgb_md: std_logic_vector (8 downto 0);
signal rgb_hd: std_logic_vector (8 downto 0);
signal rgbf: std_logic_vector (8 downto 0);
signal vga_row: std_logic_vector (11 downto 0);
signal vga_col: std_logic_vector (11 downto 0);
signal rom_col: integer range 0 to 8;
signal sec_wrj: std_logic := '0';
signal min_wrj: std_logic := '0';
signal hr_wrj: std_logic := '0';
signal sec_wrd: std_logic := '0';
signal min_wrd: std_logic := '0';
signal hr_wrd: std_logic := '0';
-- ROM pamì s uloenými èíslicemi 0 - 9
type pamet is array(0 to 8*10-1) of std_logic_vector (0 to 7);
signal rom_digit: pamet := ("00000000", -- 0
"00111100",
"00100100",
"00100100",
"00100100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 1
"00000100",
"00000100",
"00000100",
"00000100",
"00000100",
"00000000",
(others => '0'),
"00000000", -- 2
"00111100",
"00000100",
"00111100",
"00100000",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 3
"00111100",
"00000100",
"00111100",
"00000100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 4
"00100100",
"00100100",
"00111100",
"00000100",
"00000100",
"00000000",
(others => '0'),
"00000000", -- 5
"00111100",
"00100000",
"00111100",
"00000100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 6
"00111100",
"00100000",
"00111100",
"00100100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 7
"00111100",
"00000100",
"00000100",
"00000100",
"00000100",
"00000000",
(others => '0'),
"00000000", -- 8
"00111100",
"00100100",
"00111100",
"00100100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 9
"00111100",
"00100100",
"00111100",
"00000100",
"00111100",
"00000000",
(others => '0'));
begin
-- namapování entity pro práci s klávesnicí na FitKitu
kbc_u : entity work.keyboard_controller_high
-- pragma translate off
generic map(
READ_INTERVAL => 32
)
-- pragma translate on
port map(
CLK => SMCLK,
RST => RESET,
DATA_OUT => kb_data_out,
KB_KIN => KIN,
KB_KOUT => KOUT
);
-- namapování entity pro práci s koneèným automatem
fistma: entity fsm
port map(
CLK => SMCLK,
RESET => RESET,
KEY => kb_data_out,
value => value,
CNTS => CNTS
);
-- namapování entity pro práci s VGA výstupem
vga: entity work.vga_controller(arch_vga_controller)
port map(
CLK => CLK,
RST => RESET,
ENABLE => '1',
MODE => vga_mode,
DATA_RED => red,
DATA_GREEN => green,
DATA_BLUE => blue,
ADDR_COLUMN => vga_col,
ADDR_ROW => vga_row,
VGA_RED => RED_V,
VGA_GREEN => GREEN_V,
VGA_BLUE => BLUE_V,
VGA_HSYNC => HSYNC_V,
VGA_VSYNC => VSYNC_V
);
setmode(r640x480x60, vga_mode);
rom_col <= conv_integer(vga_col(5 downto 3));
-- zjitìní pro kadý counter jestli se pro nìj v pamìtí nachází '1' nebo '0'
-- také se rozhoduje, jestli se zobrazují èíslice hodin nebo budíku (pøo jeho nastavování)
sec_wrj <= rom_digit(al_sj*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_sj*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
sec_wrd <= rom_digit(al_sd*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_sd*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
min_wrj <= rom_digit(al_mj*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_mj*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
min_wrd <= rom_digit(al_md*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_md*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
hr_wrj <= rom_digit(al_hj*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_hj*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
hr_wrd <= rom_digit(al_hd*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_hd*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
-- nastavení barev pro vechny zjitìné hodnoty
-- aktuálnì nastavovaná èíslice je zvýraznìna modøe
-- klasické hodinové èíslice jsou zelené a èíslice budíku fialové
rgb_sj <= "000"&"101"&"000" when (sec_wrj = '1') and (CNTS(11) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (sec_wrj = '1') and (CNTS(11) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (sec_wrj = '1') and (CNTS(11) = '1') else
"000"&"000"&"000";
rgb_sd <= "000"&"101"&"000" when (sec_wrd = '1') and (CNTS(10) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (sec_wrd = '1') and (CNTS(10) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (sec_wrd = '1') and (CNTS(10) = '1') else
"000"&"000"&"000";
rgb_mj <= "000"&"101"&"000" when (min_wrj = '1') and (CNTS(9) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (min_wrj = '1') and (CNTS(9) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (min_wrj = '1') and (CNTS(9) = '1') else
"000"&"000"&"000";
rgb_md <= "000"&"101"&"000" when (min_wrd = '1') and (CNTS(8) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (min_wrd = '1') and (CNTS(8) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (min_wrd = '1') and (CNTS(8) = '1') else
"000"&"000"&"000";
rgb_hj <= "000"&"101"&"000" when (hr_wrj = '1') and (CNTS(7) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (hr_wrj = '1') and (CNTS(7) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (hr_wrj = '1') and (CNTS(7) = '1') else
"000"&"000"&"000";
rgb_hd <= "000"&"101"&"000" when (hr_wrd = '1') and (CNTS(6) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (hr_wrd = '1') and (CNTS(6) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (hr_wrd = '1') and (CNTS(6) = '1') else
"000"&"000"&"000";
-- pøi aktivním probliknutí se nezobrazí nic
rgbf <= "000"&"000"&"000" when BLINK(0) = '1' else
-- Tecka indikujici nastaveni alarmu:
"000"&"101"&"101" when (vga_row(11 downto 2) = "0000111011") and ((vga_col(9 downto 2)= "00011111")) and (CNTS(13) = '1') else
-- Dvojtecka mezi minutami a sekundami:
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011101") and ((vga_col(8 downto 2) = "1011111")) else
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011001") and ((vga_col(8 downto 2) = "1011111")) else
-- Dvojtecka mezi Hodinami a minutami:
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011101") and ((vga_col(8 downto 2) = "0111111")) else
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011001") and ((vga_col(8 downto 2) = "0111111")) else
-- Samotne cislice dle pozice na výstupu:
rgb_sj when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "111")) else
rgb_sd when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "110")) else
rgb_mj when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "101")) else
rgb_md when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "100")) else
rgb_hj when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "011")) else
rgb_hd when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "010")) else
"000"&"000"&"000";
red <= rgbf(8 downto 6);
green <= rgbf(5 downto 3);
blue <= rgbf(2 downto 0);
-- GENERATOR SEKUNDOVEHO SIGNALU
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
sec <= '0';
-- nastavení blikání pøi aktivovaném budíku a pøi shodì hodin a minut
-- hodiny blikají minutu a nebo do zmáèknutí '#', '*' nebo 'A'
if ((cnt = period -1) or (cnt = period / 2)) then
if ((CNTS(13) = '1') and (cnt_hd = al_hd) and (cnt_hj = al_hj) and (cnt_md = al_md) and (cnt_mj = al_mj)) then
BLINK(1) <= '1';
else
BLINK(1) <= '0';
end if;
if (CNTS(6) = '1') then
BLINK(1) <= '0';
BLINK(0) <= '0';
elsif (BLINK(1) = '1') then
BLINK(0) <= not BLINK(0);
else
BLINK(0) <= '0';
end if;
end if;
if (cnt = period -1) then
cnt <= 0;
sec <= '1';
else
cnt <= cnt + 1;
end if;
end if;
end process;
-- GENERATOR MINUTOVEHO SIGNALU + nastaveni sekundovych pozic
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
min <= '0';
if (CNTS(4) = '1') then
if (CNTS(12) = '1') then
al_sd <= value;
else
cnt_sd <= value;
end if;
elsif (CNTS(5) = '1') then
if (CNTS(12) = '1') then
al_sj <= value;
else
cnt_sj <= value;
end if;
end if;
if (sec = '1') then
if (cnt_sj = 9) and (cnt_sd = 5) then
cnt_sj <= 0;
cnt_sd <= 0;
min <= '1';
else
cnt_sj <= cnt_sj +1;
if (cnt_sj = 9) then
cnt_sj <= 0;
cnt_sd <= cnt_sd + 1;
end if;
end if;
end if;
end if;
end process;
-- GENERATOR HODINOVEHO SIGNALU + nastaveni minutových pozic
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
hour <= '0';
if (CNTS(2) = '1') then
if (CNTS(12) = '1') then
al_md <= value;
else
cnt_md <= value;
end if;
elsif (CNTS(3) = '1') then
if (CNTS(12) = '1') then
al_mj <= value;
else
cnt_mj <= value;
end if;
end if;
if (min = '1') then
if (cnt_mj = 9) and (cnt_md = 5) then
cnt_mj <= 0;
cnt_md <= 0;
hour <= '1';
else
cnt_mj <= cnt_mj + 1;
if (cnt_mj = 9) then
cnt_mj <= 0;
cnt_md <= cnt_md + 1;
end if;
end if;
end if;
end if;
end process;
-- POCITADLO HODIN + nastaveni hodinových pozic
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
if (CNTS(0) = '1') then
if (CNTS(12) = '1') then
al_hd <= value;
else
cnt_hd <= value;
end if;
elsif (CNTS(1) = '1') then
if (CNTS(12) = '1') then
al_hj <= value;
else
cnt_hj <= value;
end if;
end if;
if (hour = '1') then
if (cnt_hj = 3) and (cnt_hd = 2) then
cnt_hj <= 0;
cnt_hd <= 0;
else
cnt_hj <= cnt_hj + 1;
if (cnt_hj = 9) then
cnt_hj <= 0;
cnt_hd <= cnt_hd + 1;
end if;
end if;
end if;
end if;
end process;
end main;
-- KONEÈNÝ AUTOMAT
-- pùvodní verze neobsahovala stavy AL_..., nastavování budíku probíhalo pøes stejné stavy jako u hodin,
-- jen se pøedem nastavil CNTS(12) na '1' + pomocný signál alarm takté na '1', ale bohue se oba tyto signály
-- ihned nulovaly a nebylo moné identifikovat nastavování alarmu (nepøili jsme na pùvod tohoto chování).
-- Proto je pouíto více stavù ne by bylo potøeba + po pøechodu do nastavení hodin se budík automaticky
-- vypne a je nutno jej znovu zapnout po nastavení hodin.
-- Testování na hodnotu signálu alarm jsme zachovali pro pøedstavu pùvodního návrhu.
architecture behavioral of fsm is
-- funkce pro pøevod hodnoty vektoru klávesnice na hodnotu zmáèklé klávesy
function log2(val : integer) return natural is
variable result : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
result := i;
exit;
end if;
end loop;
return result;
end function;
type t_state is (Hour2, Hour11, Hour12, Min2, Min1, Sec2, Sec1, IDLE, IDLE2,
AL_Hour2, AL_Hour11, AL_Hour12, AL_Min2, AL_Min1, AL_Sec2, AL_Sec1);
signal present_state, next_state: t_state;
signal tmp: integer;
signal alarm: std_logic;
begin
sync_logic : process(CLK)
begin
if (RESET = '1') then
present_state <= IDLE;
elsif (CLK'event AND CLK = '1') then
present_state <= next_state;
end if;
end process sync_logic;
next_state_logic : process(present_state, KEY)
begin
case (present_state) is
---------------------------------------------
when Hour2 =>
next_state <= Hour2;
if (KEY(1 downto 0) /= "00") then
next_state <= Hour11;
elsif (KEY(2) = '1') then
next_state <= Hour12;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Hour11 =>
next_state <= Hour11;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= Min2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Hour12 =>
next_state <= Hour12;
if (KEY(3 downto 0) /= "0000") then
next_state <= Min2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Min2 =>
next_state <= Min2;
if (KEY(5 downto 0) /= "000000") then
next_state <= Min1;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Min1 =>
next_state <= Min1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= Sec2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Sec2 =>
next_state <= Sec2;
if (KEY(5 downto 0) /= "000000") then
next_state <= Sec1;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Sec1 =>
next_state <= Sec1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= Hour2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when AL_Hour2 =>
next_state <= AL_Hour2;
if (KEY(1 downto 0) /= "00") then
next_state <= AL_Hour11;
elsif (KEY(2) = '1') then
next_state <= AL_Hour12;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Hour11 =>
next_state <= AL_Hour11;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= AL_Min2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Hour12 =>
next_state <= AL_Hour12;
if (KEY(3 downto 0) /= "0000") then
next_state <= AL_Min2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Min2 =>
next_state <= AL_Min2;
if (KEY(5 downto 0) /= "000000") then
next_state <= AL_Min1;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Min1 =>
next_state <= AL_Min1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= AL_Sec2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Sec2 =>
next_state <= AL_Sec2;
if (KEY(5 downto 0) /= "000000") then
next_state <= AL_Sec1;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Sec1 =>
next_state <= AL_Sec1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= AL_Hour2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when IDLE =>
next_state <= IDLE;
if (KEY(15) = '1') then
next_state <= Hour2;
elsif (KEY(10) = '1') then
next_state <= IDLE2;
elsif (KEY(14) = '1') then
next_state <= AL_Hour2;
end if;
---------------------------------------------
when IDLE2 =>
next_state <= IDLE2;
if (KEY(15) = '1') then
next_state <= Hour2;
elsif (KEY(10) = '1') then
next_state <= IDLE;
elsif (KEY(14) = '1') then
next_state <= AL_Hour2;
end if;
---------------------------------------------
when others =>
end case;
end process next_state_logic;
output_logic : process(present_state, KEY)
begin
tmp <= log2(conv_integer(KEY(9 downto 0)));
case (present_state) is
---------------------------------------------
when Hour2 | AL_Hour2 =>
if (present_state = AL_Hour2) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(6) <= '1';
if (KEY(2 downto 0) /= "000") then
CNTS(6) <= '0';
CNTS(5) <= '0';
CNTS(0) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Hour11 | AL_Hour11 =>
if (present_state = AL_Hour11) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(7) <= '1';
if (KEY(9 downto 0) /= "0000000000") then
CNTS(7) <= '0';
CNTS(0) <= '0';
CNTS(1) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Hour12 | AL_Hour12 =>
if (present_state = AL_Hour12) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(7) <= '1';
if (KEY(3 downto 0) /= "0000") then
CNTS(7) <= '0';
CNTS(0) <= '0';
CNTS(1) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Min2 | AL_Min2 =>
if (present_state = AL_Min2) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(8) <= '1';
if (KEY(5 downto 0) /= "000000") then
CNTS(8) <= '0';
CNTS(1) <= '0';
CNTS(2) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Min1 | AL_Min1 =>
if (present_state = AL_Min1) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(9) <= '1';
if (KEY(9 downto 0) /= "0000000000") then
CNTS(9) <= '0';
CNTS(2) <= '0';
CNTS(3) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Sec2 | AL_Sec2 =>
if (present_state = AL_Sec2) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(10) <= '1';
if (KEY(5 downto 0) /= "000000") then
CNTS(10) <= '0';
CNTS(3) <= '0';
CNTS(4) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Sec1 | AL_Sec1 =>
if (present_state = AL_Sec1) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(11) <= '1';
if (KEY(9 downto 0) /= "0000000000") then
CNTS(11) <= '0';
CNTS(4) <= '0';
CNTS(5) <= '1';
value <= tmp;
end if;
---------------------------------------------
when IDLE =>
CNTS(13 downto 0) <= "00000000000000";
alarm <= '0';
if (KEY(14) = '1') then
CNTS(12) <= '1';
CNTS(13) <= '1';
alarm <= '1';
end if;
---------------------------------------------
when IDLE2 =>
CNTS(13 downto 0) <= "10000000000000";
alarm <= '1';
if (KEY(14) = '1') then
CNTS(12) <= '1';
end if;
---------------------------------------------
when others =>
end case;
end process output_logic;
end architecture behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity internalram is
port (
CLK: in std_logic;
EN: in std_logic;
ADDR: in std_logic_vector(12 downto 2);
DO: out std_logic_vector(31 downto 0)
);
end entity internalram;
architecture behave of internalram is
begin
process(CLK)
variable iaddr: natural;
begin
if rising_edge(CLK) then
if EN='1' then
iaddr := to_integer(unsigned(ADDR));
case iaddr is
when 0 => DO <= x"80007020";
when 1 => DO <= x"70427331";
when 2 => DO <= x"10121860";
when 3 => DO <= x"1000f001";
when 4 => DO <= x"4010a5a5";
when 5 => DO <= x"704b7a52";
when 6 => DO <= x"10211830";
when 7 => DO <= x"0723c1c0";
when 8 => DO <= x"42003800";
when 9 => DO <= x"80006080";
when 10 => DO <= x"6001c060";
when 11 => DO <= x"42003800";
when 12 => DO <= x"4e600011";
when 13 => DO <= x"cfad4000";
when 14 => DO <= x"74514fe0";
when 15 => DO <= x"38001060";
when 16 => DO <= x"0c1a801f";
when 17 => DO <= x"40fc3c11";
when 18 => DO <= x"38008511";
when 19 => DO <= x"40023e11";
when 20 => DO <= x"3800c16d";
when 21 => DO <= x"40013800";
when 22 => DO <= x"70112401";
when 23 => DO <= x"38003800";
when 24 => DO <= x"38003800";
when 25 => DO <= x"80096080";
when 26 => DO <= x"7f31c9cd";
when 27 => DO <= x"40003800";
when 28 => DO <= x"46ed0ca1";
when 29 => DO <= x"800a6080";
when 30 => DO <= x"7331c8cd";
when 31 => DO <= x"40003800";
when 32 => DO <= x"8aa14002";
when 33 => DO <= x"7002cc2d";
when 34 => DO <= x"40033800";
when 35 => DO <= x"4fe03800";
when 36 => DO <= x"0cdc0c1b";
when 37 => DO <= x"80096080";
when 38 => DO <= x"7d8146ed";
when 39 => DO <= x"38000c41";
when 40 => DO <= x"43ed3800";
when 41 => DO <= x"80096080";
when 42 => DO <= x"7f1145ed";
when 43 => DO <= x"38000c41";
when 44 => DO <= x"42ed3800";
when 45 => DO <= x"42603800";
when 46 => DO <= x"0c1b0c27";
when 47 => DO <= x"80096080";
when 48 => DO <= x"7d81446d";
when 49 => DO <= x"38000c71";
when 50 => DO <= x"416d3800";
when 51 => DO <= x"80096080";
when 52 => DO <= x"7f11436d";
when 53 => DO <= x"38000c51";
when 54 => DO <= x"406d3800";
when 55 => DO <= x"4fe03800";
when 56 => DO <= x"0cd50c14";
when 57 => DO <= x"70778941";
when 58 => DO <= x"401c8844";
when 59 => DO <= x"40048411";
when 60 => DO <= x"400f5301";
when 61 => DO <= x"6391d081";
when 62 => DO <= x"4700436d";
when 63 => DO <= x"38006007";
when 64 => DO <= x"ce2041ff";
when 65 => DO <= x"5ff73050";
when 66 => DO <= x"38000c18";
when 67 => DO <= x"1a186001";
when 68 => DO <= x"c0e04200";
when 69 => DO <= x"50180cd6";
when 70 => DO <= x"418d3800";
when 71 => DO <= x"0c6d4ec0";
when 72 => DO <= x"380030d0";
when 73 => DO <= x"38000000";
when 74 => DO <= x"00000000";
when 75 => DO <= x"00000000";
when 76 => DO <= x"00008000";
when 77 => DO <= x"70207002";
when 78 => DO <= x"98324004";
when 79 => DO <= x"84334002";
when 80 => DO <= x"6003cf20";
when 81 => DO <= x"41ff3800";
when 82 => DO <= x"101230d0";
when 83 => DO <= x"38007021";
when 84 => DO <= x"24013800";
when 85 => DO <= x"38003800";
when 86 => DO <= x"20013800";
when 87 => DO <= x"84124002";
when 88 => DO <= x"6002cf20";
when 89 => DO <= x"41ff3800";
when 90 => DO <= x"30d03800";
when 91 => DO <= x"70112401";
when 92 => DO <= x"38003800";
when 93 => DO <= x"38003800";
when 94 => DO <= x"30d03800";
when 95 => DO <= x"30103800";
when 96 => DO <= x"00000000";
when 97 => DO <= x"00000000";
when 98 => DO <= x"00008004";
when 99 => DO <= x"608074cd";
when 100 => DO <= x"30d07001";
when 101 => DO <= x"4fe03800";
when 102 => DO <= x"4fe03800";
when 103 => DO <= x"3e5f3800";
when 104 => DO <= x"ffff6000";
when 105 => DO <= x"7fcf180f";
when 106 => DO <= x"101f902f";
when 107 => DO <= x"40fc903f";
when 108 => DO <= x"40f8904f";
when 109 => DO <= x"40f4905f";
when 110 => DO <= x"40f0906f";
when 111 => DO <= x"40ec907f";
when 112 => DO <= x"40e8908f";
when 113 => DO <= x"40e4909f";
when 114 => DO <= x"40e090af";
when 115 => DO <= x"40dc90bf";
when 116 => DO <= x"40d890cf";
when 117 => DO <= x"40d490df";
when 118 => DO <= x"40d090ef";
when 119 => DO <= x"40cc3c51";
when 120 => DO <= x"3800901f";
when 121 => DO <= x"40c83c21";
when 122 => DO <= x"3800901f";
when 123 => DO <= x"40c43c41";
when 124 => DO <= x"3800901f";
when 125 => DO <= x"40c080f1";
when 126 => DO <= x"40c05bcf";
when 127 => DO <= x"cdcd4002";
when 128 => DO <= x"3800544f";
when 129 => DO <= x"981f40c0";
when 130 => DO <= x"3e413800";
when 131 => DO <= x"981f40c4";
when 132 => DO <= x"3e213800";
when 133 => DO <= x"981f40c8";
when 134 => DO <= x"3e513800";
when 135 => DO <= x"98ef40cc";
when 136 => DO <= x"98df40d0";
when 137 => DO <= x"98cf40d4";
when 138 => DO <= x"98bf40d8";
when 139 => DO <= x"98af40dc";
when 140 => DO <= x"989f40e0";
when 141 => DO <= x"988f40e4";
when 142 => DO <= x"987f40e8";
when 143 => DO <= x"986f40ec";
when 144 => DO <= x"985f40f0";
when 145 => DO <= x"984f40f4";
when 146 => DO <= x"983f40f8";
when 147 => DO <= x"982f40fc";
when 148 => DO <= x"181f3c5f";
when 149 => DO <= x"38003400";
when 150 => DO <= x"38000c01";
when 151 => DO <= x"0c020c03";
when 152 => DO <= x"0c040c05";
when 153 => DO <= x"0c060c07";
when 154 => DO <= x"0c080c09";
when 155 => DO <= x"0c0a0c0b";
when 156 => DO <= x"30d00c0c";
when 157 => DO <= x"3c113800";
when 158 => DO <= x"30d03800";
when 159 => DO <= x"30d03800";
when 160 => DO <= x"20813800";
when 161 => DO <= x"30d03800";
when 162 => DO <= x"20513800";
when 163 => DO <= x"30d03800";
when 164 => DO <= x"24813800";
when 165 => DO <= x"30d03800";
when 166 => DO <= x"24513800";
when 167 => DO <= x"30d03800";
when 168 => DO <= x"20913800";
when 169 => DO <= x"30d03800";
when 170 => DO <= x"20a13800";
when 171 => DO <= x"30d03800";
when 172 => DO <= x"20b13800";
when 173 => DO <= x"30d03800";
when 174 => DO <= x"20c13800";
when 175 => DO <= x"30d03800";
when 176 => DO <= x"20d13800";
when 177 => DO <= x"30d03800";
when 178 => DO <= x"20e13800";
when 179 => DO <= x"30d03800";
when 180 => DO <= x"24e13800";
when 181 => DO <= x"30d03800";
when 182 => DO <= x"20f13800";
when 183 => DO <= x"30d03800";
when 184 => DO <= x"24613800";
when 185 => DO <= x"30d02071";
when 186 => DO <= x"380030d0";
when 187 => DO <= x"38002061";
when 188 => DO <= x"380030d0";
when 189 => DO <= x"38000000";
when 190 => DO <= x"5f0f10df";
when 191 => DO <= x"905f400c";
when 192 => DO <= x"0c157011";
when 193 => DO <= x"906f4008";
when 194 => DO <= x"907f4004";
when 195 => DO <= x"90154008";
when 196 => DO <= x"70b19005";
when 197 => DO <= x"40089015";
when 198 => DO <= x"40049815";
when 199 => DO <= x"40049700";
when 200 => DO <= x"60007001";
when 201 => DO <= x"90154024";
when 202 => DO <= x"98154024";
when 203 => DO <= x"90054004";
when 204 => DO <= x"98154004";
when 205 => DO <= x"90054034";
when 206 => DO <= x"98654034";
when 207 => DO <= x"90054014";
when 208 => DO <= x"800a6080";
when 209 => DO <= x"75819875";
when 210 => DO <= x"4014c22d";
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when 1473 => DO <= x"00000000";
when 1474 => DO <= x"00000000";
when 1475 => DO <= x"00000000";
when 1476 => DO <= x"00000000";
when 1477 => DO <= x"00000000";
when 1478 => DO <= x"00000000";
when 1479 => DO <= x"00000000";
when 1480 => DO <= x"00000000";
when 1481 => DO <= x"00000000";
when 1482 => DO <= x"00000000";
when 1483 => DO <= x"00000000";
when 1484 => DO <= x"00000000";
when 1485 => DO <= x"00000000";
when 1486 => DO <= x"00000000";
when 1487 => DO <= x"00000000";
when 1488 => DO <= x"00000000";
when 1489 => DO <= x"00000000";
when 1490 => DO <= x"00000000";
when 1491 => DO <= x"00000000";
when 1492 => DO <= x"00000000";
when 1493 => DO <= x"00000000";
when 1494 => DO <= x"00000000";
when 1495 => DO <= x"00000000";
when 1496 => DO <= x"00000000";
when 1497 => DO <= x"00000000";
when 1498 => DO <= x"00000000";
when 1499 => DO <= x"00000000";
when 1500 => DO <= x"00000000";
when 1501 => DO <= x"00000000";
when 1502 => DO <= x"00000000";
when 1503 => DO <= x"00000000";
when 1504 => DO <= x"00000000";
when 1505 => DO <= x"00000000";
when 1506 => DO <= x"00000000";
when 1507 => DO <= x"00000000";
when 1508 => DO <= x"00000000";
when 1509 => DO <= x"00000000";
when 1510 => DO <= x"00000000";
when 1511 => DO <= x"00000000";
when 1512 => DO <= x"00000000";
when 1513 => DO <= x"00000000";
when 1514 => DO <= x"00000000";
when 1515 => DO <= x"00000000";
when 1516 => DO <= x"00000000";
when 1517 => DO <= x"00000000";
when 1518 => DO <= x"00000000";
when 1519 => DO <= x"00000000";
when 1520 => DO <= x"00000000";
when 1521 => DO <= x"00000000";
when 1522 => DO <= x"00000000";
when 1523 => DO <= x"00000000";
when 1524 => DO <= x"00000000";
when 1525 => DO <= x"00000000";
when 1526 => DO <= x"00000000";
when 1527 => DO <= x"00000000";
when 1528 => DO <= x"00000000";
when 1529 => DO <= x"00000000";
when 1530 => DO <= x"00000000";
when 1531 => DO <= x"00000000";
when 1532 => DO <= x"00000000";
when 1533 => DO <= x"00000000";
when 1534 => DO <= x"00000000";
when 1535 => DO <= x"00000000";
when 1536 => DO <= x"00000000";
when 1537 => DO <= x"00000000";
when 1538 => DO <= x"00000000";
when 1539 => DO <= x"00000000";
when 1540 => DO <= x"00000000";
when 1541 => DO <= x"00000000";
when 1542 => DO <= x"00000000";
when 1543 => DO <= x"00000000";
when 1544 => DO <= x"00000000";
when 1545 => DO <= x"00000000";
when 1546 => DO <= x"00000000";
when 1547 => DO <= x"00000000";
when 1548 => DO <= x"00000000";
when 1549 => DO <= x"00000000";
when 1550 => DO <= x"00000000";
when 1551 => DO <= x"00000000";
when 1552 => DO <= x"00000000";
when 1553 => DO <= x"00000000";
when 1554 => DO <= x"00000000";
when 1555 => DO <= x"00000000";
when 1556 => DO <= x"00000000";
when 1557 => DO <= x"00000000";
when 1558 => DO <= x"00000000";
when 1559 => DO <= x"00000000";
when 1560 => DO <= x"00000000";
when 1561 => DO <= x"00000000";
when 1562 => DO <= x"00000000";
when 1563 => DO <= x"00000000";
when 1564 => DO <= x"00000000";
when 1565 => DO <= x"00000000";
when 1566 => DO <= x"00000000";
when 1567 => DO <= x"00000000";
when 1568 => DO <= x"00000000";
when 1569 => DO <= x"00000000";
when 1570 => DO <= x"00000000";
when 1571 => DO <= x"00000000";
when 1572 => DO <= x"00000000";
when 1573 => DO <= x"00000000";
when 1574 => DO <= x"00000000";
when 1575 => DO <= x"00000000";
when 1576 => DO <= x"00000000";
when 1577 => DO <= x"00000000";
when 1578 => DO <= x"00000000";
when 1579 => DO <= x"00000000";
when 1580 => DO <= x"00000000";
when 1581 => DO <= x"00000000";
when 1582 => DO <= x"00000000";
when 1583 => DO <= x"00000000";
when 1584 => DO <= x"00000000";
when 1585 => DO <= x"00000000";
when 1586 => DO <= x"00000000";
when 1587 => DO <= x"00000000";
when 1588 => DO <= x"00000000";
when 1589 => DO <= x"00000000";
when 1590 => DO <= x"00000000";
when 1591 => DO <= x"00000000";
when 1592 => DO <= x"00000000";
when 1593 => DO <= x"00000000";
when 1594 => DO <= x"00000000";
when 1595 => DO <= x"00000000";
when 1596 => DO <= x"00000000";
when 1597 => DO <= x"00000000";
when 1598 => DO <= x"00000000";
when 1599 => DO <= x"00000000";
when 1600 => DO <= x"00000000";
when 1601 => DO <= x"00000000";
when 1602 => DO <= x"00000000";
when 1603 => DO <= x"00000000";
when 1604 => DO <= x"00000000";
when 1605 => DO <= x"00000000";
when 1606 => DO <= x"00000000";
when 1607 => DO <= x"00000000";
when 1608 => DO <= x"00000000";
when 1609 => DO <= x"00000000";
when 1610 => DO <= x"00000000";
when 1611 => DO <= x"00000000";
when 1612 => DO <= x"00000000";
when 1613 => DO <= x"00000000";
when 1614 => DO <= x"00000000";
when 1615 => DO <= x"00000000";
when 1616 => DO <= x"00000000";
when 1617 => DO <= x"00000000";
when 1618 => DO <= x"00000000";
when 1619 => DO <= x"00000000";
when 1620 => DO <= x"00000000";
when 1621 => DO <= x"00000000";
when 1622 => DO <= x"00000000";
when 1623 => DO <= x"00000000";
when 1624 => DO <= x"00000000";
when 1625 => DO <= x"00000000";
when 1626 => DO <= x"00000000";
when 1627 => DO <= x"00000000";
when 1628 => DO <= x"00000000";
when 1629 => DO <= x"00000000";
when 1630 => DO <= x"00000000";
when 1631 => DO <= x"00000000";
when 1632 => DO <= x"00000000";
when 1633 => DO <= x"00000000";
when 1634 => DO <= x"00000000";
when 1635 => DO <= x"00000000";
when 1636 => DO <= x"00000000";
when 1637 => DO <= x"00000000";
when 1638 => DO <= x"00000000";
when 1639 => DO <= x"00000000";
when 1640 => DO <= x"00000000";
when 1641 => DO <= x"00000000";
when 1642 => DO <= x"00000000";
when 1643 => DO <= x"00000000";
when 1644 => DO <= x"00000000";
when 1645 => DO <= x"00000000";
when 1646 => DO <= x"00000000";
when 1647 => DO <= x"00000000";
when 1648 => DO <= x"00000000";
when 1649 => DO <= x"00000000";
when 1650 => DO <= x"00000000";
when 1651 => DO <= x"00000000";
when 1652 => DO <= x"00000000";
when 1653 => DO <= x"00000000";
when 1654 => DO <= x"00000000";
when 1655 => DO <= x"00000000";
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when 1673 => DO <= x"00000000";
when 1674 => DO <= x"00000000";
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when 1689 => DO <= x"00000000";
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when 1693 => DO <= x"00000000";
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when 1704 => DO <= x"00000000";
when 1705 => DO <= x"00000000";
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when 1709 => DO <= x"00000000";
when 1710 => DO <= x"00000000";
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when 1714 => DO <= x"00000000";
when 1715 => DO <= x"00000000";
when 1716 => DO <= x"00000000";
when 1717 => DO <= x"00000000";
when 1718 => DO <= x"00000000";
when 1719 => DO <= x"00000000";
when 1720 => DO <= x"00000000";
when 1721 => DO <= x"00000000";
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when 1723 => DO <= x"00000000";
when 1724 => DO <= x"00000000";
when 1725 => DO <= x"00000000";
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when 1727 => DO <= x"00000000";
when 1728 => DO <= x"00000000";
when 1729 => DO <= x"00000000";
when 1730 => DO <= x"00000000";
when 1731 => DO <= x"00000000";
when 1732 => DO <= x"00000000";
when 1733 => DO <= x"00000000";
when 1734 => DO <= x"00000000";
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when 1736 => DO <= x"00000000";
when 1737 => DO <= x"00000000";
when 1738 => DO <= x"00000000";
when 1739 => DO <= x"00000000";
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when 1741 => DO <= x"00000000";
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when 1782 => DO <= x"00000000";
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when 1803 => DO <= x"00000000";
when 1804 => DO <= x"00000000";
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when 1807 => DO <= x"00000000";
when 1808 => DO <= x"00000000";
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when 1810 => DO <= x"00000000";
when 1811 => DO <= x"00000000";
when 1812 => DO <= x"00000000";
when 1813 => DO <= x"00000000";
when 1814 => DO <= x"00000000";
when 1815 => DO <= x"00000000";
when 1816 => DO <= x"00000000";
when 1817 => DO <= x"00000000";
when 1818 => DO <= x"00000000";
when 1819 => DO <= x"00000000";
when 1820 => DO <= x"00000000";
when 1821 => DO <= x"00000000";
when 1822 => DO <= x"00000000";
when 1823 => DO <= x"00000000";
when 1824 => DO <= x"00000000";
when 1825 => DO <= x"00000000";
when 1826 => DO <= x"00000000";
when 1827 => DO <= x"00000000";
when 1828 => DO <= x"00000000";
when 1829 => DO <= x"00000000";
when 1830 => DO <= x"00000000";
when 1831 => DO <= x"00000000";
when 1832 => DO <= x"00000000";
when 1833 => DO <= x"00000000";
when 1834 => DO <= x"00000000";
when 1835 => DO <= x"00000000";
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when 1837 => DO <= x"00000000";
when 1838 => DO <= x"00000000";
when 1839 => DO <= x"00000000";
when 1840 => DO <= x"00000000";
when 1841 => DO <= x"00000000";
when 1842 => DO <= x"00000000";
when 1843 => DO <= x"00000000";
when 1844 => DO <= x"00000000";
when 1845 => DO <= x"00000000";
when 1846 => DO <= x"00000000";
when 1847 => DO <= x"00000000";
when 1848 => DO <= x"00000000";
when 1849 => DO <= x"00000000";
when 1850 => DO <= x"00000000";
when 1851 => DO <= x"00000000";
when 1852 => DO <= x"00000000";
when 1853 => DO <= x"00000000";
when 1854 => DO <= x"00000000";
when 1855 => DO <= x"00000000";
when 1856 => DO <= x"00000000";
when 1857 => DO <= x"00000000";
when 1858 => DO <= x"00000000";
when 1859 => DO <= x"00000000";
when 1860 => DO <= x"00000000";
when 1861 => DO <= x"00000000";
when 1862 => DO <= x"00000000";
when 1863 => DO <= x"00000000";
when 1864 => DO <= x"00000000";
when 1865 => DO <= x"00000000";
when 1866 => DO <= x"00000000";
when 1867 => DO <= x"00000000";
when 1868 => DO <= x"00000000";
when 1869 => DO <= x"00000000";
when 1870 => DO <= x"00000000";
when 1871 => DO <= x"00000000";
when 1872 => DO <= x"00000000";
when 1873 => DO <= x"00000000";
when 1874 => DO <= x"00000000";
when 1875 => DO <= x"00000000";
when 1876 => DO <= x"00000000";
when 1877 => DO <= x"00000000";
when 1878 => DO <= x"00000000";
when 1879 => DO <= x"00000000";
when 1880 => DO <= x"00000000";
when 1881 => DO <= x"00000000";
when 1882 => DO <= x"00000000";
when 1883 => DO <= x"00000000";
when 1884 => DO <= x"00000000";
when 1885 => DO <= x"00000000";
when 1886 => DO <= x"00000000";
when 1887 => DO <= x"00000000";
when 1888 => DO <= x"00000000";
when 1889 => DO <= x"00000000";
when 1890 => DO <= x"00000000";
when 1891 => DO <= x"00000000";
when 1892 => DO <= x"00000000";
when 1893 => DO <= x"00000000";
when 1894 => DO <= x"00000000";
when 1895 => DO <= x"00000000";
when 1896 => DO <= x"00000000";
when 1897 => DO <= x"00000000";
when 1898 => DO <= x"00000000";
when 1899 => DO <= x"00000000";
when 1900 => DO <= x"00000000";
when 1901 => DO <= x"00000000";
when 1902 => DO <= x"00000000";
when 1903 => DO <= x"00000000";
when 1904 => DO <= x"00000000";
when 1905 => DO <= x"00000000";
when 1906 => DO <= x"00000000";
when 1907 => DO <= x"00000000";
when 1908 => DO <= x"00000000";
when 1909 => DO <= x"00000000";
when 1910 => DO <= x"00000000";
when 1911 => DO <= x"00000000";
when 1912 => DO <= x"00000000";
when 1913 => DO <= x"00000000";
when 1914 => DO <= x"00000000";
when 1915 => DO <= x"00000000";
when 1916 => DO <= x"00000000";
when 1917 => DO <= x"00000000";
when 1918 => DO <= x"00000000";
when 1919 => DO <= x"00000000";
when 1920 => DO <= x"00000000";
when 1921 => DO <= x"00000000";
when 1922 => DO <= x"00000000";
when 1923 => DO <= x"00000000";
when 1924 => DO <= x"00000000";
when 1925 => DO <= x"00000000";
when 1926 => DO <= x"00000000";
when 1927 => DO <= x"00000000";
when 1928 => DO <= x"00000000";
when 1929 => DO <= x"00000000";
when 1930 => DO <= x"00000000";
when 1931 => DO <= x"00000000";
when 1932 => DO <= x"00000000";
when 1933 => DO <= x"00000000";
when 1934 => DO <= x"00000000";
when 1935 => DO <= x"00000000";
when 1936 => DO <= x"00000000";
when 1937 => DO <= x"00000000";
when 1938 => DO <= x"00000000";
when 1939 => DO <= x"00000000";
when 1940 => DO <= x"00000000";
when 1941 => DO <= x"00000000";
when 1942 => DO <= x"00000000";
when 1943 => DO <= x"00000000";
when 1944 => DO <= x"00000000";
when 1945 => DO <= x"00000000";
when 1946 => DO <= x"00000000";
when 1947 => DO <= x"00000000";
when 1948 => DO <= x"00000000";
when 1949 => DO <= x"00000000";
when 1950 => DO <= x"00000000";
when 1951 => DO <= x"00000000";
when 1952 => DO <= x"00000000";
when 1953 => DO <= x"00000000";
when 1954 => DO <= x"00000000";
when 1955 => DO <= x"00000000";
when 1956 => DO <= x"00000000";
when 1957 => DO <= x"00000000";
when 1958 => DO <= x"00000000";
when 1959 => DO <= x"00000000";
when 1960 => DO <= x"00000000";
when 1961 => DO <= x"00000000";
when 1962 => DO <= x"00000000";
when 1963 => DO <= x"00000000";
when 1964 => DO <= x"00000000";
when 1965 => DO <= x"00000000";
when 1966 => DO <= x"00000000";
when 1967 => DO <= x"00000000";
when 1968 => DO <= x"00000000";
when 1969 => DO <= x"00000000";
when 1970 => DO <= x"00000000";
when 1971 => DO <= x"00000000";
when 1972 => DO <= x"00000000";
when 1973 => DO <= x"00000000";
when 1974 => DO <= x"00000000";
when 1975 => DO <= x"00000000";
when 1976 => DO <= x"00000000";
when 1977 => DO <= x"00000000";
when 1978 => DO <= x"00000000";
when 1979 => DO <= x"00000000";
when 1980 => DO <= x"00000000";
when 1981 => DO <= x"00000000";
when 1982 => DO <= x"00000000";
when 1983 => DO <= x"00000000";
when 1984 => DO <= x"00000000";
when 1985 => DO <= x"00000000";
when 1986 => DO <= x"00000000";
when 1987 => DO <= x"00000000";
when 1988 => DO <= x"00000000";
when 1989 => DO <= x"00000000";
when 1990 => DO <= x"00000000";
when 1991 => DO <= x"00000000";
when 1992 => DO <= x"00000000";
when 1993 => DO <= x"00000000";
when 1994 => DO <= x"00000000";
when 1995 => DO <= x"00000000";
when 1996 => DO <= x"00000000";
when 1997 => DO <= x"00000000";
when 1998 => DO <= x"00000000";
when 1999 => DO <= x"00000000";
when 2000 => DO <= x"00000000";
when 2001 => DO <= x"00000000";
when 2002 => DO <= x"00000000";
when 2003 => DO <= x"00000000";
when 2004 => DO <= x"00000000";
when 2005 => DO <= x"00000000";
when 2006 => DO <= x"00000000";
when 2007 => DO <= x"00000000";
when 2008 => DO <= x"00000000";
when 2009 => DO <= x"00000000";
when 2010 => DO <= x"00000000";
when 2011 => DO <= x"00000000";
when 2012 => DO <= x"00000000";
when 2013 => DO <= x"00000000";
when 2014 => DO <= x"00000000";
when 2015 => DO <= x"00000000";
when 2016 => DO <= x"00000000";
when 2017 => DO <= x"00000000";
when 2018 => DO <= x"00000000";
when 2019 => DO <= x"00000000";
when 2020 => DO <= x"00000000";
when 2021 => DO <= x"00000000";
when 2022 => DO <= x"00000000";
when 2023 => DO <= x"00000000";
when 2024 => DO <= x"00000000";
when 2025 => DO <= x"00000000";
when 2026 => DO <= x"00000000";
when 2027 => DO <= x"00000000";
when 2028 => DO <= x"00000000";
when 2029 => DO <= x"00000000";
when 2030 => DO <= x"00000000";
when 2031 => DO <= x"00000000";
when 2032 => DO <= x"00000000";
when 2033 => DO <= x"00000000";
when 2034 => DO <= x"00000000";
when 2035 => DO <= x"00000000";
when 2036 => DO <= x"00000000";
when 2037 => DO <= x"00000000";
when 2038 => DO <= x"00000000";
when 2039 => DO <= x"00000000";
when 2040 => DO <= x"00000000";
when 2041 => DO <= x"00000000";
when 2042 => DO <= x"00000000";
when 2043 => DO <= x"00000000";
when 2044 => DO <= x"00000000";
when 2045 => DO <= x"00000000";
when 2046 => DO <= x"00000000";
when 2047 => DO <= x"00000000";
when others =>
end case;
end if;
end if;
end process;
end behave;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : zynq_design_1_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
-- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
---------------------
-- twiddle factor for
-- 256-point FFT
---------------------
-- Description
-- This is an automatically generated twiddle factor file for 256 points FFT
library ieee;
use ieee.std_logic_1164.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
entity twiddle_factor is
generic (
-- data width of the real and imaginary part
data_width : integer := 16
);
port (
-- twiddle factor output
wk_out_re : out std_logic_vector (256 / 2 * data_width - 1 downto 0);
wk_out_im : out std_logic_vector (256 / 2 * data_width - 1 downto 0)
);
end twiddle_factor;
-- Function Implementation 0
architecture FIMP_0 of twiddle_factor is
begin
-- twiddle factor values
wk_out_re( (0 + 1) * data_width - 1
downto
0 * data_width
) <= to_slv(to_sfixed(1.0, 0, 1- data_width));
wk_out_im( (0 + 1) * data_width - 1
downto
0 * data_width
) <= to_slv(to_sfixed(0.0, 0, 1- data_width));
wk_out_re( (1 + 1) * data_width - 1
downto
1 * data_width
) <= to_slv(to_sfixed(0.999698818696, 0, 1- data_width));
wk_out_im( (1 + 1) * data_width - 1
downto
1 * data_width
) <= to_slv(to_sfixed(-0.0245412285229, 0, 1- data_width));
wk_out_re( (2 + 1) * data_width - 1
downto
2 * data_width
) <= to_slv(to_sfixed(0.998795456205, 0, 1- data_width));
wk_out_im( (2 + 1) * data_width - 1
downto
2 * data_width
) <= to_slv(to_sfixed(-0.0490676743274, 0, 1- data_width));
wk_out_re( (3 + 1) * data_width - 1
downto
3 * data_width
) <= to_slv(to_sfixed(0.997290456679, 0, 1- data_width));
wk_out_im( (3 + 1) * data_width - 1
downto
3 * data_width
) <= to_slv(to_sfixed(-0.0735645635997, 0, 1- data_width));
wk_out_re( (4 + 1) * data_width - 1
downto
4 * data_width
) <= to_slv(to_sfixed(0.995184726672, 0, 1- data_width));
wk_out_im( (4 + 1) * data_width - 1
downto
4 * data_width
) <= to_slv(to_sfixed(-0.0980171403296, 0, 1- data_width));
wk_out_re( (5 + 1) * data_width - 1
downto
5 * data_width
) <= to_slv(to_sfixed(0.992479534599, 0, 1- data_width));
wk_out_im( (5 + 1) * data_width - 1
downto
5 * data_width
) <= to_slv(to_sfixed(-0.122410675199, 0, 1- data_width));
wk_out_re( (6 + 1) * data_width - 1
downto
6 * data_width
) <= to_slv(to_sfixed(0.989176509965, 0, 1- data_width));
wk_out_im( (6 + 1) * data_width - 1
downto
6 * data_width
) <= to_slv(to_sfixed(-0.146730474455, 0, 1- data_width));
wk_out_re( (7 + 1) * data_width - 1
downto
7 * data_width
) <= to_slv(to_sfixed(0.985277642389, 0, 1- data_width));
wk_out_im( (7 + 1) * data_width - 1
downto
7 * data_width
) <= to_slv(to_sfixed(-0.17096188876, 0, 1- data_width));
wk_out_re( (8 + 1) * data_width - 1
downto
8 * data_width
) <= to_slv(to_sfixed(0.980785280403, 0, 1- data_width));
wk_out_im( (8 + 1) * data_width - 1
downto
8 * data_width
) <= to_slv(to_sfixed(-0.195090322016, 0, 1- data_width));
wk_out_re( (9 + 1) * data_width - 1
downto
9 * data_width
) <= to_slv(to_sfixed(0.975702130039, 0, 1- data_width));
wk_out_im( (9 + 1) * data_width - 1
downto
9 * data_width
) <= to_slv(to_sfixed(-0.219101240157, 0, 1- data_width));
wk_out_re( (10 + 1) * data_width - 1
downto
10 * data_width
) <= to_slv(to_sfixed(0.970031253195, 0, 1- data_width));
wk_out_im( (10 + 1) * data_width - 1
downto
10 * data_width
) <= to_slv(to_sfixed(-0.242980179903, 0, 1- data_width));
wk_out_re( (11 + 1) * data_width - 1
downto
11 * data_width
) <= to_slv(to_sfixed(0.963776065795, 0, 1- data_width));
wk_out_im( (11 + 1) * data_width - 1
downto
11 * data_width
) <= to_slv(to_sfixed(-0.266712757475, 0, 1- data_width));
wk_out_re( (12 + 1) * data_width - 1
downto
12 * data_width
) <= to_slv(to_sfixed(0.956940335732, 0, 1- data_width));
wk_out_im( (12 + 1) * data_width - 1
downto
12 * data_width
) <= to_slv(to_sfixed(-0.290284677254, 0, 1- data_width));
wk_out_re( (13 + 1) * data_width - 1
downto
13 * data_width
) <= to_slv(to_sfixed(0.949528180593, 0, 1- data_width));
wk_out_im( (13 + 1) * data_width - 1
downto
13 * data_width
) <= to_slv(to_sfixed(-0.313681740399, 0, 1- data_width));
wk_out_re( (14 + 1) * data_width - 1
downto
14 * data_width
) <= to_slv(to_sfixed(0.941544065183, 0, 1- data_width));
wk_out_im( (14 + 1) * data_width - 1
downto
14 * data_width
) <= to_slv(to_sfixed(-0.336889853392, 0, 1- data_width));
wk_out_re( (15 + 1) * data_width - 1
downto
15 * data_width
) <= to_slv(to_sfixed(0.932992798835, 0, 1- data_width));
wk_out_im( (15 + 1) * data_width - 1
downto
15 * data_width
) <= to_slv(to_sfixed(-0.359895036535, 0, 1- data_width));
wk_out_re( (16 + 1) * data_width - 1
downto
16 * data_width
) <= to_slv(to_sfixed(0.923879532511, 0, 1- data_width));
wk_out_im( (16 + 1) * data_width - 1
downto
16 * data_width
) <= to_slv(to_sfixed(-0.382683432365, 0, 1- data_width));
wk_out_re( (17 + 1) * data_width - 1
downto
17 * data_width
) <= to_slv(to_sfixed(0.914209755704, 0, 1- data_width));
wk_out_im( (17 + 1) * data_width - 1
downto
17 * data_width
) <= to_slv(to_sfixed(-0.405241314005, 0, 1- data_width));
wk_out_re( (18 + 1) * data_width - 1
downto
18 * data_width
) <= to_slv(to_sfixed(0.903989293123, 0, 1- data_width));
wk_out_im( (18 + 1) * data_width - 1
downto
18 * data_width
) <= to_slv(to_sfixed(-0.42755509343, 0, 1- data_width));
wk_out_re( (19 + 1) * data_width - 1
downto
19 * data_width
) <= to_slv(to_sfixed(0.893224301196, 0, 1- data_width));
wk_out_im( (19 + 1) * data_width - 1
downto
19 * data_width
) <= to_slv(to_sfixed(-0.449611329655, 0, 1- data_width));
wk_out_re( (20 + 1) * data_width - 1
downto
20 * data_width
) <= to_slv(to_sfixed(0.881921264348, 0, 1- data_width));
wk_out_im( (20 + 1) * data_width - 1
downto
20 * data_width
) <= to_slv(to_sfixed(-0.471396736826, 0, 1- data_width));
wk_out_re( (21 + 1) * data_width - 1
downto
21 * data_width
) <= to_slv(to_sfixed(0.870086991109, 0, 1- data_width));
wk_out_im( (21 + 1) * data_width - 1
downto
21 * data_width
) <= to_slv(to_sfixed(-0.49289819223, 0, 1- data_width));
wk_out_re( (22 + 1) * data_width - 1
downto
22 * data_width
) <= to_slv(to_sfixed(0.85772861, 0, 1- data_width));
wk_out_im( (22 + 1) * data_width - 1
downto
22 * data_width
) <= to_slv(to_sfixed(-0.514102744193, 0, 1- data_width));
wk_out_re( (23 + 1) * data_width - 1
downto
23 * data_width
) <= to_slv(to_sfixed(0.84485356525, 0, 1- data_width));
wk_out_im( (23 + 1) * data_width - 1
downto
23 * data_width
) <= to_slv(to_sfixed(-0.534997619887, 0, 1- data_width));
wk_out_re( (24 + 1) * data_width - 1
downto
24 * data_width
) <= to_slv(to_sfixed(0.831469612303, 0, 1- data_width));
wk_out_im( (24 + 1) * data_width - 1
downto
24 * data_width
) <= to_slv(to_sfixed(-0.55557023302, 0, 1- data_width));
wk_out_re( (25 + 1) * data_width - 1
downto
25 * data_width
) <= to_slv(to_sfixed(0.817584813152, 0, 1- data_width));
wk_out_im( (25 + 1) * data_width - 1
downto
25 * data_width
) <= to_slv(to_sfixed(-0.575808191418, 0, 1- data_width));
wk_out_re( (26 + 1) * data_width - 1
downto
26 * data_width
) <= to_slv(to_sfixed(0.803207531481, 0, 1- data_width));
wk_out_im( (26 + 1) * data_width - 1
downto
26 * data_width
) <= to_slv(to_sfixed(-0.595699304492, 0, 1- data_width));
wk_out_re( (27 + 1) * data_width - 1
downto
27 * data_width
) <= to_slv(to_sfixed(0.788346427627, 0, 1- data_width));
wk_out_im( (27 + 1) * data_width - 1
downto
27 * data_width
) <= to_slv(to_sfixed(-0.615231590581, 0, 1- data_width));
wk_out_re( (28 + 1) * data_width - 1
downto
28 * data_width
) <= to_slv(to_sfixed(0.773010453363, 0, 1- data_width));
wk_out_im( (28 + 1) * data_width - 1
downto
28 * data_width
) <= to_slv(to_sfixed(-0.634393284164, 0, 1- data_width));
wk_out_re( (29 + 1) * data_width - 1
downto
29 * data_width
) <= to_slv(to_sfixed(0.757208846506, 0, 1- data_width));
wk_out_im( (29 + 1) * data_width - 1
downto
29 * data_width
) <= to_slv(to_sfixed(-0.653172842954, 0, 1- data_width));
wk_out_re( (30 + 1) * data_width - 1
downto
30 * data_width
) <= to_slv(to_sfixed(0.740951125355, 0, 1- data_width));
wk_out_im( (30 + 1) * data_width - 1
downto
30 * data_width
) <= to_slv(to_sfixed(-0.671558954847, 0, 1- data_width));
wk_out_re( (31 + 1) * data_width - 1
downto
31 * data_width
) <= to_slv(to_sfixed(0.724247082951, 0, 1- data_width));
wk_out_im( (31 + 1) * data_width - 1
downto
31 * data_width
) <= to_slv(to_sfixed(-0.689540544737, 0, 1- data_width));
wk_out_re( (32 + 1) * data_width - 1
downto
32 * data_width
) <= to_slv(to_sfixed(0.707106781187, 0, 1- data_width));
wk_out_im( (32 + 1) * data_width - 1
downto
32 * data_width
) <= to_slv(to_sfixed(-0.707106781187, 0, 1- data_width));
wk_out_re( (33 + 1) * data_width - 1
downto
33 * data_width
) <= to_slv(to_sfixed(0.689540544737, 0, 1- data_width));
wk_out_im( (33 + 1) * data_width - 1
downto
33 * data_width
) <= to_slv(to_sfixed(-0.724247082951, 0, 1- data_width));
wk_out_re( (34 + 1) * data_width - 1
downto
34 * data_width
) <= to_slv(to_sfixed(0.671558954847, 0, 1- data_width));
wk_out_im( (34 + 1) * data_width - 1
downto
34 * data_width
) <= to_slv(to_sfixed(-0.740951125355, 0, 1- data_width));
wk_out_re( (35 + 1) * data_width - 1
downto
35 * data_width
) <= to_slv(to_sfixed(0.653172842954, 0, 1- data_width));
wk_out_im( (35 + 1) * data_width - 1
downto
35 * data_width
) <= to_slv(to_sfixed(-0.757208846506, 0, 1- data_width));
wk_out_re( (36 + 1) * data_width - 1
downto
36 * data_width
) <= to_slv(to_sfixed(0.634393284164, 0, 1- data_width));
wk_out_im( (36 + 1) * data_width - 1
downto
36 * data_width
) <= to_slv(to_sfixed(-0.773010453363, 0, 1- data_width));
wk_out_re( (37 + 1) * data_width - 1
downto
37 * data_width
) <= to_slv(to_sfixed(0.615231590581, 0, 1- data_width));
wk_out_im( (37 + 1) * data_width - 1
downto
37 * data_width
) <= to_slv(to_sfixed(-0.788346427627, 0, 1- data_width));
wk_out_re( (38 + 1) * data_width - 1
downto
38 * data_width
) <= to_slv(to_sfixed(0.595699304492, 0, 1- data_width));
wk_out_im( (38 + 1) * data_width - 1
downto
38 * data_width
) <= to_slv(to_sfixed(-0.803207531481, 0, 1- data_width));
wk_out_re( (39 + 1) * data_width - 1
downto
39 * data_width
) <= to_slv(to_sfixed(0.575808191418, 0, 1- data_width));
wk_out_im( (39 + 1) * data_width - 1
downto
39 * data_width
) <= to_slv(to_sfixed(-0.817584813152, 0, 1- data_width));
wk_out_re( (40 + 1) * data_width - 1
downto
40 * data_width
) <= to_slv(to_sfixed(0.55557023302, 0, 1- data_width));
wk_out_im( (40 + 1) * data_width - 1
downto
40 * data_width
) <= to_slv(to_sfixed(-0.831469612303, 0, 1- data_width));
wk_out_re( (41 + 1) * data_width - 1
downto
41 * data_width
) <= to_slv(to_sfixed(0.534997619887, 0, 1- data_width));
wk_out_im( (41 + 1) * data_width - 1
downto
41 * data_width
) <= to_slv(to_sfixed(-0.84485356525, 0, 1- data_width));
wk_out_re( (42 + 1) * data_width - 1
downto
42 * data_width
) <= to_slv(to_sfixed(0.514102744193, 0, 1- data_width));
wk_out_im( (42 + 1) * data_width - 1
downto
42 * data_width
) <= to_slv(to_sfixed(-0.85772861, 0, 1- data_width));
wk_out_re( (43 + 1) * data_width - 1
downto
43 * data_width
) <= to_slv(to_sfixed(0.49289819223, 0, 1- data_width));
wk_out_im( (43 + 1) * data_width - 1
downto
43 * data_width
) <= to_slv(to_sfixed(-0.870086991109, 0, 1- data_width));
wk_out_re( (44 + 1) * data_width - 1
downto
44 * data_width
) <= to_slv(to_sfixed(0.471396736826, 0, 1- data_width));
wk_out_im( (44 + 1) * data_width - 1
downto
44 * data_width
) <= to_slv(to_sfixed(-0.881921264348, 0, 1- data_width));
wk_out_re( (45 + 1) * data_width - 1
downto
45 * data_width
) <= to_slv(to_sfixed(0.449611329655, 0, 1- data_width));
wk_out_im( (45 + 1) * data_width - 1
downto
45 * data_width
) <= to_slv(to_sfixed(-0.893224301196, 0, 1- data_width));
wk_out_re( (46 + 1) * data_width - 1
downto
46 * data_width
) <= to_slv(to_sfixed(0.42755509343, 0, 1- data_width));
wk_out_im( (46 + 1) * data_width - 1
downto
46 * data_width
) <= to_slv(to_sfixed(-0.903989293123, 0, 1- data_width));
wk_out_re( (47 + 1) * data_width - 1
downto
47 * data_width
) <= to_slv(to_sfixed(0.405241314005, 0, 1- data_width));
wk_out_im( (47 + 1) * data_width - 1
downto
47 * data_width
) <= to_slv(to_sfixed(-0.914209755704, 0, 1- data_width));
wk_out_re( (48 + 1) * data_width - 1
downto
48 * data_width
) <= to_slv(to_sfixed(0.382683432365, 0, 1- data_width));
wk_out_im( (48 + 1) * data_width - 1
downto
48 * data_width
) <= to_slv(to_sfixed(-0.923879532511, 0, 1- data_width));
wk_out_re( (49 + 1) * data_width - 1
downto
49 * data_width
) <= to_slv(to_sfixed(0.359895036535, 0, 1- data_width));
wk_out_im( (49 + 1) * data_width - 1
downto
49 * data_width
) <= to_slv(to_sfixed(-0.932992798835, 0, 1- data_width));
wk_out_re( (50 + 1) * data_width - 1
downto
50 * data_width
) <= to_slv(to_sfixed(0.336889853392, 0, 1- data_width));
wk_out_im( (50 + 1) * data_width - 1
downto
50 * data_width
) <= to_slv(to_sfixed(-0.941544065183, 0, 1- data_width));
wk_out_re( (51 + 1) * data_width - 1
downto
51 * data_width
) <= to_slv(to_sfixed(0.313681740399, 0, 1- data_width));
wk_out_im( (51 + 1) * data_width - 1
downto
51 * data_width
) <= to_slv(to_sfixed(-0.949528180593, 0, 1- data_width));
wk_out_re( (52 + 1) * data_width - 1
downto
52 * data_width
) <= to_slv(to_sfixed(0.290284677254, 0, 1- data_width));
wk_out_im( (52 + 1) * data_width - 1
downto
52 * data_width
) <= to_slv(to_sfixed(-0.956940335732, 0, 1- data_width));
wk_out_re( (53 + 1) * data_width - 1
downto
53 * data_width
) <= to_slv(to_sfixed(0.266712757475, 0, 1- data_width));
wk_out_im( (53 + 1) * data_width - 1
downto
53 * data_width
) <= to_slv(to_sfixed(-0.963776065795, 0, 1- data_width));
wk_out_re( (54 + 1) * data_width - 1
downto
54 * data_width
) <= to_slv(to_sfixed(0.242980179903, 0, 1- data_width));
wk_out_im( (54 + 1) * data_width - 1
downto
54 * data_width
) <= to_slv(to_sfixed(-0.970031253195, 0, 1- data_width));
wk_out_re( (55 + 1) * data_width - 1
downto
55 * data_width
) <= to_slv(to_sfixed(0.219101240157, 0, 1- data_width));
wk_out_im( (55 + 1) * data_width - 1
downto
55 * data_width
) <= to_slv(to_sfixed(-0.975702130039, 0, 1- data_width));
wk_out_re( (56 + 1) * data_width - 1
downto
56 * data_width
) <= to_slv(to_sfixed(0.195090322016, 0, 1- data_width));
wk_out_im( (56 + 1) * data_width - 1
downto
56 * data_width
) <= to_slv(to_sfixed(-0.980785280403, 0, 1- data_width));
wk_out_re( (57 + 1) * data_width - 1
downto
57 * data_width
) <= to_slv(to_sfixed(0.17096188876, 0, 1- data_width));
wk_out_im( (57 + 1) * data_width - 1
downto
57 * data_width
) <= to_slv(to_sfixed(-0.985277642389, 0, 1- data_width));
wk_out_re( (58 + 1) * data_width - 1
downto
58 * data_width
) <= to_slv(to_sfixed(0.146730474455, 0, 1- data_width));
wk_out_im( (58 + 1) * data_width - 1
downto
58 * data_width
) <= to_slv(to_sfixed(-0.989176509965, 0, 1- data_width));
wk_out_re( (59 + 1) * data_width - 1
downto
59 * data_width
) <= to_slv(to_sfixed(0.122410675199, 0, 1- data_width));
wk_out_im( (59 + 1) * data_width - 1
downto
59 * data_width
) <= to_slv(to_sfixed(-0.992479534599, 0, 1- data_width));
wk_out_re( (60 + 1) * data_width - 1
downto
60 * data_width
) <= to_slv(to_sfixed(0.0980171403296, 0, 1- data_width));
wk_out_im( (60 + 1) * data_width - 1
downto
60 * data_width
) <= to_slv(to_sfixed(-0.995184726672, 0, 1- data_width));
wk_out_re( (61 + 1) * data_width - 1
downto
61 * data_width
) <= to_slv(to_sfixed(0.0735645635997, 0, 1- data_width));
wk_out_im( (61 + 1) * data_width - 1
downto
61 * data_width
) <= to_slv(to_sfixed(-0.997290456679, 0, 1- data_width));
wk_out_re( (62 + 1) * data_width - 1
downto
62 * data_width
) <= to_slv(to_sfixed(0.0490676743274, 0, 1- data_width));
wk_out_im( (62 + 1) * data_width - 1
downto
62 * data_width
) <= to_slv(to_sfixed(-0.998795456205, 0, 1- data_width));
wk_out_re( (63 + 1) * data_width - 1
downto
63 * data_width
) <= to_slv(to_sfixed(0.0245412285229, 0, 1- data_width));
wk_out_im( (63 + 1) * data_width - 1
downto
63 * data_width
) <= to_slv(to_sfixed(-0.999698818696, 0, 1- data_width));
wk_out_re( (64 + 1) * data_width - 1
downto
64 * data_width
) <= to_slv(to_sfixed(6.12323399574e-17, 0, 1- data_width));
wk_out_im( (64 + 1) * data_width - 1
downto
64 * data_width
) <= to_slv(to_sfixed(-1.0, 0, 1- data_width));
wk_out_re( (65 + 1) * data_width - 1
downto
65 * data_width
) <= to_slv(to_sfixed(-0.0245412285229, 0, 1- data_width));
wk_out_im( (65 + 1) * data_width - 1
downto
65 * data_width
) <= to_slv(to_sfixed(-0.999698818696, 0, 1- data_width));
wk_out_re( (66 + 1) * data_width - 1
downto
66 * data_width
) <= to_slv(to_sfixed(-0.0490676743274, 0, 1- data_width));
wk_out_im( (66 + 1) * data_width - 1
downto
66 * data_width
) <= to_slv(to_sfixed(-0.998795456205, 0, 1- data_width));
wk_out_re( (67 + 1) * data_width - 1
downto
67 * data_width
) <= to_slv(to_sfixed(-0.0735645635997, 0, 1- data_width));
wk_out_im( (67 + 1) * data_width - 1
downto
67 * data_width
) <= to_slv(to_sfixed(-0.997290456679, 0, 1- data_width));
wk_out_re( (68 + 1) * data_width - 1
downto
68 * data_width
) <= to_slv(to_sfixed(-0.0980171403296, 0, 1- data_width));
wk_out_im( (68 + 1) * data_width - 1
downto
68 * data_width
) <= to_slv(to_sfixed(-0.995184726672, 0, 1- data_width));
wk_out_re( (69 + 1) * data_width - 1
downto
69 * data_width
) <= to_slv(to_sfixed(-0.122410675199, 0, 1- data_width));
wk_out_im( (69 + 1) * data_width - 1
downto
69 * data_width
) <= to_slv(to_sfixed(-0.992479534599, 0, 1- data_width));
wk_out_re( (70 + 1) * data_width - 1
downto
70 * data_width
) <= to_slv(to_sfixed(-0.146730474455, 0, 1- data_width));
wk_out_im( (70 + 1) * data_width - 1
downto
70 * data_width
) <= to_slv(to_sfixed(-0.989176509965, 0, 1- data_width));
wk_out_re( (71 + 1) * data_width - 1
downto
71 * data_width
) <= to_slv(to_sfixed(-0.17096188876, 0, 1- data_width));
wk_out_im( (71 + 1) * data_width - 1
downto
71 * data_width
) <= to_slv(to_sfixed(-0.985277642389, 0, 1- data_width));
wk_out_re( (72 + 1) * data_width - 1
downto
72 * data_width
) <= to_slv(to_sfixed(-0.195090322016, 0, 1- data_width));
wk_out_im( (72 + 1) * data_width - 1
downto
72 * data_width
) <= to_slv(to_sfixed(-0.980785280403, 0, 1- data_width));
wk_out_re( (73 + 1) * data_width - 1
downto
73 * data_width
) <= to_slv(to_sfixed(-0.219101240157, 0, 1- data_width));
wk_out_im( (73 + 1) * data_width - 1
downto
73 * data_width
) <= to_slv(to_sfixed(-0.975702130039, 0, 1- data_width));
wk_out_re( (74 + 1) * data_width - 1
downto
74 * data_width
) <= to_slv(to_sfixed(-0.242980179903, 0, 1- data_width));
wk_out_im( (74 + 1) * data_width - 1
downto
74 * data_width
) <= to_slv(to_sfixed(-0.970031253195, 0, 1- data_width));
wk_out_re( (75 + 1) * data_width - 1
downto
75 * data_width
) <= to_slv(to_sfixed(-0.266712757475, 0, 1- data_width));
wk_out_im( (75 + 1) * data_width - 1
downto
75 * data_width
) <= to_slv(to_sfixed(-0.963776065795, 0, 1- data_width));
wk_out_re( (76 + 1) * data_width - 1
downto
76 * data_width
) <= to_slv(to_sfixed(-0.290284677254, 0, 1- data_width));
wk_out_im( (76 + 1) * data_width - 1
downto
76 * data_width
) <= to_slv(to_sfixed(-0.956940335732, 0, 1- data_width));
wk_out_re( (77 + 1) * data_width - 1
downto
77 * data_width
) <= to_slv(to_sfixed(-0.313681740399, 0, 1- data_width));
wk_out_im( (77 + 1) * data_width - 1
downto
77 * data_width
) <= to_slv(to_sfixed(-0.949528180593, 0, 1- data_width));
wk_out_re( (78 + 1) * data_width - 1
downto
78 * data_width
) <= to_slv(to_sfixed(-0.336889853392, 0, 1- data_width));
wk_out_im( (78 + 1) * data_width - 1
downto
78 * data_width
) <= to_slv(to_sfixed(-0.941544065183, 0, 1- data_width));
wk_out_re( (79 + 1) * data_width - 1
downto
79 * data_width
) <= to_slv(to_sfixed(-0.359895036535, 0, 1- data_width));
wk_out_im( (79 + 1) * data_width - 1
downto
79 * data_width
) <= to_slv(to_sfixed(-0.932992798835, 0, 1- data_width));
wk_out_re( (80 + 1) * data_width - 1
downto
80 * data_width
) <= to_slv(to_sfixed(-0.382683432365, 0, 1- data_width));
wk_out_im( (80 + 1) * data_width - 1
downto
80 * data_width
) <= to_slv(to_sfixed(-0.923879532511, 0, 1- data_width));
wk_out_re( (81 + 1) * data_width - 1
downto
81 * data_width
) <= to_slv(to_sfixed(-0.405241314005, 0, 1- data_width));
wk_out_im( (81 + 1) * data_width - 1
downto
81 * data_width
) <= to_slv(to_sfixed(-0.914209755704, 0, 1- data_width));
wk_out_re( (82 + 1) * data_width - 1
downto
82 * data_width
) <= to_slv(to_sfixed(-0.42755509343, 0, 1- data_width));
wk_out_im( (82 + 1) * data_width - 1
downto
82 * data_width
) <= to_slv(to_sfixed(-0.903989293123, 0, 1- data_width));
wk_out_re( (83 + 1) * data_width - 1
downto
83 * data_width
) <= to_slv(to_sfixed(-0.449611329655, 0, 1- data_width));
wk_out_im( (83 + 1) * data_width - 1
downto
83 * data_width
) <= to_slv(to_sfixed(-0.893224301196, 0, 1- data_width));
wk_out_re( (84 + 1) * data_width - 1
downto
84 * data_width
) <= to_slv(to_sfixed(-0.471396736826, 0, 1- data_width));
wk_out_im( (84 + 1) * data_width - 1
downto
84 * data_width
) <= to_slv(to_sfixed(-0.881921264348, 0, 1- data_width));
wk_out_re( (85 + 1) * data_width - 1
downto
85 * data_width
) <= to_slv(to_sfixed(-0.49289819223, 0, 1- data_width));
wk_out_im( (85 + 1) * data_width - 1
downto
85 * data_width
) <= to_slv(to_sfixed(-0.870086991109, 0, 1- data_width));
wk_out_re( (86 + 1) * data_width - 1
downto
86 * data_width
) <= to_slv(to_sfixed(-0.514102744193, 0, 1- data_width));
wk_out_im( (86 + 1) * data_width - 1
downto
86 * data_width
) <= to_slv(to_sfixed(-0.85772861, 0, 1- data_width));
wk_out_re( (87 + 1) * data_width - 1
downto
87 * data_width
) <= to_slv(to_sfixed(-0.534997619887, 0, 1- data_width));
wk_out_im( (87 + 1) * data_width - 1
downto
87 * data_width
) <= to_slv(to_sfixed(-0.84485356525, 0, 1- data_width));
wk_out_re( (88 + 1) * data_width - 1
downto
88 * data_width
) <= to_slv(to_sfixed(-0.55557023302, 0, 1- data_width));
wk_out_im( (88 + 1) * data_width - 1
downto
88 * data_width
) <= to_slv(to_sfixed(-0.831469612303, 0, 1- data_width));
wk_out_re( (89 + 1) * data_width - 1
downto
89 * data_width
) <= to_slv(to_sfixed(-0.575808191418, 0, 1- data_width));
wk_out_im( (89 + 1) * data_width - 1
downto
89 * data_width
) <= to_slv(to_sfixed(-0.817584813152, 0, 1- data_width));
wk_out_re( (90 + 1) * data_width - 1
downto
90 * data_width
) <= to_slv(to_sfixed(-0.595699304492, 0, 1- data_width));
wk_out_im( (90 + 1) * data_width - 1
downto
90 * data_width
) <= to_slv(to_sfixed(-0.803207531481, 0, 1- data_width));
wk_out_re( (91 + 1) * data_width - 1
downto
91 * data_width
) <= to_slv(to_sfixed(-0.615231590581, 0, 1- data_width));
wk_out_im( (91 + 1) * data_width - 1
downto
91 * data_width
) <= to_slv(to_sfixed(-0.788346427627, 0, 1- data_width));
wk_out_re( (92 + 1) * data_width - 1
downto
92 * data_width
) <= to_slv(to_sfixed(-0.634393284164, 0, 1- data_width));
wk_out_im( (92 + 1) * data_width - 1
downto
92 * data_width
) <= to_slv(to_sfixed(-0.773010453363, 0, 1- data_width));
wk_out_re( (93 + 1) * data_width - 1
downto
93 * data_width
) <= to_slv(to_sfixed(-0.653172842954, 0, 1- data_width));
wk_out_im( (93 + 1) * data_width - 1
downto
93 * data_width
) <= to_slv(to_sfixed(-0.757208846506, 0, 1- data_width));
wk_out_re( (94 + 1) * data_width - 1
downto
94 * data_width
) <= to_slv(to_sfixed(-0.671558954847, 0, 1- data_width));
wk_out_im( (94 + 1) * data_width - 1
downto
94 * data_width
) <= to_slv(to_sfixed(-0.740951125355, 0, 1- data_width));
wk_out_re( (95 + 1) * data_width - 1
downto
95 * data_width
) <= to_slv(to_sfixed(-0.689540544737, 0, 1- data_width));
wk_out_im( (95 + 1) * data_width - 1
downto
95 * data_width
) <= to_slv(to_sfixed(-0.724247082951, 0, 1- data_width));
wk_out_re( (96 + 1) * data_width - 1
downto
96 * data_width
) <= to_slv(to_sfixed(-0.707106781187, 0, 1- data_width));
wk_out_im( (96 + 1) * data_width - 1
downto
96 * data_width
) <= to_slv(to_sfixed(-0.707106781187, 0, 1- data_width));
wk_out_re( (97 + 1) * data_width - 1
downto
97 * data_width
) <= to_slv(to_sfixed(-0.724247082951, 0, 1- data_width));
wk_out_im( (97 + 1) * data_width - 1
downto
97 * data_width
) <= to_slv(to_sfixed(-0.689540544737, 0, 1- data_width));
wk_out_re( (98 + 1) * data_width - 1
downto
98 * data_width
) <= to_slv(to_sfixed(-0.740951125355, 0, 1- data_width));
wk_out_im( (98 + 1) * data_width - 1
downto
98 * data_width
) <= to_slv(to_sfixed(-0.671558954847, 0, 1- data_width));
wk_out_re( (99 + 1) * data_width - 1
downto
99 * data_width
) <= to_slv(to_sfixed(-0.757208846506, 0, 1- data_width));
wk_out_im( (99 + 1) * data_width - 1
downto
99 * data_width
) <= to_slv(to_sfixed(-0.653172842954, 0, 1- data_width));
wk_out_re( (100 + 1) * data_width - 1
downto
100 * data_width
) <= to_slv(to_sfixed(-0.773010453363, 0, 1- data_width));
wk_out_im( (100 + 1) * data_width - 1
downto
100 * data_width
) <= to_slv(to_sfixed(-0.634393284164, 0, 1- data_width));
wk_out_re( (101 + 1) * data_width - 1
downto
101 * data_width
) <= to_slv(to_sfixed(-0.788346427627, 0, 1- data_width));
wk_out_im( (101 + 1) * data_width - 1
downto
101 * data_width
) <= to_slv(to_sfixed(-0.615231590581, 0, 1- data_width));
wk_out_re( (102 + 1) * data_width - 1
downto
102 * data_width
) <= to_slv(to_sfixed(-0.803207531481, 0, 1- data_width));
wk_out_im( (102 + 1) * data_width - 1
downto
102 * data_width
) <= to_slv(to_sfixed(-0.595699304492, 0, 1- data_width));
wk_out_re( (103 + 1) * data_width - 1
downto
103 * data_width
) <= to_slv(to_sfixed(-0.817584813152, 0, 1- data_width));
wk_out_im( (103 + 1) * data_width - 1
downto
103 * data_width
) <= to_slv(to_sfixed(-0.575808191418, 0, 1- data_width));
wk_out_re( (104 + 1) * data_width - 1
downto
104 * data_width
) <= to_slv(to_sfixed(-0.831469612303, 0, 1- data_width));
wk_out_im( (104 + 1) * data_width - 1
downto
104 * data_width
) <= to_slv(to_sfixed(-0.55557023302, 0, 1- data_width));
wk_out_re( (105 + 1) * data_width - 1
downto
105 * data_width
) <= to_slv(to_sfixed(-0.84485356525, 0, 1- data_width));
wk_out_im( (105 + 1) * data_width - 1
downto
105 * data_width
) <= to_slv(to_sfixed(-0.534997619887, 0, 1- data_width));
wk_out_re( (106 + 1) * data_width - 1
downto
106 * data_width
) <= to_slv(to_sfixed(-0.85772861, 0, 1- data_width));
wk_out_im( (106 + 1) * data_width - 1
downto
106 * data_width
) <= to_slv(to_sfixed(-0.514102744193, 0, 1- data_width));
wk_out_re( (107 + 1) * data_width - 1
downto
107 * data_width
) <= to_slv(to_sfixed(-0.870086991109, 0, 1- data_width));
wk_out_im( (107 + 1) * data_width - 1
downto
107 * data_width
) <= to_slv(to_sfixed(-0.49289819223, 0, 1- data_width));
wk_out_re( (108 + 1) * data_width - 1
downto
108 * data_width
) <= to_slv(to_sfixed(-0.881921264348, 0, 1- data_width));
wk_out_im( (108 + 1) * data_width - 1
downto
108 * data_width
) <= to_slv(to_sfixed(-0.471396736826, 0, 1- data_width));
wk_out_re( (109 + 1) * data_width - 1
downto
109 * data_width
) <= to_slv(to_sfixed(-0.893224301196, 0, 1- data_width));
wk_out_im( (109 + 1) * data_width - 1
downto
109 * data_width
) <= to_slv(to_sfixed(-0.449611329655, 0, 1- data_width));
wk_out_re( (110 + 1) * data_width - 1
downto
110 * data_width
) <= to_slv(to_sfixed(-0.903989293123, 0, 1- data_width));
wk_out_im( (110 + 1) * data_width - 1
downto
110 * data_width
) <= to_slv(to_sfixed(-0.42755509343, 0, 1- data_width));
wk_out_re( (111 + 1) * data_width - 1
downto
111 * data_width
) <= to_slv(to_sfixed(-0.914209755704, 0, 1- data_width));
wk_out_im( (111 + 1) * data_width - 1
downto
111 * data_width
) <= to_slv(to_sfixed(-0.405241314005, 0, 1- data_width));
wk_out_re( (112 + 1) * data_width - 1
downto
112 * data_width
) <= to_slv(to_sfixed(-0.923879532511, 0, 1- data_width));
wk_out_im( (112 + 1) * data_width - 1
downto
112 * data_width
) <= to_slv(to_sfixed(-0.382683432365, 0, 1- data_width));
wk_out_re( (113 + 1) * data_width - 1
downto
113 * data_width
) <= to_slv(to_sfixed(-0.932992798835, 0, 1- data_width));
wk_out_im( (113 + 1) * data_width - 1
downto
113 * data_width
) <= to_slv(to_sfixed(-0.359895036535, 0, 1- data_width));
wk_out_re( (114 + 1) * data_width - 1
downto
114 * data_width
) <= to_slv(to_sfixed(-0.941544065183, 0, 1- data_width));
wk_out_im( (114 + 1) * data_width - 1
downto
114 * data_width
) <= to_slv(to_sfixed(-0.336889853392, 0, 1- data_width));
wk_out_re( (115 + 1) * data_width - 1
downto
115 * data_width
) <= to_slv(to_sfixed(-0.949528180593, 0, 1- data_width));
wk_out_im( (115 + 1) * data_width - 1
downto
115 * data_width
) <= to_slv(to_sfixed(-0.313681740399, 0, 1- data_width));
wk_out_re( (116 + 1) * data_width - 1
downto
116 * data_width
) <= to_slv(to_sfixed(-0.956940335732, 0, 1- data_width));
wk_out_im( (116 + 1) * data_width - 1
downto
116 * data_width
) <= to_slv(to_sfixed(-0.290284677254, 0, 1- data_width));
wk_out_re( (117 + 1) * data_width - 1
downto
117 * data_width
) <= to_slv(to_sfixed(-0.963776065795, 0, 1- data_width));
wk_out_im( (117 + 1) * data_width - 1
downto
117 * data_width
) <= to_slv(to_sfixed(-0.266712757475, 0, 1- data_width));
wk_out_re( (118 + 1) * data_width - 1
downto
118 * data_width
) <= to_slv(to_sfixed(-0.970031253195, 0, 1- data_width));
wk_out_im( (118 + 1) * data_width - 1
downto
118 * data_width
) <= to_slv(to_sfixed(-0.242980179903, 0, 1- data_width));
wk_out_re( (119 + 1) * data_width - 1
downto
119 * data_width
) <= to_slv(to_sfixed(-0.975702130039, 0, 1- data_width));
wk_out_im( (119 + 1) * data_width - 1
downto
119 * data_width
) <= to_slv(to_sfixed(-0.219101240157, 0, 1- data_width));
wk_out_re( (120 + 1) * data_width - 1
downto
120 * data_width
) <= to_slv(to_sfixed(-0.980785280403, 0, 1- data_width));
wk_out_im( (120 + 1) * data_width - 1
downto
120 * data_width
) <= to_slv(to_sfixed(-0.195090322016, 0, 1- data_width));
wk_out_re( (121 + 1) * data_width - 1
downto
121 * data_width
) <= to_slv(to_sfixed(-0.985277642389, 0, 1- data_width));
wk_out_im( (121 + 1) * data_width - 1
downto
121 * data_width
) <= to_slv(to_sfixed(-0.17096188876, 0, 1- data_width));
wk_out_re( (122 + 1) * data_width - 1
downto
122 * data_width
) <= to_slv(to_sfixed(-0.989176509965, 0, 1- data_width));
wk_out_im( (122 + 1) * data_width - 1
downto
122 * data_width
) <= to_slv(to_sfixed(-0.146730474455, 0, 1- data_width));
wk_out_re( (123 + 1) * data_width - 1
downto
123 * data_width
) <= to_slv(to_sfixed(-0.992479534599, 0, 1- data_width));
wk_out_im( (123 + 1) * data_width - 1
downto
123 * data_width
) <= to_slv(to_sfixed(-0.122410675199, 0, 1- data_width));
wk_out_re( (124 + 1) * data_width - 1
downto
124 * data_width
) <= to_slv(to_sfixed(-0.995184726672, 0, 1- data_width));
wk_out_im( (124 + 1) * data_width - 1
downto
124 * data_width
) <= to_slv(to_sfixed(-0.0980171403296, 0, 1- data_width));
wk_out_re( (125 + 1) * data_width - 1
downto
125 * data_width
) <= to_slv(to_sfixed(-0.997290456679, 0, 1- data_width));
wk_out_im( (125 + 1) * data_width - 1
downto
125 * data_width
) <= to_slv(to_sfixed(-0.0735645635997, 0, 1- data_width));
wk_out_re( (126 + 1) * data_width - 1
downto
126 * data_width
) <= to_slv(to_sfixed(-0.998795456205, 0, 1- data_width));
wk_out_im( (126 + 1) * data_width - 1
downto
126 * data_width
) <= to_slv(to_sfixed(-0.0490676743274, 0, 1- data_width));
wk_out_re( (127 + 1) * data_width - 1
downto
127 * data_width
) <= to_slv(to_sfixed(-0.999698818696, 0, 1- data_width));
wk_out_im( (127 + 1) * data_width - 1
downto
127 * data_width
) <= to_slv(to_sfixed(-0.0245412285229, 0, 1- data_width));
end FIMP_0; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN5UKV3NIG is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000011001";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GN5UKV3NIG is
Begin
-- Constant
output <= "0000000000011001";
end architecture; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:18:24 10/06/2010
-- Design Name:
-- Module Name: Mux4to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux4to1 is
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end Mux4to1;
architecture Behavioral of Mux4to1 is
begin
--Seleccion de unidad de tiempo HH:MM
with Sel select
Tiempo <= UniMin when "00",
DecMin when "01",
UniHor when "10",
DecHor when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:18:24 10/06/2010
-- Design Name:
-- Module Name: Mux4to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux4to1 is
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end Mux4to1;
architecture Behavioral of Mux4to1 is
begin
--Seleccion de unidad de tiempo HH:MM
with Sel select
Tiempo <= UniMin when "00",
DecMin when "01",
UniHor when "10",
DecHor when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:18:24 10/06/2010
-- Design Name:
-- Module Name: Mux4to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux4to1 is
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end Mux4to1;
architecture Behavioral of Mux4to1 is
begin
--Seleccion de unidad de tiempo HH:MM
with Sel select
Tiempo <= UniMin when "00",
DecMin when "01",
UniHor when "10",
DecHor when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:18:24 10/06/2010
-- Design Name:
-- Module Name: Mux4to1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux4to1 is
port (
DecHor : in STD_LOGIC_VECTOR (3 downto 0);
UniHor : in STD_LOGIC_VECTOR (3 downto 0);
DecMin : in STD_LOGIC_VECTOR (3 downto 0);
UniMin : in STD_LOGIC_VECTOR (3 downto 0);
Sel : in STD_LOGIC_VECTOR (1 downto 0);
Tiempo : out STD_LOGIC_VECTOR (3 downto 0));
end Mux4to1;
architecture Behavioral of Mux4to1 is
begin
--Seleccion de unidad de tiempo HH:MM
with Sel select
Tiempo <= UniMin when "00",
DecMin when "01",
UniHor when "10",
DecHor when others;
end Behavioral;
|
package p is
shared variable pglobal : integer := 2;
end package;
-------------------------------------------------------------------------------
entity shared1 is
end entity;
use work.p.all;
architecture test of shared1 is
shared variable global : integer := 5;
procedure check_it(constant expect : in integer) is
begin
assert global = expect;
end procedure;
procedure set_it(constant set : in integer) is
begin
global := set;
end procedure;
begin
process is
begin
assert global = 5;
global := 6;
check_it(6);
set_it(7);
assert global = 7;
assert pglobal = 2;
pglobal := 51;
wait;
end process;
end architecture;
|
package p is
shared variable pglobal : integer := 2;
end package;
-------------------------------------------------------------------------------
entity shared1 is
end entity;
use work.p.all;
architecture test of shared1 is
shared variable global : integer := 5;
procedure check_it(constant expect : in integer) is
begin
assert global = expect;
end procedure;
procedure set_it(constant set : in integer) is
begin
global := set;
end procedure;
begin
process is
begin
assert global = 5;
global := 6;
check_it(6);
set_it(7);
assert global = 7;
assert pglobal = 2;
pglobal := 51;
wait;
end process;
end architecture;
|
package p is
shared variable pglobal : integer := 2;
end package;
-------------------------------------------------------------------------------
entity shared1 is
end entity;
use work.p.all;
architecture test of shared1 is
shared variable global : integer := 5;
procedure check_it(constant expect : in integer) is
begin
assert global = expect;
end procedure;
procedure set_it(constant set : in integer) is
begin
global := set;
end procedure;
begin
process is
begin
assert global = 5;
global := 6;
check_it(6);
set_it(7);
assert global = 7;
assert pglobal = 2;
pglobal := 51;
wait;
end process;
end architecture;
|
package p is
shared variable pglobal : integer := 2;
end package;
-------------------------------------------------------------------------------
entity shared1 is
end entity;
use work.p.all;
architecture test of shared1 is
shared variable global : integer := 5;
procedure check_it(constant expect : in integer) is
begin
assert global = expect;
end procedure;
procedure set_it(constant set : in integer) is
begin
global := set;
end procedure;
begin
process is
begin
assert global = 5;
global := 6;
check_it(6);
set_it(7);
assert global = 7;
assert pglobal = 2;
pglobal := 51;
wait;
end process;
end architecture;
|
package p is
shared variable pglobal : integer := 2;
end package;
-------------------------------------------------------------------------------
entity shared1 is
end entity;
use work.p.all;
architecture test of shared1 is
shared variable global : integer := 5;
procedure check_it(constant expect : in integer) is
begin
assert global = expect;
end procedure;
procedure set_it(constant set : in integer) is
begin
global := set;
end procedure;
begin
process is
begin
assert global = 5;
global := 6;
check_it(6);
set_it(7);
assert global = 7;
assert pglobal = 2;
pglobal := 51;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Top-level GTX wrapper for Ethernet MAC
-- Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
-- File : v6_gtxwizard_top.vhd
-- Version : 1.4
-------------------------------------------------------------------------------
--
-- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------
-- Description: This is the top-level GTX wrapper. It
-- instantiates the lower-level wrappers produced by
-- the Virtex-6 FPGA GTX Wrapper Wizard.
------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity v6_gtxwizard_top is
port (
RESETDONE : out std_logic;
ENMCOMMAALIGN : in std_logic;
ENPCOMMAALIGN : in std_logic;
LOOPBACK : in std_logic;
POWERDOWN : in std_logic;
RXUSRCLK2 : in std_logic;
RXRESET : in std_logic;
TXCHARDISPMODE : in std_logic;
TXCHARDISPVAL : in std_logic;
TXCHARISK : in std_logic;
TXDATA : in std_logic_vector (7 downto 0);
TXUSRCLK2 : in std_logic;
TXRESET : in std_logic;
RXCHARISCOMMA : out std_logic;
RXCHARISK : out std_logic;
RXCLKCORCNT : out std_logic_vector (2 downto 0);
RXDATA : out std_logic_vector (7 downto 0);
RXDISPERR : out std_logic;
RXNOTINTABLE : out std_logic;
RXRUNDISP : out std_logic;
RXBUFERR : out std_logic;
TXBUFERR : out std_logic;
PLLLKDET : out std_logic;
TXOUTCLK : out std_logic;
RXELECIDLE : out std_logic;
TXN : out std_logic;
TXP : out std_logic;
RXN : in std_logic;
RXP : in std_logic;
CLK_DS : in std_logic;
PMARESET : in std_logic
);
end v6_gtxwizard_top;
architecture wrapper of v6_gtxwizard_top is
component V6_GTXWIZARD
generic
(
-- Simulation attributes
WRAPPER_SIM_GTXRESET_SPEEDUP : integer := 1
);
port
(
------------------------ Loopback and Powerdown Ports ----------------------
GTX0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
GTX0_RXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
GTX0_TXPOWERDOWN_IN : in std_logic_vector(1 downto 0);
----------------------- Receive Ports - 8b10b Decoder ----------------------
GTX0_RXCHARISCOMMA_OUT : out std_logic;
GTX0_RXCHARISK_OUT : out std_logic;
GTX0_RXDISPERR_OUT : out std_logic;
GTX0_RXNOTINTABLE_OUT : out std_logic;
GTX0_RXRUNDISP_OUT : out std_logic;
------------------- Receive Ports - Clock Correction Ports -----------------
GTX0_RXCLKCORCNT_OUT : out std_logic_vector(2 downto 0);
--------------- Receive Ports - Comma Detection and Alignment --------------
GTX0_RXENMCOMMAALIGN_IN : in std_logic;
GTX0_RXENPCOMMAALIGN_IN : in std_logic;
------------------- Receive Ports - RX Data Path interface -----------------
GTX0_RXDATA_OUT : out std_logic_vector(7 downto 0);
GTX0_RXRECCLK_OUT : out std_logic;
GTX0_RXRESET_IN : in std_logic;
GTX0_RXUSRCLK2_IN : in std_logic;
-------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GTX0_RXBUFRESET_IN : in std_logic;
GTX0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GTX0_RXELECIDLE_OUT : out std_logic;
GTX0_RXN_IN : in std_logic;
GTX0_RXP_IN : in std_logic;
------------------------ Receive Ports - RX PLL Ports ----------------------
GTX0_GTXRXRESET_IN : in std_logic;
GTX0_MGTREFCLKRX_IN : in std_logic;
GTX0_PLLRXRESET_IN : in std_logic;
GTX0_RXPLLLKDET_OUT : out std_logic;
GTX0_RXRESETDONE_OUT : out std_logic;
---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GTX0_TXCHARDISPMODE_IN : in std_logic;
GTX0_TXCHARDISPVAL_IN : in std_logic;
GTX0_TXCHARISK_IN : in std_logic;
------------------ Transmit Ports - TX Data Path interface -----------------
GTX0_TXDATA_IN : in std_logic_vector(7 downto 0);
GTX0_TXOUTCLK_OUT : out std_logic;
GTX0_TXRESET_IN : in std_logic;
GTX0_TXUSRCLK2_IN : in std_logic;
--------------- Transmit Ports - TX Driver and OOB signalling --------------
GTX0_TXN_OUT : out std_logic;
GTX0_TXP_OUT : out std_logic;
------------- Transmit Ports - TX Buffering and Phase Alignment ------------
GTX0_TXBUFSTATUS_OUT : out std_logic_vector(1 downto 0);
----------------------- Transmit Ports - TX PLL Ports ----------------------
GTX0_GTXTXRESET_IN : in std_logic;
GTX0_TXRESETDONE_OUT : out std_logic
);
end component;
----------------------------------------------------------------------
-- Signal declarations for GTX
----------------------------------------------------------------------
signal GND_BUS : std_logic_vector (55 downto 0);
signal RXBUFSTATUS_float : std_logic_vector(1 downto 0);
signal TXBUFSTATUS_float : std_logic;
signal clk_ds_i : std_logic;
signal pma_reset_i : std_logic;
signal reset_r : std_logic_vector(3 downto 0);
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_r : signal is "TRUE";
signal resetdone_tx_i : std_logic;
signal resetdone_tx_r : std_logic;
signal resetdone_rx_i : std_logic;
signal resetdone_rx_r : std_logic;
signal resetdone_i : std_logic;
begin
GND_BUS(55 downto 0) <= (others => '0');
--------------------------------------------------------------------
-- GTX PMA reset circuitry
--------------------------------------------------------------------
-- Locally buffer the output of the IBUFDS_GTXE1 for reset logic
bufr_clk_ds : BUFR port map (
I => CLK_DS,
O => clk_ds_i,
CE => '1',
CLR => '0'
);
process(PMARESET, clk_ds_i)
begin
if (PMARESET = '1') then
reset_r <= "1111";
elsif clk_ds_i'event and clk_ds_i = '1' then
reset_r <= reset_r(2 downto 0) & PMARESET;
end if;
end process;
pma_reset_i <= reset_r(3);
----------------------------------------------------------------------
-- Instantiate the Virtex-6 GTX
----------------------------------------------------------------------
-- Direct from the GTX Wizard output
v6_gtxwizard_inst : V6_GTXWIZARD
generic map (
WRAPPER_SIM_GTXRESET_SPEEDUP => 1
)
port map (
---------------------- Loopback and Powerdown Ports ----------------------
GTX0_LOOPBACK_IN(2 downto 1) => "00",
GTX0_LOOPBACK_IN(0) => LOOPBACK,
GTX0_RXPOWERDOWN_IN(0) => POWERDOWN,
GTX0_RXPOWERDOWN_IN(1) => POWERDOWN,
GTX0_TXPOWERDOWN_IN(0) => POWERDOWN,
GTX0_TXPOWERDOWN_IN(1) => POWERDOWN,
--------------------- Receive Ports - 8b10b Decoder ----------------------
GTX0_RXCHARISCOMMA_OUT => RXCHARISCOMMA,
GTX0_RXCHARISK_OUT => RXCHARISK,
GTX0_RXDISPERR_OUT => RXDISPERR,
GTX0_RXNOTINTABLE_OUT => RXNOTINTABLE,
GTX0_RXRUNDISP_OUT => RXRUNDISP,
----------------- Receive Ports - Clock Correction Ports -----------------
GTX0_RXCLKCORCNT_OUT => RXCLKCORCNT,
------------- Receive Ports - Comma Detection and Alignment --------------
GTX0_RXENMCOMMAALIGN_IN => ENMCOMMAALIGN,
GTX0_RXENPCOMMAALIGN_IN => ENPCOMMAALIGN,
----------------- Receive Ports - RX Data Path interface -----------------
GTX0_RXDATA_OUT => RXDATA,
GTX0_RXRECCLK_OUT => open,
GTX0_RXRESET_IN => RXRESET,
GTX0_RXUSRCLK2_IN => RXUSRCLK2,
------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
GTX0_RXBUFRESET_IN => RXRESET,
GTX0_RXBUFSTATUS_OUT(2) => RXBUFERR,
GTX0_RXBUFSTATUS_OUT(1 downto 0) => RXBUFSTATUS_float,
----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GTX0_RXELECIDLE_OUT => RXELECIDLE,
GTX0_RXN_IN => RXN,
GTX0_RXP_IN => RXP,
-------------------- Receive Ports - RX PLL Ports ------------------------
GTX0_GTXRXRESET_IN => pma_reset_i,
GTX0_MGTREFCLKRX_IN => CLK_DS,
GTX0_PLLRXRESET_IN => pma_reset_i,
GTX0_RXPLLLKDET_OUT => PLLLKDET,
GTX0_RXRESETDONE_OUT => resetdone_rx_i,
-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
GTX0_TXCHARDISPMODE_IN => TXCHARDISPMODE,
GTX0_TXCHARDISPVAL_IN => TXCHARDISPVAL,
GTX0_TXCHARISK_IN => TXCHARISK,
---------------- Transmit Ports - TX Data Path interface -----------------
GTX0_TXDATA_IN => TXDATA,
GTX0_TXOUTCLK_OUT => TXOUTCLK,
GTX0_TXRESET_IN => TXRESET,
GTX0_TXUSRCLK2_IN => TXUSRCLK2,
------------- Transmit Ports - TX Driver and OOB signalling --------------
GTX0_TXN_OUT => TXN,
GTX0_TXP_OUT => TXP,
----------- Transmit Ports - TX Buffering and Phase Alignment ------------
GTX0_TXBUFSTATUS_OUT(1) => TXBUFERR,
GTX0_TXBUFSTATUS_OUT(0) => TXBUFSTATUS_float,
-------------------- Transmit Ports - TX PLL Ports -----------------------
GTX0_GTXTXRESET_IN => pma_reset_i,
GTX0_TXRESETDONE_OUT => resetdone_tx_i
);
-- Register the Tx and Rx resetdone signals, and AND them to provide a
-- single RESETDONE output
process(TXUSRCLK2, TXRESET)
begin
if (TXRESET = '1') then
resetdone_tx_r <= '0';
elsif TXUSRCLK2'event and TXUSRCLK2 = '1' then
resetdone_tx_r <= resetdone_tx_i;
end if;
end process;
process(RXUSRCLK2, RXRESET)
begin
if (RXRESET = '1') then
resetdone_rx_r <= '0';
elsif RXUSRCLK2'event and RXUSRCLK2 = '1' then
resetdone_rx_r <= resetdone_rx_i;
end if;
end process;
resetdone_i <= resetdone_tx_r and resetdone_rx_r;
RESETDONE <= resetdone_i;
end wrapper;
|
-----LIBRARIES-----
library ieee;
use ieee.std_logic_1164.all;
-----ENTITY-----
entity Demultiplexer is
port( data_in : in std_logic_vector(20 downto 0);
disp0, disp1, disp2 : out std_logic_vector(6 downto 0)
);
end Demultiplexer;
-----Architecture-----
architecture demuxer of Demultiplexer is
begin
disp0 <= data_in(6 downto 0);
disp1 <= data_in(13 downto 7);
disp2 <= data_in(20 downto 14);
end demuxer; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
-- Fun1 = A + B (aritmeetiline liitmine)
entity func1 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end func1;
architecture design of func1 is
signal a_sign, b_sign,o_sign: signed(3 downto 0);
begin
a_sign <= signed(a);
b_sign <= signed(b);
o_sign <= a_sign + b_sign;
o <= std_logic_vector(o_sign);
end design; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
-- Fun1 = A + B (aritmeetiline liitmine)
entity func1 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end func1;
architecture design of func1 is
signal a_sign, b_sign,o_sign: signed(3 downto 0);
begin
a_sign <= signed(a);
b_sign <= signed(b);
o_sign <= a_sign + b_sign;
o <= std_logic_vector(o_sign);
end design; |
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 12.2
-- \ \ Application : xaw2vhdl
-- / / Filename : global_clock.vhd
-- /___/ /\ Timestamp : 08/31/2010 15:23:33
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle D:/IO One/vga/vga/ipcore_dir/global_clock.xaw -st global_clock.vhd
--Design Name: global_clock
--Device: xc3s500e-5fg320
--
-- Module global_clock
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity global_clock is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKDV_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic);
end global_clock;
architecture BEHAVIORAL of global_clock is
signal CLKDV_BUF : std_logic;
signal CLKFB_IN : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKDV_BUFG_INST : BUFG
port map (I=>CLKDV_BUF,
O=>CLKDV_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>CLKDV_BUF,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>open,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: fifo_inferred.vhd
-- Author: Cobham Gaisler AB
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.">";
use ieee.std_logic_unsigned."<";
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity generic_fifo is
generic (
tech : integer := 0; -- target technology
abits : integer := 10; -- fifo address bits (actual fifo depth = 2**abits)
dbits : integer := 32; -- fifo data width
sepclk : integer := 1; -- 1 = asynchrounous read/write clocks, 0 = synchronous read/write clocks
pfull : integer := 100; -- almost full threshold (max 2**abits - 3)
pempty : integer := 10; -- almost empty threshold (min 2)
fwft : integer := 0 -- 1 = first word fall trough mode, 0 = standard mode
);
port (
rclk : in std_logic; -- read clock
rrstn : in std_logic; -- read clock domain synchronous reset
wrstn : in std_logic; -- write clock domain synchronous reset
renable : in std_logic; -- read enable
rfull : out std_logic; -- fifo full (synchronized in read clock domain)
rempty : out std_logic; -- fifo empty
aempty : out std_logic; -- fifo almost empty (depending on pempty threshold)
rusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in read clock domain)
dataout : out std_logic_vector(dbits-1 downto 0); -- fifo data output
wclk : in std_logic; -- write clock
write : in std_logic; -- write enable
wfull : out std_logic; -- fifo full
afull : out std_logic; -- fifo almost full (depending on pfull threshold)
wempty : out std_logic; -- fifo empty (synchronized in write clock domain)
wusedw : out std_logic_vector(abits-1 downto 0); -- fifo used words (synchronized in write clock domain)
datain : in std_logic_vector(dbits-1 downto 0)); -- fifo data input
end;
architecture rtl_fifo of generic_fifo is
procedure gray_encoder(variable idata : in std_logic_vector; variable odata : out std_logic_vector) is
begin
for i in 0 to (idata'left)-1 loop
odata(i) := idata(i) xor idata(i+1);
end loop;
odata(odata'left) := idata(idata'left);
end gray_encoder;
procedure gray_decoder(signal idata : in std_logic_vector; constant size : integer; variable odata : out std_logic_vector) is
variable vdata : std_logic_vector(size downto 0);
begin
vdata(vdata'left) := idata(idata'left);
for i in (idata'left)-1 downto 0 loop
vdata(i) := idata(i) xor vdata(i+1);
end loop;
odata := vdata;
end gray_decoder;
type wfifo_type is record
waddr : std_logic_vector(abits downto 0);
waddr_gray : std_logic_vector(abits downto 0);
full : std_logic;
end record;
type rfifo_type is record
raddr : std_logic_vector(abits downto 0);
raddr_gray : std_logic_vector(abits downto 0);
empty : std_logic;
end record;
signal wregs, wregsin : wfifo_type;
signal rregs, rregsin : rfifo_type;
signal raddr_sync_encoded, waddr_sync_encoded : std_logic_vector(abits downto 0);
signal empty_sync, full_sync : std_logic;
begin
---------------------
-- write clock domain
---------------------
wdomain_comb: process(wregs, write, raddr_sync_encoded, wrstn)
variable vwregs : wfifo_type;
variable vwusedw : std_logic_vector(abits-1 downto 0);
variable raddr_sync_decoded : std_logic_vector(abits downto 0);
begin
-- initialize fifo signals on write side
vwregs := wregs;
vwregs.full := '0';
afull <= '0';
-- fifo full generation and compute wusedw
gray_decoder(raddr_sync_encoded,abits,raddr_sync_decoded); -- decode read address coming from read clock domain
if (vwregs.waddr(abits)=raddr_sync_decoded(abits)) then
vwusedw := vwregs.waddr(abits-1 downto 0)-raddr_sync_decoded(abits-1 downto 0);
if (vwusedw > (2**abits-2)) then
vwregs.full := '1';
end if;
else
vwusedw := raddr_sync_decoded(abits-1 downto 0)-vwregs.waddr(abits-1 downto 0);
if (vwusedw < 2) then
vwregs.full := '1';
end if;
vwusedw := 2**abits - vwusedw;
end if;
-- write fifo
if write = '1' then
vwregs.waddr := vwregs.waddr + 1;
end if;
gray_encoder(vwregs.waddr,vwregs.waddr_gray);
-- assign wusedw and almost full fifo output
wusedw <= vwusedw;
if vwusedw>pfull then
afull <= '1';
end if;
-- synchronous reset
if wrstn = '0' then
vwregs.waddr := (others =>'0');
vwregs.waddr_gray := (others =>'0');
vwregs.full := '0';
end if;
-- update fifo signals
wregsin <= vwregs;
end process;
wdomain_regs: process(wclk)
begin
if rising_edge(wclk) then
wregs <= wregsin;
end if;
end process;
------------
-- sync regs
------------
-- transfer write address (encoded) in read clock domain
-- transfer read address (encoded) in write clock domain
-- transfer empty in write clock domain
-- transfer full in read block domain
-- Note: input d is already registered in the source clock domain
syn_gen0: for i in 0 to abits generate -- fifo addresses
syncreg_inst0: syncreg generic map (tech => tech, stages => 2)
port map(clk => rclk, d => wregs.waddr_gray(i), q => waddr_sync_encoded(i));
syncreg_inst1: syncreg generic map (tech => tech, stages => 2)
port map(clk => wclk, d => rregs.raddr_gray(i), q => raddr_sync_encoded(i));
end generate;
syncreg_inst2: syncreg generic map (tech => tech, stages => 2)
port map(clk => wclk, d => rregs.empty, q => empty_sync);
syncreg_inst3: syncreg generic map (tech => tech, stages => 2)
port map(clk => rclk, d => wregs.full, q => full_sync);
-- Assign synchronized empty/full to fifo outputs
wempty <= empty_sync;
rfull <= full_sync;
wfull <= wregsin.full;
rempty <= rregsin.empty;
--------------------
-- read clock domain
--------------------
rdomain_comb: process(rregs, renable, waddr_sync_encoded, rrstn)
variable vrregs : rfifo_type;
variable vrusedw : std_logic_vector(abits-1 downto 0);
variable waddr_sync_decoded : std_logic_vector(abits downto 0);
begin
-- initialize fifo signals on read side
vrregs := rregs;
vrregs.empty := '0';
aempty <= '0';
-- fifo empty generation
gray_encoder(vrregs.raddr,vrregs.raddr_gray);
if (vrregs.raddr_gray=waddr_sync_encoded) then
vrregs.empty := '1';
end if;
-- compute and assign rusedw fifo output
gray_decoder(waddr_sync_encoded,abits,waddr_sync_decoded);
if (vrregs.raddr(abits)=waddr_sync_decoded(abits)) then
vrusedw := waddr_sync_decoded(abits-1 downto 0)-vrregs.raddr(abits-1 downto 0);
else
vrusedw := (2**abits) - (vrregs.raddr(abits-1 downto 0)-waddr_sync_decoded(abits-1 downto 0));
end if;
rusedw <= vrusedw;
-- assign almost empty
if vrusedw<pempty then
aempty <= '1';
end if;
-- read fifo
if renable = '1' then
vrregs.raddr := vrregs.raddr + 1;
end if;
-- synchronous reset
if rrstn = '0' then
vrregs.raddr := (others =>'0');
vrregs.raddr_gray := (others =>'0');
vrregs.empty := '1';
end if;
-- update fifo signals
rregsin <= vrregs;
end process;
rdomain_regs: process(rclk)
begin
if rising_edge(rclk) then
rregs <= rregsin;
end if;
end process;
-- memory instantiation
nofwft_gen: if fwft = 0 generate
ram0 : syncram_2p generic map ( tech => tech, abits => abits, dbits => dbits, sepclk => sepclk)
port map (rclk, renable, rregsin.raddr(abits-1 downto 0), dataout, wclk, write, wregsin.waddr(abits-1 downto 0), datain);
end generate;
fwft_gen: if fwft = 1 generate
ram0 : syncram_2p generic map ( tech => tech, abits => abits, dbits => dbits, sepclk => sepclk)
port map (rclk, '1', rregsin.raddr(abits-1 downto 0), dataout, wclk, write, wregs.waddr(abits-1 downto 0), datain);
end generate;
end;
|
-- user_memory module for simulation
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity user_memory is
port
(
clk: in std_logic;
reset_n: in std_logic;
cyc_i: in std_logic;
stb_i: in std_logic;
we_i: in std_logic;
sel_i: in std_logic_vector(3 downto 0);
adr_i: in std_logic_vector(MEM_ADDR_SIZE - 1 downto 0);
data_i: in word;
data_o: out word;
ack_o: out std_logic;
err_o: out std_logic
);
end user_memory;
architecture user_memory_arc of user_memory is
begin
memory: entity work.sim_memory_onchip_wb(sim_memory_onchip_wb_arc)
generic map
(
ADDR_WIDTH => MEM_ADDR_SIZE,
MEMORY_IMAGE_FILE => "program.hex",
PRINT_INITIALIZATION => false
)
port map
(
clk => clk,
reset_n => reset_n,
ack_o => ack_o,
err_o => err_o,
cyc_i => cyc_i,
stb_i => stb_i,
we_i => we_i,
sel_i => sel_i,
adr_i => adr_i,
data_i => data_i,
data_o => data_o
);
end;
|
-- user_memory module for simulation
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity user_memory is
port
(
clk: in std_logic;
reset_n: in std_logic;
cyc_i: in std_logic;
stb_i: in std_logic;
we_i: in std_logic;
sel_i: in std_logic_vector(3 downto 0);
adr_i: in std_logic_vector(MEM_ADDR_SIZE - 1 downto 0);
data_i: in word;
data_o: out word;
ack_o: out std_logic;
err_o: out std_logic
);
end user_memory;
architecture user_memory_arc of user_memory is
begin
memory: entity work.sim_memory_onchip_wb(sim_memory_onchip_wb_arc)
generic map
(
ADDR_WIDTH => MEM_ADDR_SIZE,
MEMORY_IMAGE_FILE => "program.hex",
PRINT_INITIALIZATION => false
)
port map
(
clk => clk,
reset_n => reset_n,
ack_o => ack_o,
err_o => err_o,
cyc_i => cyc_i,
stb_i => stb_i,
we_i => we_i,
sel_i => sel_i,
adr_i => adr_i,
data_i => data_i,
data_o => data_o
);
end;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_cos_s5
-- VHDL created on Tue Mar 12 15:57:58 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_cos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_cos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0);
signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0);
signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0);
signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0);
signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0);
signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0);
signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0);
signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0);
signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0);
signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0);
signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0);
signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0);
signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0);
signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0);
signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0);
signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0);
signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0);
signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0);
signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0);
signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0);
signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0);
signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0);
signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0);
signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0);
signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0);
signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0);
signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0";
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b;
--expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0
expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0);
expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0);
--R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0
R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b;
--expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0
expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0);
expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23);
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865)
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq,
address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa,
data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia
);
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184)
zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000";
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b);
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842)
-- every=1, low=0, high=1, step=1, init=1
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1));
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841)
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq,
address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa,
data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia
);
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4
fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0);
fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0);
--oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4
oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b;
--prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4
prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22)
cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011";
--expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q);
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b));
expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0);
expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0');
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq,
address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa,
data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia
);
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset;
rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4
os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q;
--prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q);
prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8
ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4
prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0);
prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0);
--reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b);
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0');
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q;
prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0);
--prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q);
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b));
prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9
multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0);
--multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b;
multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46);
--rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b;
rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14);
--reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10
ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--cstAllZwE_uid28_fpCosPiTest(CONSTANT,27)
cstAllZwE_uid28_fpCosPiTest_q <= "00000000";
--vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0);
vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0);
--mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179)
mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11";
--cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9
cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8);
--vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11
ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153)
leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000";
--vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0);
vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4);
--vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167)
leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00";
--vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0);
vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0);
--vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b)
BEGIN
CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2);
--vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1";
ELSE
vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0);
vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0);
--reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q;
vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q;
rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1);
--vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q;
vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0";
--r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12
r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q;
--biasM1_uid60_fpCosPiTest(CONSTANT,59)
biasM1_uid60_fpCosPiTest_q <= "01111110";
--expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q);
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b));
expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0);
--expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12
expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0);
expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0);
--reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0
xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q;
xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0);
xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10);
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13
finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q;
finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13
ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852)
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia
);
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146)
ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000";
--fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14
fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q;
--LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13
leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q;
--X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0);
X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0);
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923)
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9
ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305)
leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12
leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0);
X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0);
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922)
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9
ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12
leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0);
X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0);
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921)
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9
ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12
leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924)
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9
ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q;
leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3);
--leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b;
leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q;
WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0);
--leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316)
leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000";
--leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12
leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q;
--reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12
leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12
leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q;
leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q;
WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q;
WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q;
leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13
fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0);
fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25);
--reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1
ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14
finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q;
finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q)
BEGIN
CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS
WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q;
WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q;
WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14
RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q;
--expXRR_uid34_fpCosPiTest(BITSELECT,33)@14
expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0);
expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50);
--cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000";
--cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14
cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q;
cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0';
cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0);
cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b));
cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11);
--exp_uid11_fpCosPiTest(BITSELECT,10)@0
exp_uid11_fpCosPiTest_in <= a(30 downto 0);
exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23);
--cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0
cosXIsOne_uid36_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0';
cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0);
cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b));
cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10);
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14
cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q;
cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n;
cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b;
--ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14
ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17
InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q;
InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXOne_uid92_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a;
END IF;
END PROCESS;
--X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15
X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0);
X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0);
--leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159)
leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15
leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15
X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0);
X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0);
--leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15
leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q;
--X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15
X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0);
X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0);
--leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15
leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000";
--fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14
fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0);
fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0);
--ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14
ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15
oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q;
--extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15
extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q;
--fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14
fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b);
fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q);
fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b));
fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0);
--fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14
fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0);
fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b;
leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0);
LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0);
--ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15
ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170)
leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000";
--leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16
leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0);
--ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15
ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16
leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0);
LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0);
--ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15
ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16
leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14
ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q;
leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid44_fpCosPiTest(BITSELECT,43)@16
y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0);
y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1);
--ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16
ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 2 )
PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid49_fpCosPiTest(BITJOIN,48)@16
pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid49_fpCosPiTest(SUB,49)@17
oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q);
oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q);
oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b));
oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0);
--reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18
cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q;
cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0';
cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0);
cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b));
cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67);
--InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18
InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a;
--intXParity_uid43_fpCosPiTest(BITSELECT,42)@16
intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q;
intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64);
--ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16
ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17
yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0";
--ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17
ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18
InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q;
InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a;
--signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18
signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid95_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18
InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q;
InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a;
--signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18
signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c;
signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q;
signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid100_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d;
END IF;
END IF;
END PROCESS;
--signR_uid101_fpCosPiTest(LOGICAL,100)@19
signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q;
signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q;
signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b;
--cstAllZWF_uid7_fpCosPiTest(CONSTANT,6)
cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000";
--frac_uid13_fpCosPiTest(BITSELECT,12)@0
frac_uid13_fpCosPiTest_in <= a(22 downto 0);
frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b;
fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q;
fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0";
--cstAllOWE_uid6_fpCosPiTest(CONSTANT,5)
cstAllOWE_uid6_fpCosPiTest_q <= "11111111";
--expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b;
expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q;
expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0";
--exc_I_uid15_fpCosPiTest(LOGICAL,14)@0
exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q;
exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b;
--ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0
ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18
InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q;
InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid102_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q;
InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a;
--exc_N_uid17_fpCosPiTest(LOGICAL,16)@0
exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q;
exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b;
--InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0
InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid103_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a;
END IF;
END PROCESS;
--ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1
ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19
signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q;
signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q;
signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c;
--ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19
ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpCosPiTest(CONSTANT,21)
cstBias_uid22_fpCosPiTest_q <= "01111111";
--oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17
oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0);
oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0);
--reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18
ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid54_fpCosPiTest(BITSELECT,53)@16
yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0);
yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0);
--reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17
ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 62, depth => 2 )
PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--z_uid55_fpCosPiTest(MUX,54)@19
z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q;
z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q)
BEGIN
CASE z_uid55_fpCosPiTest_s IS
WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q;
WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q;
WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@19
zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20
memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19
zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36);
--yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19
yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5);
--reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925)
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20
ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23
prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b);
prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0');
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q;
prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q;
prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26
highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b;
highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1);
--ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20
ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23
memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q;
memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26
sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q);
sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b);
sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b));
sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26
lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0);
--s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26
s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b;
--reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927)
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27
prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b);
prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0');
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q;
prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q;
prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30
highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b;
highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940)
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27
memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30
sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q);
sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b);
sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b));
sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30
lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0);
--s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30
s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b;
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30
fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5);
--reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0";
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0);
X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0);
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900)
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 1,
numwords_a => 2,
width_b => 14,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0);
--leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220)
leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23
leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19
vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0);
vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0);
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889)
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0);
--zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23
leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b;
--X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0);
X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0);
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878)
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia
);
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23
leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b);
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b;
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911)
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0);
--rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19
rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q;
rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30);
--vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19
vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b;
vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q;
vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20
ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20
cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q;
--ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19
ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20
vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q)
BEGIN
CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20
rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16);
--vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20
vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q;
vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0";
--reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21
ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20
vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0);
vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0);
--vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20
vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20
rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21
vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q;
vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0";
--ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21
ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20
vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0);
vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21
vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q;
WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21
rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4);
--vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21
vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1";
ELSE
vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21
vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0);
--reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22
vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22
rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2);
--vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22
vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0";
--vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22
vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0);
--vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22
vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q;
vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b)
BEGIN
CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS
WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b;
WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22
rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q;
rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1);
--vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22
vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b;
vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q;
vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0";
--r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22
r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q;
--leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0);
LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0);
--ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23
ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24
leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0);
LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0);
--ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23
ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24
leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q;
--LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0);
LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0);
--ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23
ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24
leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q;
--reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22
ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24
ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25
leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0);
LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0);
--ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24
ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25
leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q;
--LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24
ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25
leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22
ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q;
leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q;
WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--p_uid59_fpCosPiTest(BITSELECT,58)@25
p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q;
p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36);
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954)
-- every=1, low=0, high=2, step=1, init=1
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2));
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953)
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq,
address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa,
data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia
);
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset;
ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0);
--reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31
mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q;
mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q;
mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@34
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q;
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51);
--rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815)
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0);
--expHardCase_uid61_fpCosPiTest(SUB,60)@33
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@33
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0);
--reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--highRes_uid70_fpCosPiTest(BITSELECT,69)@34
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@34
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34
expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q;
--expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q);
expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b));
expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@34
expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24);
--reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b);
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0";
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b;
--ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0
ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14
ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16
InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q;
InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a;
END IF;
END PROCESS;
--InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0
InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n;
InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a;
--ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0
ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45)
cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000";
--half_uid47_fpCosPiTest(BITJOIN,46)@17
half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q;
--yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17
yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q;
yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q;
yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0";
--yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17
yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q;
yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q;
yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c;
--excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0
excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q;
excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b;
--ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0
ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid86_fpCosPiTest(BITJOIN,85)@17
join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
--expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17
expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q;
--reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--expSelector_uid88_fpCosPiTest(LOOKUP,87)@18
expSelector_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelector_uid88_fpCosPiTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS
WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01";
WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11";
WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10";
WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00";
WHEN OTHERS =>
expSelector_uid88_fpCosPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829)
-- every=1, low=0, high=13, step=1, init=1
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13;
ELSE
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4));
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828)
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0);
--expRPostExc_uid90_fpCosPiTest(MUX,89)@35
expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid90_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q;
WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid30_fpCosPiTest(CONSTANT,29)
cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34
fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b);
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b;
--reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15
ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q;
END IF;
END IF;
END PROCESS;
--excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18
excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q;
excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q;
excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q;
excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c;
--join_uid84_fpCosPiTest(BITJOIN,83)@18
join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q;
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966)
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid85_fpCosPiTest(MUX,84)@35
fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q;
fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid85_fpCosPiTest_s IS
WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q;
WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q;
WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cosXR_uid105_fpCosPiTest(BITJOIN,104)@35
cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q;
--xOut(GPOUT,4)@35
q <= cosXR_uid105_fpCosPiTest_q;
end normal;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:49:30 01/16/2015
-- Design Name:
-- Module Name: DualPortBRAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use ieee.std_logic_unsigned.all;
entity DualPortBRAM is
port (CLK : in std_logic;
WE : in std_logic;
EN : in std_logic;
ADDRW : in std_logic_vector(7 downto 0);
ADDRR : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(0 downto 0);
DO : out std_logic_vector(0 downto 0));
end DualPortBRAM;
architecture Behavioral of DualPortBRAM is
constant ADDR_WIDTH : integer := 8;
constant DATA_WIDTH : integer := 1;
type DPBRAM is array (2**ADDR_WIDTH-1 downto 0) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal BRAM: DPBRAM;
begin
process (CLK)
begin
if (CLK'event and CLK = '1') then
if (EN = '1') then
if (WE = '1') then
BRAM(conv_integer(ADDRW)) <= DI;
end if;
--<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
DO <= BRAM(conv_integer(ADDRR));
end if;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity CPU is
port(
clk: in std_logic;
Overflow: out std_logic
);
end CPU;
architecture Behavioral of CPU is
component PC
port(
clk: in std_logic;
AddressIn: in std_logic_vector(31 downto 0);
AddressOut: out std_logic_vector(31 downto 0)
);
end component;
component Add
port(
x: in std_logic_vector(31 downto 0);
y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component SignExtend
port(
x: in std_logic_vector(15 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2
port(
x: in std_logic_vector(31 downto 0);
y: out std_logic_vector(31 downto 0)
);
end component;
component ShiftLeft2Jump
port(
x: in std_logic_vector(25 downto 0);
y: in std_logic_vector(3 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
component Mux5
port(
x, y: in std_logic_vector (4 downto 0);
sel: in std_logic;
z :out std_logic_vector(4 downto 0)
);
end component;
component Mux32
port(
x, y: in std_logic_vector (31 downto 0);
sel: in std_logic;
z: out std_logic_vector(31 downto 0)
);
end component;
component And2
port(
a, b: in std_logic;
y: out std_logic
);
end component;
component ALU
generic(
n: natural := 32
);
port(
a, b: in std_logic_vector(n-1 downto 0);
Oper: in std_logic_vector(3 downto 0);
Result: buffer std_logic_vector(n-1 downto 0);
Zero, CarryOut, Overflow: buffer std_logic
);
end component;
component Registers
port(
RR1, RR2, WR: in std_logic_vector(4 downto 0);
WD: in std_logic_vector(31 downto 0);
RegWrite, Clk: in std_logic;
RD1, RD2: out std_logic_vector(31 downto 0)
);
end component;
component InstructionMemory
port (
Address: in std_logic_vector(31 downto 0);
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component DataMemory
port(
WriteData: in std_logic_vector(31 downto 0);
Address: in std_logic_vector(31 downto 0);
Clk, MemRead, MemWrite: in std_logic;
ReadData: out std_logic_vector(31 downto 0)
);
end component;
component ALUControl
port(
ALUOp: in std_logic_vector(1 downto 0);
Funct: in std_logic_vector(5 downto 0);
Operation: out std_logic_vector(3 downto 0)
);
end component;
component Control
port(
Opcode: in std_logic_vector(5 downto 0);
RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump: out std_logic;
ALUOp: out std_logic_vector(1 downto 0)
);
end component;
signal RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, R, Zero, CarryOut: std_logic := '0';
signal AlUOp: std_logic_vector(1 downto 0) := "00";
signal Operation: std_logic_vector(3 downto 0) := "0000";
signal B: std_logic_vector(4 downto 0) := "00000";
signal A, C, D, E, F, G, H, J, L, K, M, N, P, Q, Instruction: std_logic_vector(31 downto 0) := X"00000000";
begin
PC_instance: PC port map(clk, P, A);
Add_instance_0: Add port map(A, X"00000004", L);
Add_instance_1: Add port map(L, K, M);
SignExtend_instance: SignExtend port map(Instruction(15 downto 0), E);
ShiftLeft2_instance: ShiftLeft2 port map(E, K);
ShiftLeft2Jump_instance: ShiftLeft2Jump port map(Instruction(25 downto 0), L(31 downto 28), Q);
Mux5_instance: Mux5 port map(Instruction(20 downto 16), Instruction(15 downto 11), RegDst, B);
Mux32_instance_0: Mux32 port map(L, M, R, N);
Mux32_instance_1: Mux32 port map(N, Q, Jump, P);
Mux32_instance_2: Mux32 port map(D, E, ALUSrc, F);
Mux32_instance_3: Mux32 port map(G, H, MemToReg, J);
And2_instance: And2 port map(Branch, Zero, R);
ALU_instance: ALU port map(C, F, Operation, G, Zero, CarryOut, Overflow);
Registers_instance: Registers port map(Instruction(25 downto 21), Instruction(20 downto 16), B, J, RegWrite, clk, C, D);
InstructionMemory_instance: InstructionMemory port map(A, Instruction);
DataMemory_instance: DataMemory port map(D, G, clk, MemRead, MemWrite, H);
ALUControl_instance: ALUControl port map(ALUOp, Instruction(5 downto 0), Operation);
Control_instance: Control port map(Instruction(31 downto 26), RegDst, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Jump, ALUOp);
end Behavioral;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Cache Core (SRAMs), 1 read port, 1 write port
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
entity cache_core_1r1w is
generic (
log2_assoc : natural := 0;
word_bits : natural := 1;
index_bits : natural := 1;
offset_bits : natural := 0;
tag_bits : natural := 1;
write_first : boolean := true
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
we : in std_ulogic;
wway : in std_ulogic_vector(2**log2_assoc-1 downto 0);
wtagen : in std_ulogic;
wdataen : in std_ulogic;
windex : in std_ulogic_vector(index_bits-1 downto 0);
woffset : in std_ulogic_vector(offset_bits-1 downto 0);
wtag : in std_ulogic_vector(tag_bits-1 downto 0);
wdata : in std_ulogic_vector(word_bits-1 downto 0);
re : in std_ulogic;
rway : in std_ulogic_vector(2**log2_assoc-1 downto 0);
rtagen : in std_ulogic;
rdataen : in std_ulogic;
rindex : in std_ulogic_vector(index_bits-1 downto 0);
roffset : in std_ulogic_vector(offset_bits-1 downto 0);
rtag : out std_ulogic_vector2(2**log2_assoc-1 downto 0, tag_bits-1 downto 0);
rdata : out std_ulogic_vector2(2**log2_assoc-1 downto 0, word_bits-1 downto 0)
);
end;
|
-----------------------------------------------------------------------------------
-- Created by Sam Rohrer --
-- Beamforms in the nearfield based on a generic for distance --
-- Accesses memory for test data --
-- Uses cellular RAM --
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity mem_access is
port(
o_datain_r : out std_logic_vector (7 downto 0); -- 8 bit from memory
o_datain_l : out std_logic_vector (7 downto 0); -- 8 bit from memory
o_addressbus : out std_logic_vector (26 downto 1);
i_databus : in std_logic_vector (15 downto 0);
i_sampleclock : in std_logic;
i_clock : in std_logic;
i_reset : in std_logic
);
end mem_access;
architecture Behavioral of mem_access is
signal clockpulses : integer ;
signal counter : std_logic_vector (24 downto 0);
signal channel_select : std_logic;
begin
--*******************************************************--
data_access: process (i_sampleclock, i_reset, clockpulses)
begin
if (i_reset = '1') then
channel_select <= '0';
o_addressbus <= (others => '0');
o_datain_r <= X"00";
o_datain_l <= X"00";
counter <= (others => '0');
elsif (clockpulses = 0) then
channel_select <= '0';
o_addressbus <= channel_select & counter;
elsif (clockpulses = 75) then
o_datain_r <= i_databus (7 downto 0);
elsif (clockpulses = 100) then
channel_select <= '1';
o_addressbus <= channel_select & counter;
elsif (clockpulses = 175) then
channel_select <= '0';
o_addressbus <= channel_select & counter;
elsif (clockpulses = 275) then
o_datain_l <= i_databus (7 downto 0);
elsif (rising_edge(i_sampleclock)) then
counter <= counter + '1';
elsif (counter = "1111111111111111111111111") then
counter <= (others => '0');
end if;
end process;
--*******************************************************--
clkpulses_counter: process (i_clock, i_reset, i_sampleclock)
begin
if (i_reset = '1') then
clockpulses <= 0;
elsif (rising_edge(i_clock)) then
clockpulses <= clockpulses + 1;
end if;
if (rising_edge(i_sampleclock)) then
clockpulses <= 0;
end if;
end process;
--*******************************************************--
end Behavioral; |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_McEliece_QD-Goppa_Decrypt_v4
-- Module Name: Tb_McEliece_QD-Goppa_Decrypt_v4
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This test bench tests mceliece_qd_goppa_decrypt_v4 circuit.
-- The test is done only for one value loaded into memories, and in the end the output
-- memories are verified.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_polynomial_evaluator_syndrome_pipelines :
--
-- The number of pipelines in polynomial_syndrome_computing_n circuit.
-- This number can be 1 or greater, but only power of 2.
--
-- log2_number_of_polynomial_evaluator_syndrome_pipelines :
--
-- This is the log2 of the number_of_polynomial_evaluator_syndrome_pipelines.
-- This is ceil(log2(number_of_polynomial_evaluator_syndrome_pipelines))
--
-- polynomial_evaluator_syndrome_pipeline_size :
--
-- This is the number of stages on polynomial_syndrome_computing_n circuit.
-- This number can be 2 or greater.
--
-- polynomial_evaluator_syndrome_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(polynomial_evaluator_syndrome_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
-- file_memory_L :
--
-- This file stores the private key, support elements L.
--
-- file_memory_h :
--
-- This file stores the private key, the inverted evaluation of all support elements L
-- into polynomial g, aka g(L)^(-1)
--
-- file_memory_codeword :
--
-- This file stores the ciphertext that will be decrypted.
--
-- file_memory_message :
--
-- This file stores the plaintext obtained by decrypting the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- file_memory_error :
--
-- This file stores the error array added to the codeword to transform into the ciphertext.
-- This is necessary to verify if the circuit decrypted correctly the ciphertext.
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- mceliece_qd_goppa_decrypt_with_mem_v4 Rev 1.0
-- ram_bank Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity tb_mceliece_qd_goppa_decrypt_v4_with_mem is
Generic(
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
polynomial_evaluator_syndrome_pipeline_size : integer := 2;
polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
gf_2_m : integer range 1 to 20 := 6;
length_codeword : integer := 52;
size_codeword : integer := 6;
number_of_errors : integer := 4;
size_number_of_errors : integer := 3;
file_memory_L : string := "mceliece/data_tests/L_qdgoppa_52_28_4_6.dat";
file_memory_h : string := "mceliece/data_tests/h_qdgoppa_52_28_4_6.dat";
file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_52_28_4_6.dat";
file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
file_memory_error : string := "mceliece/data_tests/error_qdgoppa_52_28_4_6.dat"
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1751_27_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1751_27_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1751_27_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1751_27_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1751_27_11.dat"
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_2048_1498_50_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_2048_1498_50_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_2048_1498_50_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_2048_1498_50_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_2048_1498_50_11.dat"
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_goppa_3307_2515_66_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_goppa_3307_2515_66_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_goppa_3307_2515_66_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_goppa_3307_2515_66_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_goppa_3307_2515_66_12.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2528_2144_32_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2528_2144_32_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [1792, 1088, 64, 11] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 1792;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_1792_1088_64_11.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_1792_1088_64_11.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_1792_1088_64_11.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_1792_1088_64_11.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_1792_1088_64_11.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_2816_2048_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_2816_2048_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [4096, 2048, 128, 16] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 16;
-- length_codeword : integer := 4096;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_4096_2048_128_16.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_4096_2048_128_16.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_4096_2048_128_16.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_4096_2048_128_16.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_4096_2048_128_16.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_3328_2560_64_12.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_3328_2560_64_12.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [6144, 2560, 256, 14] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 14;
-- length_codeword : integer := 6144;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 256;
-- size_number_of_errors : integer := 9;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_6144_2560_256_14.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_6144_2560_256_14.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_6144_2560_256_14.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_6144_2560_256_14.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_6144_2560_256_14.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_polynomial_evaluator_syndrome_pipelines : integer := 1;
-- log2_number_of_polynomial_evaluator_syndrome_pipelines : integer := 0;
-- polynomial_evaluator_syndrome_pipeline_size : integer := 2;
-- polynomial_evaluator_syndrome_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8;
-- file_memory_L : string := "mceliece/data_tests/L_qdgoppa_7296_5632_128_13.dat";
-- file_memory_h : string := "mceliece/data_tests/h_qdgoppa_7296_5632_128_13.dat";
-- file_memory_codeword : string := "mceliece/data_tests/ciphertext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_message : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- file_memory_error : string := "mceliece/data_tests/error_qdgoppa_7296_5632_128_13.dat"
);
end tb_mceliece_qd_goppa_decrypt_v4_with_mem;
architecture Behavioral of tb_mceliece_qd_goppa_decrypt_v4_with_mem is
component mceliece_qd_goppa_decrypt_v4_with_mem
Generic(
number_of_polynomial_evaluator_syndrome_pipelines : integer;
log2_number_of_polynomial_evaluator_syndrome_pipelines : integer;
polynomial_evaluator_syndrome_pipeline_size : integer;
polynomial_evaluator_syndrome_size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
number_of_errors : integer;
size_number_of_errors : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
load_address_mem : in STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
load_sel_mem : in STD_LOGIC_VECTOR(1 downto 0);
load_write_value_mem : in STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
load_write_enable_mem : in STD_LOGIC;
load_read_value_mem : out STD_LOGIC_VECTOR((2*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal load_address_mem : STD_LOGIC_VECTOR((size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal load_sel_mem : STD_LOGIC_VECTOR(1 downto 0);
signal load_write_value_mem : STD_LOGIC_VECTOR((gf_2_m*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal load_write_enable_mem : STD_LOGIC;
signal load_read_value_mem : STD_LOGIC_VECTOR((2*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal syndrome_generation_finalized : STD_LOGIC;
signal key_equation_finalized : STD_LOGIC;
signal decryption_finalized : STD_LOGIC;
signal true_value_error : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal true_value_message : STD_LOGIC_VECTOR((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal true_address_value_error_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal true_value_error_message : STD_LOGIC_VECTOR((2*number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0);
signal error_value_error_message : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
pure function read_value_file (file memory_file : text; constant word_size : integer; constant number_of_words : integer) return STD_LOGIC_VECTOR is
variable line_n : line;
variable value_buffer : std_logic_vector((number_of_words*word_size - 1) downto 0);
variable file_read_buffer : std_logic_vector((word_size - 1) downto 0);
variable value_buffer_amount : integer;
begin
value_buffer_amount := 0;
while ((value_buffer_amount /= (word_size*number_of_words)) and (not endfile(memory_file))) loop
readline (memory_file, line_n);
read (line_n, file_read_buffer);
value_buffer((value_buffer_amount + word_size - 1) downto value_buffer_amount) := file_read_buffer;
value_buffer_amount := value_buffer_amount + word_size;
end loop;
while (value_buffer_amount /= (word_size*number_of_words)) loop
value_buffer((value_buffer_amount + word_size - 1) downto value_buffer_amount) := (others => '0');
value_buffer_amount := value_buffer_amount + word_size;
end loop;
return value_buffer;
end function;
begin
test : mceliece_qd_goppa_decrypt_v4_with_mem
Generic Map(
number_of_polynomial_evaluator_syndrome_pipelines => number_of_polynomial_evaluator_syndrome_pipelines,
log2_number_of_polynomial_evaluator_syndrome_pipelines => log2_number_of_polynomial_evaluator_syndrome_pipelines,
polynomial_evaluator_syndrome_pipeline_size => polynomial_evaluator_syndrome_pipeline_size,
polynomial_evaluator_syndrome_size_pipeline_size => polynomial_evaluator_syndrome_size_pipeline_size,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
number_of_errors => number_of_errors,
size_number_of_errors => size_number_of_errors
)
Port Map(
clk => clk,
rst => rst,
load_address_mem => load_address_mem,
load_sel_mem => load_sel_mem,
load_write_value_mem => load_write_value_mem,
load_write_enable_mem => load_write_enable_mem,
load_read_value_mem => load_read_value_mem,
syndrome_generation_finalized => syndrome_generation_finalized,
key_equation_finalized => key_equation_finalized,
decryption_finalized => decryption_finalized
);
true_mem_message : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_message,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_value_error_message,
rst_value => (others => '0'),
data_out => true_value_message
);
true_mem_error : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => number_of_polynomial_evaluator_syndrome_pipelines,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => file_memory_error,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => true_address_value_error_message,
rst_value => (others => '0'),
data_out => true_value_error
);
true_value_error_message <= true_value_error & true_value_message;
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
process
FILE memory_L : text is in file_memory_L;
FILE memory_h : text is in file_memory_h;
FILE memory_codeword : text is in file_memory_codeword;
variable i : integer;
variable loading_cycle_count : integer range 0 to 2000000000 := 0;
variable syndrome_cycle_count : integer range 0 to 2000000000 := 0;
variable key_equation_cycle_count : integer range 0 to 2000000000 := 0;
variable correct_errors_cycle_count : integer range 0 to 2000000000 := 0;
begin
true_address_value_error_message <= (others => '0');
rst <= '1';
error_value_error_message <= '0';
wait for PERIOD*2;
i := 0;
load_sel_mem <= "00"; -- Load private key L
while (i < (length_codeword)) loop
load_address_mem <= std_logic_vector(to_unsigned(i/number_of_polynomial_evaluator_syndrome_pipelines, size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines));
load_write_value_mem <= read_value_file(memory_L, gf_2_m, number_of_polynomial_evaluator_syndrome_pipelines);
load_write_enable_mem <= '0';
wait for PERIOD;
load_write_enable_mem <= '1';
i := i + number_of_polynomial_evaluator_syndrome_pipelines;
wait for PERIOD;
end loop;
load_write_enable_mem <= '0';
file_close(memory_L);
wait for PERIOD*2;
i := 0;
load_sel_mem <= "01"; -- Load private key h
while (i < (length_codeword)) loop
load_address_mem <= std_logic_vector(to_unsigned(i/number_of_polynomial_evaluator_syndrome_pipelines, size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines));
load_write_value_mem <= read_value_file(memory_h, gf_2_m, number_of_polynomial_evaluator_syndrome_pipelines);
load_write_enable_mem <= '0';
wait for PERIOD;
load_write_enable_mem <= '1';
i := i + number_of_polynomial_evaluator_syndrome_pipelines;
wait for PERIOD;
end loop;
load_write_enable_mem <= '0';
file_close(memory_h);
wait for PERIOD*2;
i := 0;
load_write_value_mem <= (others => '0');
load_sel_mem <= "10"; -- Load ciphertext
while (i < (length_codeword)) loop
load_address_mem <= std_logic_vector(to_unsigned(i/number_of_polynomial_evaluator_syndrome_pipelines, size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines));
load_write_value_mem((number_of_polynomial_evaluator_syndrome_pipelines - 1) downto 0) <= read_value_file(memory_codeword, 1, number_of_polynomial_evaluator_syndrome_pipelines);
load_write_enable_mem <= '0';
wait for PERIOD;
load_write_enable_mem <= '1';
i := i + number_of_polynomial_evaluator_syndrome_pipelines;
wait for PERIOD;
end loop;
load_write_enable_mem <= '0';
file_close(memory_codeword);
wait for PERIOD*2;
rst <= '0';
loading_cycle_count := cycle_count;
wait until syndrome_generation_finalized = '1';
syndrome_cycle_count := cycle_count - loading_cycle_count;
report "Circuit finish Syndrome = " & integer'image(syndrome_cycle_count/2) & " cycles";
wait until key_equation_finalized = '1';
key_equation_cycle_count := cycle_count - syndrome_cycle_count - loading_cycle_count;
report "Circuit finish Key Equation = " & integer'image(key_equation_cycle_count/2) & " cycles";
wait until decryption_finalized = '1';
correct_errors_cycle_count := cycle_count - key_equation_cycle_count - syndrome_cycle_count - loading_cycle_count;
report "Circuit finish Correct Errors = " & integer'image(correct_errors_cycle_count/2) & " cycles";
report "Circuit finish = " & integer'image((cycle_count - loading_cycle_count)/2) & " cycles";
wait for PERIOD;
i := 0;
load_sel_mem <= "11";
rst <= '1';
wait for PERIOD;
while (i < (length_codeword)) loop
true_address_value_error_message(size_codeword - 1 downto 0) <= std_logic_vector(to_unsigned(i, size_codeword));
load_address_mem <= std_logic_vector(to_unsigned(i/number_of_polynomial_evaluator_syndrome_pipelines, size_codeword - log2_number_of_polynomial_evaluator_syndrome_pipelines));
wait for (PERIOD*3);
if (true_value_error_message = load_read_value_mem) then
error_value_error_message <= '0';
else
error_value_error_message <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
error_value_error_message <= '0';
wait for PERIOD;
i := i + number_of_polynomial_evaluator_syndrome_pipelines;
end loop;
wait for PERIOD;
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Alternate between the outputs of the two interleaved filters.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1281_filter_output is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- 1st MAC result
data1_i : in signed(23 downto 0);
data1_en_i : in std_ulogic;
-- 2nd MAC result
data2_i : in signed(23 downto 0);
data2_en_i : in std_ulogic;
-- Filter output
data_o : out std_ulogic_vector(23 downto 0);
data_en_o : out std_ulogic);
end entity ads1281_filter_output;
architecture rtl of ads1281_filter_output is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal data : signed(23 downto 0);
signal data_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= std_ulogic_vector(data);
data_en_o <= data_en;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
data <= to_signed(0, data'length);
data_en <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
if data1_en_i = '1' then
data <= data1_i;
elsif data2_en_i = '1' then
data <= data2_i;
end if;
data_en <= data1_en_i xor data2_en_i;
end if;
end if;
end process regs;
end architecture rtl;
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity one_wire_tb is
end entity;
architecture rtl of one_wire_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
constant TX_TEST_DATA : std_logic_vector(7 downto 0) := "10101010";
constant RX_TEST_DATA : std_logic_vector(7 downto 0) := "10101010";
signal clk : std_logic := '0';
signal reset : std_logic;
signal reset_ow : std_logic;
signal ow_in : std_logic;
signal ow_out : std_logic;
signal ow_n_out : std_logic;
signal data : std_logic_vector(8 - 1 downto 0);
signal data_f : std_logic;
signal receive_data_f : std_logic;
signal busy : std_logic;
signal data_out : std_logic_vector(8 - 1 downto 0);
signal data_out_f : std_logic;
-- Signals internal to the test bench, not related to DUT
signal reset_done : std_logic;
signal send_done : std_logic;
signal receive_done : std_logic;
begin
-- Invert the output signal coming from the 1-wire module for display
ow_out <= not ow_n_out;
DUT_inst: entity work.one_wire(rtl)
generic map
(
US_D => 100
)
port map
(
clk => clk,
reset => reset,
reset_ow => reset_ow,
ow_in => ow_in,
data_in => data,
data_in_f => data_f,
receive_data_f => receive_data_f,
ow_out => ow_n_out,
busy_out => busy,
data_out => data_out,
data_out_f => data_out_f
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
-- TODO: Change all these processes to a single state machine!
-- Generate a reset pulse on the 1-wire bus once reset is done
ow_reset_gen: process(clk, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
reset_ow <= '0';
elsif rising_edge(clk) then
reset_ow <= '0';
if done = '0' then
reset_ow <= '1';
done := '1';
end if;
end if;
end process;
-- Pull up flag after reset is sent to the bus (bus is not busy anymore)
ow_reset_done_gen: process(busy, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
reset_done <= '0';
elsif falling_edge(busy) then
if done = '0' then
reset_done <= '1';
done := '1';
end if;
end if;
end process;
-- Send data on OW bus after reset is done
ow_tx_data_gen: process(reset_done, clk, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
data <= (others => '0');
data_f <= '0';
elsif rising_edge(reset_done) then
data <= TX_TEST_DATA;
data_f <= '1';
elsif rising_edge(clk) then
data_f <= '0';
end if;
end process;
-- Pull up flag after done sending data to the bus (bus is not busy anymore)
ow_send_done_gen: process(busy, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
send_done <= '0';
elsif falling_edge(busy) then
if done = '0' and reset_done = '1' then
send_done <= '1';
done := '1';
end if;
end if;
end process;
-- Pull up a flag to indicate we want to receive data from the OW bus
ow_rx_f_gen: process(send_done, clk, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
receive_data_f <= '0';
elsif rising_edge(send_done) then
if done = '0' then
receive_data_f <= '1';
done := '1';
end if;
elsif rising_edge(clk) then
receive_data_f <= '0';
end if;
end process;
-- Send data to OW module after sending is done
ow_rx_data_gen: process(send_done, ow_out, reset)
variable done : std_logic;
variable sending : std_logic;
variable index : natural;
begin
if reset = '1' then
done := '0';
sending := '0';
ow_in <= '0';
index := 0;
elsif rising_edge(send_done) then
-- Only start sending after TX test is done
sending := '1';
elsif rising_edge(ow_out) then
if sending = '1' then
index := index + 1;
if index = 7 then
ow_in <= RX_TEST_DATA(index);
sending := '0';
done := '1';
else
ow_in <= RX_TEST_DATA(index);
end if;
end if;
end if;
end process;
-- Pull up flag after done sending data to the bus (bus is not busy anymore)
ow_receive_done_gen: process(busy, reset)
variable done : std_logic;
begin
if reset = '1' then
done := '0';
receive_done <= '0';
elsif falling_edge(busy) then
if done = '0' and send_done = '1' then
receive_done <= '1';
done := '1';
end if;
end if;
end process;
-- Assert received data is correct
ow_rx_data_assert: process(data_out_f)
begin
if data_out_f = '1' then
assert data_out = RX_TEST_DATA report "RX data does not match!"
severity warning;
end if;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library work;
use work.all;
entity AESL_autobus_indices_samples is
generic (
constant TV_IN : STRING (1 to 76) := "../tv/cdatafile/c.nfa_accept_samples_generic_hw.autotvin_indices_samples.dat";
constant TV_OUT : STRING (1 to 81) := "../tv/rtldatafile/rtl.nfa_accept_samples_generic_hw.autotvout_indices_samples.dat";
constant DATA_WIDTH : INTEGER := 16;
constant ADDR_WIDTH : INTEGER := 32;
constant DEPTH : INTEGER := 10;
constant FIFO_DEPTH : INTEGER := 32;
constant FIFO_DEPTH_ADDR_WIDTH : INTEGER := 32
);
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
bus_req_RW : IN STD_LOGIC;
bus_req_full_n : OUT STD_LOGIC;
bus_req_RW_en : IN STD_LOGIC;
bus_rsp_empty_n : OUT STD_LOGIC;
bus_rsp_read : IN STD_LOGIC;
bus_address : IN STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0);
bus_din : IN STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_dout : OUT STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
bus_size : IN STD_LOGIC_VECTOR ( 31 downto 0);
ready : IN STD_LOGIC;
done : IN STD_LOGIC
);
end AESL_autobus_indices_samples;
architecture behav of AESL_autobus_indices_samples is
-- Inner signals
signal FIFO_req_ptr_r : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_ptr_w : STD_LOGIC_VECTOR (FIFO_DEPTH_ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_req_flag : STD_LOGIC := '0'; -- 0: empty hint, 1: full hint
signal FIFO_req_empty : STD_LOGIC := '0';
signal FIFO_req_full : STD_LOGIC := '0';
signal FIFO_req_read : STD_LOGIC := '0';
signal FIFO_req_burst_flag:STD_LOGIC := '0';
signal FIFO_rsp_ptr_r : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_ptr_w : STD_LOGIC_VECTOR (ADDR_WIDTH - 1 downto 0) := (others => '0');
signal FIFO_rsp_flag : STD_LOGIC := '0';
signal FIFO_rsp_empty : STD_LOGIC;
signal FIFO_rsp_full : STD_LOGIC;
signal FIFO_rsp_write : STD_LOGIC;
signal FIFO_req_temp_state : STD_LOGIC_VECTOR(1 downto 0) := "00";
type arr_fifo_req_RW is array(0 to FIFO_DEPTH - 1) of STD_LOGIC;
type arr_fifo_req_addr is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
type arr_fifo_req_din is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
type arr_fifo_req_size is array(0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(31 downto 0);
type arr_mem is array(0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable FIFO_req_RW : arr_fifo_req_RW;
shared variable FIFO_req_address: arr_fifo_req_addr;
shared variable FIFO_req_din : arr_fifo_req_din;
shared variable FIFO_req_size : arr_fifo_req_size;
shared variable mem : arr_mem := (others => (others => '0'));
shared variable FIFO_rsp_mem : arr_mem := (others => (others => '0'));
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_sub(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) - unsigned(v2);
return std_logic_vector(res);
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := '0';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := '0';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := '0';
end case;
end if;
end loop;
return ret;
end function;
begin
-------------- Assignment for output port -------------------
assign_proc : process
begin
wait until (clk'event and clk = '1');
wait for 0.4 ns;
bus_dout <= FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_r));
end process;
bus_rsp_proc : process(FIFO_rsp_empty)
begin
bus_rsp_empty_n <= not FIFO_rsp_empty;
end process;
bus_req_full_n_proc : process(FIFO_req_full)
begin
bus_req_full_n <= not FIFO_req_full;
end process;
FIFO_req_empty_full_proc : process(FIFO_req_ptr_r, FIFO_req_ptr_w, FIFO_req_flag)
begin
if(FIFO_req_ptr_r = FIFO_req_ptr_w) then
if(FIFO_req_flag = '1') then
FIFO_req_full <= '1';
FIFO_req_empty <= '0';
else
FIFO_req_full <= '0';
FIFO_req_empty <= '1';
end if;
else
FIFO_req_full <= '0';
FIFO_req_empty <= '0';
end if;
end process;
FIFO_rsp_empty_full_proc : process(FIFO_rsp_ptr_r, FIFO_rsp_ptr_w, FIFO_rsp_flag)
begin
if(FIFO_rsp_ptr_r = FIFO_rsp_ptr_w) then
if(FIFO_rsp_flag = '1') then
FIFO_rsp_full <= '1';
FIFO_rsp_empty <= '0';
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '1';
end if;
else
FIFO_rsp_full <= '0';
FIFO_rsp_empty <= '0';
end if;
end process;
-- Push RTL's req into FIFO_req
FIFO_req_write_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_req_ptr_w <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_req_RW_en = '1' and FIFO_req_full = '0') then
FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_w)) := bus_req_RW;
FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_w)) := bus_address;
FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_w)) := bus_din;
FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_w)) := bus_size;
if(CONV_INTEGER(FIFO_req_ptr_w) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_w <= esl_add(FIFO_req_ptr_w,"1");
else
FIFO_req_ptr_w <= (others => '0');
end if;
end if;
end if;
end process;
FIFO_req_read_proc : process(clk, rst)
variable FIFO_req_RW_temp : STD_LOGIC;
variable FIFO_req_address_temp : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
variable FIFO_req_din_temp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable FIFO_req_size_temp : STD_LOGIC_VECTOR(31 downto 0);
constant IDLE_STATE : STD_LOGIC_VECTOR(1 downto 0) := "00";
constant READ_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "01";
constant WRITE_BURST_STATE : STD_LOGIC_VECTOR(1 downto 0) := "10";
begin
if(rst = '1') then
FIFO_req_temp_state <= IDLE_STATE;
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
elsif (clk'event and clk = '1') then
case FIFO_req_temp_state is
when IDLE_STATE =>
if(FIFO_req_empty = '0' and FIFO_rsp_full = '0') then
FIFO_req_read <= '1';
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_RW_temp:= FIFO_req_RW(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_address_temp := FIFO_req_address(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_din_temp := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
FIFO_req_size_temp := FIFO_req_size(CONV_INTEGER(FIFO_req_ptr_r));
-- Read request
if(FIFO_req_RW_temp = '0') then
FIFO_rsp_write <= '1'; -- Indicate the output is valid
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(FIFO_rsp_ptr_w /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w,"1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) /= 0 and CONV_INTEGER(FIFO_req_size_temp) /= 1) then -- Read burst request
FIFO_req_temp_state <= READ_BURST_STATE; -- To deal with the rest data
end if;
else
FIFO_rsp_write <= '0'; -- Indicate the output is not valid
if(CONV_INTEGER(FIFO_req_size_temp) = 0 or CONV_INTEGER(FIFO_req_size_temp) = 1) then -- Write single request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp;
else -- Write burst request
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din_temp; -- Input the first data
FIFO_req_temp_state <= WRITE_BURST_STATE; -- To deal with the rest data
end if;
end if;
else -- There is no request in the FIFO_req
FIFO_req_read <= '0';
FIFO_rsp_write <= '0';
end if;
when READ_BURST_STATE =>
FIFO_req_read <= '0'; -- Stop reading the next request
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst read out of size!";
end if;
FIFO_rsp_mem(CONV_INTEGER(FIFO_rsp_ptr_w)) := mem(CONV_INTEGER(FIFO_req_address_temp));
if(CONV_INTEGER(FIFO_rsp_ptr_w) /= DEPTH - 1) then
FIFO_rsp_ptr_w <= esl_add(FIFO_rsp_ptr_w, "1");
else
FIFO_rsp_ptr_w <= (others => '0');
end if;
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
when WRITE_BURST_STATE =>
if(FIFO_req_empty = '0') then
FIFO_req_read <= '1'; -- Keep reading the next data(The data is storaged in FIFO_req but it is not a request)
if(CONV_INTEGER(FIFO_req_ptr_r) /= FIFO_DEPTH - 1) then
FIFO_req_ptr_r <= esl_add(FIFO_req_ptr_r, "1");
else
FIFO_req_ptr_r <= (others => '0');
end if;
FIFO_req_size_temp := esl_sub(FIFO_req_size_temp, "1");
if(CONV_INTEGER(FIFO_req_address_temp) /= DEPTH - 1) then
FIFO_req_address_temp := esl_add(FIFO_req_address_temp, "1");
else
report "Burst write out of size!";
end if;
mem(CONV_INTEGER(FIFO_req_address_temp)) := FIFO_req_din(CONV_INTEGER(FIFO_req_ptr_r));
if(CONV_INTEGER(FIFO_req_size_temp) = 1) then -- The last one is done
FIFO_req_temp_state <= IDLE_STATE;
end if;
end if;
when OTHERS =>
FIFO_req_temp_state <= IDLE_STATE;
end case;
end if;
end process;
-- Generate "FIFO_req_flag"
FIFO_req_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_req_flag <= '0';
else
if((bus_req_RW_en = '1' and FIFO_req_full /= '1') and CONV_INTEGER(FIFO_req_ptr_w) = FIFO_DEPTH - 1) then
FIFO_req_flag <= '1';
end if;
wait for 0.4 ns;
if((FIFO_req_read = '1' and FIFO_req_empty /= '1') and CONV_INTEGER(FIFO_req_ptr_r) = 0) then
FIFO_req_flag <= '0';
end if;
end if;
end process;
-- Generate "FIFO_rsp_flag"
FIFO_rsp_flag_proc : process
begin
wait until clk'event and clk = '1';
if(rst = '1') then
FIFO_rsp_flag <= '0';
else
if((bus_rsp_read = '1' and FIFO_rsp_empty /= '1') and CONV_INTEGER(FIFO_rsp_ptr_r) = DEPTH - 1) then
FIFO_rsp_flag <= '0';
end if;
wait for 0.4 ns;
if((FIFO_rsp_write = '1' and FIFO_rsp_full /= '1') and CONV_INTEGER(FIFO_rsp_ptr_w) = 0) then
FIFO_rsp_flag <= '1';
end if;
end if;
end process;
-- Pop data from FIFO_rsp
FIFO_rsp_ptr_r_proc : process(clk, rst)
begin
if(rst = '1') then
FIFO_rsp_ptr_r <= (others => '0');
elsif (clk'event and clk = '1') then
if(bus_rsp_read = '1' and FIFO_rsp_empty /= '1') then
if(CONV_INTEGER(FIFO_rsp_ptr_r) /= DEPTH - 1) then
FIFO_rsp_ptr_r <= esl_add(FIFO_rsp_ptr_r, "1");
else
FIFO_rsp_ptr_r <= (others => '0');
end if;
end if;
end if;
end process;
----------------------------Read file-------------------
-- Read data from file
read_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable token_len : INTEGER;
variable token_int : INTEGER;
variable idx : INTEGER;
--variable mem_var : arr2D;
begin
file_open(fstatus, fp, TV_IN, READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
report "The token is " & token;
assert false report "Illegal format of [[[runtime]]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
-- Start to read data for every transaction round
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(ready /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
for i in 0 to DEPTH - 1 loop
esl_read_token(fp, token_line, token);
mem(i) := esl_str2lv_hex(token, DATA_WIDTH);
end loop;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
report "The token is " & token;
assert false report "Illegal format of [[/transaction]] part in " & TV_IN severity failure;
end if;
esl_read_token(fp, token_line, token);
end loop;
file_close(fp);
wait;
end process;
----------------------------Write file-------------------
-- Write data to file
write_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128 );
variable transaction_idx : INTEGER;
begin
wait until (rst = '0');
transaction_idx := 0;
while(true) loop
wait until clk'event and clk = '1';
while(done /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to DEPTH - 1 loop
write(token_line, "0x" & esl_conv_string_hex(mem(i)));
writeline(fp, token_line);
end loop;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
wait;
end process;
end behav;
|
-- Ian Roth
-- ECE 8455
-- Mandelbrot Calculation, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
LIBRARY work;
USE work.fixed_pkg.all;
ENTITY Mandelbrot IS
PORT(
x_const, y_const :IN sfixed(3 downto -32);
x_in, y_in :IN sfixed(3 downto -32);
iteration_in :IN unsigned(15 downto 0);
done_in, clk, rst :IN STD_LOGIC;
x_const_out, y_const_out :OUT sfixed(3 downto -32);
x_out, y_out :OUT sfixed(3 downto -32);
iteration_out :OUT unsigned(15 downto 0);
done_out :OUT STD_LOGIC
);
END ENTITY Mandelbrot;
ARCHITECTURE Behavior of Mandelbrot IS
CONSTANT limit :sfixed(3 downto 0) := X"2";
SIGNAL x_sqr, y_sqr :sfixed(3 downto -32);
BEGIN
x_sqr <= resize(x_in * x_in, x_sqr);
y_sqr <= resize(y_in * y_in, y_sqr);
Process(clk,rst)
BEGIN
IF (clk'EVENT and clk = '1') THEN
IF (rst = '1') THEN
iteration_out <= X"0000";
done_out <= '0';
ELSE
x_out <= resize(x_sqr - y_sqr + x_const, x_sqr);
y_out <= resize(((x_in * y_in) sll 1) + y_const, y_sqr);
x_const_out <= x_const;
y_const_out <= y_const;
IF (done_in = '1') THEN
done_out <= '1';
iteration_out <= iteration_in;
ELSE
IF (resize(x_sqr + y_sqr, x_sqr) > limit) THEN
done_out <= '1';
iteration_out <= iteration_in;
ELSE
done_out <= '0';
iteration_out <= iteration_in + 1;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END Behavior; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (2);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 0;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (16);
constant CFG_DDRSP_RSKEW : integer := (0);
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 1;
constant CFG_PCIVID : integer := 16#1AC8#;
constant CFG_PCIDID : integer := 16#0054#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
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j5omPVx9aw==
`protect end_protected
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eca_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eca_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:04 wig Exp $
-- $Date: 2004/04/06 10:50:04 $
-- $Log: inst_eca_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:04 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eca_e
--
architecture rtl of inst_eca_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc543.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p02n01i00543ent IS
END c03s04b00x00p02n01i00543ent;
ARCHITECTURE c03s04b00x00p02n01i00543arch OF c03s04b00x00p02n01i00543ent IS
type ARR is
record
V1 : Integer;
V2 : Integer;
end record;
type A1 is file ARR; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p02n01i00543 - Missing reserved word 'OF'."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p02n01i00543arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc543.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p02n01i00543ent IS
END c03s04b00x00p02n01i00543ent;
ARCHITECTURE c03s04b00x00p02n01i00543arch OF c03s04b00x00p02n01i00543ent IS
type ARR is
record
V1 : Integer;
V2 : Integer;
end record;
type A1 is file ARR; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p02n01i00543 - Missing reserved word 'OF'."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p02n01i00543arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc543.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p02n01i00543ent IS
END c03s04b00x00p02n01i00543ent;
ARCHITECTURE c03s04b00x00p02n01i00543arch OF c03s04b00x00p02n01i00543ent IS
type ARR is
record
V1 : Integer;
V2 : Integer;
end record;
type A1 is file ARR; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s04b00x00p02n01i00543 - Missing reserved word 'OF'."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b00x00p02n01i00543arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity:
-- File: sysmon_unisim.vhd
-- Author: Jan Andersson - Gaisler Research
-- Description: Xilinx System Monitor
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.SYSMON;
-- pragma translate_on
-------------------------------------------------------------------------------
-- Virtex 5 System Monitor
-------------------------------------------------------------------------------
entity sysmon_virtex5 is
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end sysmon_virtex5;
architecture struct of sysmon_virtex5 is
component SYSMON
generic (
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt"
);
port (
ALM : out std_logic_vector(2 downto 0);
BUSY : out std_ulogic;
CHANNEL : out std_logic_vector(4 downto 0);
DO : out std_logic_vector(15 downto 0);
DRDY : out std_ulogic;
EOC : out std_ulogic;
EOS : out std_ulogic;
JTAGBUSY : out std_ulogic;
JTAGLOCKED : out std_ulogic;
JTAGMODIFIED : out std_ulogic;
OT : out std_ulogic;
CONVST : in std_ulogic;
CONVSTCLK : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
RESET : in std_ulogic;
VAUXN : in std_logic_vector(15 downto 0);
VAUXP : in std_logic_vector(15 downto 0);
VN : in std_ulogic;
VP : in std_ulogic
);
end component;
begin -- struct
sysmon0 : SYSMON
generic map (INIT_40 => INIT_40, INIT_41 => INIT_41, INIT_42 => INIT_42,
INIT_43 => INIT_43, INIT_44 => INIT_44, INIT_45 => INIT_45,
INIT_46 => INIT_46, INIT_47 => INIT_47, INIT_48 => INIT_48,
INIT_49 => INIT_49, INIT_4A => INIT_4A, INIT_4B => INIT_4B,
INIT_4C => INIT_4C, INIT_4D => INIT_4D, INIT_4E => INIT_4E,
INIT_4F => INIT_4F, INIT_50 => INIT_50, INIT_51 => INIT_51,
INIT_52 => INIT_52, INIT_53 => INIT_53, INIT_54 => INIT_54,
INIT_55 => INIT_55, INIT_56 => INIT_56, INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => alm, busy => busy, channel => channel, do => do,
drdy => drdy, eoc => eoc, eos => eos, jtagbusy => jtagbusy,
jtaglocked => jtaglocked, jtagmodified => jtagmodified,
ot => ot, convst => convst, convstclk => convstclk,
daddr => daddr, dclk => dclk, den => den, di => di,
dwe => dwe, reset => reset, vauxn => vauxn, vauxp => vauxp,
vn => vn, vp => vp);
end struct;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1832.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01832ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01832ent;
ARCHITECTURE c07s01b00x00p08n01i01832arch OF c07s01b00x00p08n01i01832ent IS
function test return small_int is
begin
return c07s01b00x00p08n01i01832nt; -- entity name illegal here
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01832 - Entity name are not permitted as primaries in a function return statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01832arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1832.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01832ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01832ent;
ARCHITECTURE c07s01b00x00p08n01i01832arch OF c07s01b00x00p08n01i01832ent IS
function test return small_int is
begin
return c07s01b00x00p08n01i01832nt; -- entity name illegal here
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01832 - Entity name are not permitted as primaries in a function return statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01832arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1832.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01832ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01832ent;
ARCHITECTURE c07s01b00x00p08n01i01832arch OF c07s01b00x00p08n01i01832ent IS
function test return small_int is
begin
return c07s01b00x00p08n01i01832nt; -- entity name illegal here
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01832 - Entity name are not permitted as primaries in a function return statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01832arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memmux03 is
port (
wen : std_logic;
addr : std_logic_vector (3 downto 0);
rdat : out std_logic;
wdat : std_logic_vector (12 downto 0);
clk : std_logic;
rst : std_logic);
end memmux03;
architecture rtl of memmux03 is
begin
process (clk)
is
variable mem : std_logic_vector (12 downto 0);
variable ad : natural range 0 to 12;
begin
if rising_edge(clk) then
if rst = '1' then
mem := (others => '0');
else
ad := to_integer(unsigned(addr));
rdat <= mem (ad);
if wen = '1' then
mem := wdat;
end if;
end if;
end if;
end process;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity RS232Read is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
S : out std_logic_vector(13 downto 0)
);
end RS232Read;
architecture moore of RS232Read is
signal FBaud : std_logic;
signal ENC : std_logic;
signal LDx : std_logic;
signal EOR : std_logic;
signal Q : std_logic_vector(7 downto 0);
signal NBaud : std_logic_vector(3 downto 0);
component BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end component;
component FSMRead is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
FBaud : in std_logic;
ENC : out std_logic;
EOR : out std_logic;
LDx : out std_logic
);
end component;
component RegSerPar is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
LDx : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component;
component hex_7seg is
port(
RST : in std_logic;
CLK : in std_logic;
EOR : in std_logic;
Q : in std_logic_vector(3 downto 0);
S : out std_logic_vector(6 downto 0)
);
end component;
begin
U00 : FSMRead port map(RST,CLK,Rx,FBaud,ENC,EOR,LDx);
U01 : RegSerPar port map(RST,CLK,Rx,LDx,Q);
U02 : BaudRateRD port map(RST,CLK,ENC,NBaud,FBaud);
U03 : hex_7seg port map(RST,CLK,EOR,Q(3 downto 0),S(6 downto 0));
U04 : hex_7seg port map(RST,CLK,EOR,Q(7 downto 4),S(13 downto 7));
end moore;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity RS232Read is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
S : out std_logic_vector(13 downto 0)
);
end RS232Read;
architecture moore of RS232Read is
signal FBaud : std_logic;
signal ENC : std_logic;
signal LDx : std_logic;
signal EOR : std_logic;
signal Q : std_logic_vector(7 downto 0);
signal NBaud : std_logic_vector(3 downto 0);
component BaudRateRD is
port(
RST : in std_logic;
CLK : in std_logic;
ENC : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end component;
component FSMRead is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
FBaud : in std_logic;
ENC : out std_logic;
EOR : out std_logic;
LDx : out std_logic
);
end component;
component RegSerPar is
port(
RST : in std_logic;
CLK : in std_logic;
Rx : in std_logic;
LDx : in std_logic;
Q : out std_logic_vector(7 downto 0)
);
end component;
component hex_7seg is
port(
RST : in std_logic;
CLK : in std_logic;
EOR : in std_logic;
Q : in std_logic_vector(3 downto 0);
S : out std_logic_vector(6 downto 0)
);
end component;
begin
U00 : FSMRead port map(RST,CLK,Rx,FBaud,ENC,EOR,LDx);
U01 : RegSerPar port map(RST,CLK,Rx,LDx,Q);
U02 : BaudRateRD port map(RST,CLK,ENC,NBaud,FBaud);
U03 : hex_7seg port map(RST,CLK,EOR,Q(3 downto 0),S(6 downto 0));
U04 : hex_7seg port map(RST,CLK,EOR,Q(7 downto 4),S(13 downto 7));
end moore;
|
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|
`protect begin_protected
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LIHAu1ROghCG8vr9QqFlH2Ed5cgANxU//9BVzrfgTldhBu6E4j0M2IRr84vMHUAxYdoVmpc6PBLX
KBjhI48PixDEg/2RHsA7Vf5awMAgi1dUMla21YTkU2XRhDASFx7ZxAs5ycn0sqUPvExPMVuhDj/S
+DQPv/xOCXsjUNwre+/1m3A8EKA=
`protect end_protected
|
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use unisim.vcomponents.all; -- xilinx component declarations
entity clockgen is
port (
ext_clk, async_resetb : in std_ulogic;
clk, sync_reset : out std_ulogic
);
end clockgen;
architecture virtex5 of clockgen is
------------------------------------------------------------
-- local signals
------------------------------------------------------------
signal clk_i : std_ulogic;
signal locked : std_ulogic;
signal clock_from_ibufg : std_ulogic;
signal reset, reset_sync : std_ulogic;
signal clkfb : std_ulogic;
signal clk_to_bufg : std_ulogic;
signal reset_cond : std_ulogic;
begin
clk <= clk_i;
------------------------------------------------------------
-- clock generation
------------------------------------------------------------
clock_pin_ibufg: ibufg
port map(
I => ext_clk,
O => clock_from_ibufg
);
------------------------------------------------------------
-- reset synchronizer
------------------------------------------------------------
reset_synchronizer: process ( clock_from_ibufg, async_resetb )
begin
if async_resetb = '0' then
reset <= '1';
reset_sync <= '1';
elsif rising_edge(clk_i) then
reset <= reset_sync;
reset_sync <= '0';
end if;
end process;
------------------------------------------------------------
------------------------------------------------------------
-- PLL
------------------------------------------------------------
pll_inst: pll_base
generic map (
clkfbout_mult => 6,
clkout0_divide => 6,
clkin_period => 10.0
)
port map (
clkin => clock_from_ibufg,
rst => reset,
clkfbout => clkfb,
clkfbin => clkfb,
clkout0 => clk_to_bufg,
clkout1 => open,
clkout2 => open,
clkout3 => open,
clkout4 => open,
clkout5 => open,
locked => locked
);
gen_clk_bufg: bufg
port map (
I => clk_to_bufg,
O => clk_i
);
------------------------------------------------------------
-- synchronous reset output
------------------------------------------------------------
reset_cond <= not locked or reset;
------------------------------------------------------------
sync_rst_out: process ( clk_i, reset_cond )
begin
if reset_cond = '1' then
sync_reset <= '1';
elsif rising_edge(clk_i) then
sync_reset <= '0';
end if;
end process;
------------------------------------------------------------
end virtex5;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: EXTERNAL_MEMORY_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EXTERNAL_MEMORY_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END EXTERNAL_MEMORY_exdes;
ARCHITECTURE xilinx OF EXTERNAL_MEMORY_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT EXTERNAL_MEMORY IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : EXTERNAL_MEMORY
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: EXTERNAL_MEMORY_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY EXTERNAL_MEMORY_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END EXTERNAL_MEMORY_exdes;
ARCHITECTURE xilinx OF EXTERNAL_MEMORY_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT EXTERNAL_MEMORY IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : EXTERNAL_MEMORY
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNLUTPOW.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnlutpow IS
PORT (
add : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_lnlutpow;
ARCHITECTURE rtl OF fp_lnlutpow IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000" =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
WHEN "0000001" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(126,8);
WHEN "0000010" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(127,8);
WHEN "0000011" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000100" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000101" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(128,8);
WHEN "0000110" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0000111" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001001" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001010" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001011" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(129,8);
WHEN "0001100" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001101" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001110" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0001111" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010001" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010010" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010011" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010100" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010101" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010110" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0010111" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(130,8);
WHEN "0011000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011001" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011010" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011011" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011100" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011101" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011110" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0011111" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100001" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100010" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100011" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100100" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100101" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100110" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0100111" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101001" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101010" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101011" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101100" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101101" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101110" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(131,8);
WHEN "0101111" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110001" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110010" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110011" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110100" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110101" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110110" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0110111" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111001" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111010" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111011" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111100" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111101" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111110" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "0111111" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000000" =>
logman <= conv_std_logic_vector(3240472,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000001" =>
logman <= conv_std_logic_vector(3422176,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000010" =>
logman <= conv_std_logic_vector(3603881,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000011" =>
logman <= conv_std_logic_vector(3785585,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000100" =>
logman <= conv_std_logic_vector(3967289,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000101" =>
logman <= conv_std_logic_vector(4148994,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000110" =>
logman <= conv_std_logic_vector(4330698,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1000111" =>
logman <= conv_std_logic_vector(4512403,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001000" =>
logman <= conv_std_logic_vector(4694107,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001001" =>
logman <= conv_std_logic_vector(4875811,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001010" =>
logman <= conv_std_logic_vector(5057516,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001011" =>
logman <= conv_std_logic_vector(5239220,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001100" =>
logman <= conv_std_logic_vector(5420924,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001101" =>
logman <= conv_std_logic_vector(5602629,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001110" =>
logman <= conv_std_logic_vector(5784333,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1001111" =>
logman <= conv_std_logic_vector(5966038,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010000" =>
logman <= conv_std_logic_vector(6147742,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010001" =>
logman <= conv_std_logic_vector(6329446,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010010" =>
logman <= conv_std_logic_vector(6511151,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010011" =>
logman <= conv_std_logic_vector(6692855,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010100" =>
logman <= conv_std_logic_vector(6874559,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010101" =>
logman <= conv_std_logic_vector(7056264,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010110" =>
logman <= conv_std_logic_vector(7237968,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1010111" =>
logman <= conv_std_logic_vector(7419673,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011000" =>
logman <= conv_std_logic_vector(7601377,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011001" =>
logman <= conv_std_logic_vector(7783081,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011010" =>
logman <= conv_std_logic_vector(7964786,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011011" =>
logman <= conv_std_logic_vector(8146490,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011100" =>
logman <= conv_std_logic_vector(8328194,23);
logexp <= conv_std_logic_vector(132,8);
WHEN "1011101" =>
logman <= conv_std_logic_vector(60645,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011110" =>
logman <= conv_std_logic_vector(151498,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1011111" =>
logman <= conv_std_logic_vector(242350,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100000" =>
logman <= conv_std_logic_vector(333202,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100001" =>
logman <= conv_std_logic_vector(424054,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100010" =>
logman <= conv_std_logic_vector(514906,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100011" =>
logman <= conv_std_logic_vector(605759,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100100" =>
logman <= conv_std_logic_vector(696611,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100101" =>
logman <= conv_std_logic_vector(787463,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100110" =>
logman <= conv_std_logic_vector(878315,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1100111" =>
logman <= conv_std_logic_vector(969167,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101000" =>
logman <= conv_std_logic_vector(1060019,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101001" =>
logman <= conv_std_logic_vector(1150872,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101010" =>
logman <= conv_std_logic_vector(1241724,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101011" =>
logman <= conv_std_logic_vector(1332576,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101100" =>
logman <= conv_std_logic_vector(1423428,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101101" =>
logman <= conv_std_logic_vector(1514280,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101110" =>
logman <= conv_std_logic_vector(1605133,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1101111" =>
logman <= conv_std_logic_vector(1695985,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110000" =>
logman <= conv_std_logic_vector(1786837,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110001" =>
logman <= conv_std_logic_vector(1877689,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110010" =>
logman <= conv_std_logic_vector(1968541,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110011" =>
logman <= conv_std_logic_vector(2059394,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110100" =>
logman <= conv_std_logic_vector(2150246,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110101" =>
logman <= conv_std_logic_vector(2241098,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110110" =>
logman <= conv_std_logic_vector(2331950,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1110111" =>
logman <= conv_std_logic_vector(2422802,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111000" =>
logman <= conv_std_logic_vector(2513654,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111001" =>
logman <= conv_std_logic_vector(2604507,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111010" =>
logman <= conv_std_logic_vector(2695359,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111011" =>
logman <= conv_std_logic_vector(2786211,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111100" =>
logman <= conv_std_logic_vector(2877063,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111101" =>
logman <= conv_std_logic_vector(2967915,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111110" =>
logman <= conv_std_logic_vector(3058768,23);
logexp <= conv_std_logic_vector(133,8);
WHEN "1111111" =>
logman <= conv_std_logic_vector(3149620,23);
logexp <= conv_std_logic_vector(133,8);
WHEN others =>
logman <= conv_std_logic_vector(0,23);
logexp <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weight_out_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weight_out_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END weight_out_exdes;
ARCHITECTURE xilinx OF weight_out_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT weight_out IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : weight_out
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity k_ukf_Vsigrefofkofall is
port (
clock : in std_logic;
Vrefofkplusone : in std_logic_vector(31 downto 0);
refsigma : in std_logic_vector(31 downto 0);
Vsigrefofkofzero : out std_logic_vector(31 downto 0);
Vsigrefofkofone : out std_logic_vector(31 downto 0);
Vsigrefofkoftwo : out std_logic_vector(31 downto 0)
);
end k_ukf_Vsigrefofkofall;
architecture struct of k_ukf_Vsigrefofkofall is
component k_ukf_add IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component k_ukf_sub IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
begin
Vsigrefofkofzero <= Vrefofkplusone;
M1 : k_ukf_add port map
( clock => clock,
dataa => Vrefofkplusone,
datab => refsigma,
result => Vsigrefofkofone);
M2 : k_ukf_sub port map
( clock => clock,
dataa => Vrefofkplusone,
datab => refsigma,
result => Vsigrefofkoftwo);
end struct; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc296.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n04i00296ent IS
END c03s01b03x01p01n04i00296ent;
ARCHITECTURE c03s01b03x01p01n04i00296arch OF c03s01b03x01p01n04i00296ent IS
type some_time is range 1 to 100
units
fs; -- base unit
x = 10 fs;
y = 10 x;
end units;
constant z : some_time := 10 y;
signal S : integer;
BEGIN
TESTING: PROCESS
BEGIN
S <= 10 after z;
wait for 20 ns;
assert FALSE
report "***FAILED TEST: c03s01b03x01p01n04i00296 - The delay specification is not of type TIME."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n04i00296arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc296.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n04i00296ent IS
END c03s01b03x01p01n04i00296ent;
ARCHITECTURE c03s01b03x01p01n04i00296arch OF c03s01b03x01p01n04i00296ent IS
type some_time is range 1 to 100
units
fs; -- base unit
x = 10 fs;
y = 10 x;
end units;
constant z : some_time := 10 y;
signal S : integer;
BEGIN
TESTING: PROCESS
BEGIN
S <= 10 after z;
wait for 20 ns;
assert FALSE
report "***FAILED TEST: c03s01b03x01p01n04i00296 - The delay specification is not of type TIME."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n04i00296arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc296.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n04i00296ent IS
END c03s01b03x01p01n04i00296ent;
ARCHITECTURE c03s01b03x01p01n04i00296arch OF c03s01b03x01p01n04i00296ent IS
type some_time is range 1 to 100
units
fs; -- base unit
x = 10 fs;
y = 10 x;
end units;
constant z : some_time := 10 y;
signal S : integer;
BEGIN
TESTING: PROCESS
BEGIN
S <= 10 after z;
wait for 20 ns;
assert FALSE
report "***FAILED TEST: c03s01b03x01p01n04i00296 - The delay specification is not of type TIME."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n04i00296arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1492.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p05n01i01492ent IS
END c08s08b00x00p05n01i01492ent;
ARCHITECTURE c08s08b00x00p05n01i01492arch OF c08s08b00x00p05n01i01492ent IS
BEGIN
TESTING: PROCESS
variable b1, b2 : boolean ;= true;
BEGIN
case b1 is
end case; -- illegal
assert FALSE
report "***FAILED TEST: c08s08b00x00p05n01i01492 - Case statement must have at least one alternative."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p05n01i01492arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1492.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p05n01i01492ent IS
END c08s08b00x00p05n01i01492ent;
ARCHITECTURE c08s08b00x00p05n01i01492arch OF c08s08b00x00p05n01i01492ent IS
BEGIN
TESTING: PROCESS
variable b1, b2 : boolean ;= true;
BEGIN
case b1 is
end case; -- illegal
assert FALSE
report "***FAILED TEST: c08s08b00x00p05n01i01492 - Case statement must have at least one alternative."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p05n01i01492arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1492.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p05n01i01492ent IS
END c08s08b00x00p05n01i01492ent;
ARCHITECTURE c08s08b00x00p05n01i01492arch OF c08s08b00x00p05n01i01492ent IS
BEGIN
TESTING: PROCESS
variable b1, b2 : boolean ;= true;
BEGIN
case b1 is
end case; -- illegal
assert FALSE
report "***FAILED TEST: c08s08b00x00p05n01i01492 - Case statement must have at least one alternative."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p05n01i01492arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY mig_wrap_proc_sys_reset_0_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END mig_wrap_proc_sys_reset_0_0;
ARCHITECTURE mig_wrap_proc_sys_reset_0_0_arch OF mig_wrap_proc_sys_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mig_wrap_proc_sys_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "virtex7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '1',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END mig_wrap_proc_sys_reset_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- Library UNISIM;
-- use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity memory is
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end; --entity memory
architecture rtl of memory is
signal data_out : std_logic_vector(31 downto 0);
signal index : integer := 0;
begin
index <= conv_integer(address(16 - 1 downto 2));
BRAM_SINGLE_MACRO_inst : BRAM_SINGLE_MACRO
generic map(
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "VIRTEX6, "SPARTAN6"
DO_REG => 0, -- Optional output register (0 or 1)
INIT => X"000000000000000000", -- Initial values on output port
INIT_FILE => "NONE",
WRITE_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
READ_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
SRVAL => X"000000000000000000", -- Set/Reset value for port output
WRITE_MODE => "READ_FIRST" -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
)
port map(
DO => data_out, -- Output data, width defined by READ_WIDTH parameter
ADDR => STD_logic_vector(to_unsigned(index, 10)), -- Input address, width defined by read/write port depth
CLK => CLK, -- 1-bit input clock
DI => data_write, -- Input data port, width defined by WRITE_WIDTH parameter
EN => '1', -- 1-bit input RAM enable
REGCE => '0', -- 1-bit input output register enable
RST => '0', -- 1-bit input reset
WE => byte_we -- Input write enable, width defined by write port depth
);
dram_proc : process(clk, address, byte_we, pause)
begin
if rising_edge(clk) then
if pause = '0' then
data_read <= data_out;
end if;
end if;
end process;
end; --architecture logic
|
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- Library UNISIM;
-- use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity memory is
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end; --entity memory
architecture rtl of memory is
signal data_out : std_logic_vector(31 downto 0);
signal index : integer := 0;
begin
index <= conv_integer(address(16 - 1 downto 2));
BRAM_SINGLE_MACRO_inst : BRAM_SINGLE_MACRO
generic map(
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "VIRTEX6, "SPARTAN6"
DO_REG => 0, -- Optional output register (0 or 1)
INIT => X"000000000000000000", -- Initial values on output port
INIT_FILE => "NONE",
WRITE_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
READ_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
SRVAL => X"000000000000000000", -- Set/Reset value for port output
WRITE_MODE => "READ_FIRST" -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
)
port map(
DO => data_out, -- Output data, width defined by READ_WIDTH parameter
ADDR => STD_logic_vector(to_unsigned(index, 10)), -- Input address, width defined by read/write port depth
CLK => CLK, -- 1-bit input clock
DI => data_write, -- Input data port, width defined by WRITE_WIDTH parameter
EN => '1', -- 1-bit input RAM enable
REGCE => '0', -- 1-bit input output register enable
RST => '0', -- 1-bit input reset
WE => byte_we -- Input write enable, width defined by write port depth
);
dram_proc : process(clk, address, byte_we, pause)
begin
if rising_edge(clk) then
if pause = '0' then
data_read <= data_out;
end if;
end if;
end process;
end; --architecture logic
|
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- Library UNISIM;
-- use UNISIM.vcomponents.all;
Library UNIMACRO;
use UNIMACRO.vcomponents.all;
entity memory is
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end; --entity memory
architecture rtl of memory is
signal data_out : std_logic_vector(31 downto 0);
signal index : integer := 0;
begin
index <= conv_integer(address(16 - 1 downto 2));
BRAM_SINGLE_MACRO_inst : BRAM_SINGLE_MACRO
generic map(
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "VIRTEX6, "SPARTAN6"
DO_REG => 0, -- Optional output register (0 or 1)
INIT => X"000000000000000000", -- Initial values on output port
INIT_FILE => "NONE",
WRITE_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
READ_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
SRVAL => X"000000000000000000", -- Set/Reset value for port output
WRITE_MODE => "READ_FIRST" -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
)
port map(
DO => data_out, -- Output data, width defined by READ_WIDTH parameter
ADDR => STD_logic_vector(to_unsigned(index, 10)), -- Input address, width defined by read/write port depth
CLK => CLK, -- 1-bit input clock
DI => data_write, -- Input data port, width defined by WRITE_WIDTH parameter
EN => '1', -- 1-bit input RAM enable
REGCE => '0', -- 1-bit input output register enable
RST => '0', -- 1-bit input reset
WE => byte_we -- Input write enable, width defined by write port depth
);
dram_proc : process(clk, address, byte_we, pause)
begin
if rising_edge(clk) then
if pause = '0' then
data_read <= data_out;
end if;
end if;
end process;
end; --architecture logic
|
library verilog;
use verilog.vl_types.all;
entity nfa_accept_samples_generic_hw_top is
generic(
C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_nfa_initials_buckets_AWIDTH: integer := 32;
C_nfa_initials_buckets_DWIDTH: integer := 64;
C_nfa_initials_buckets_NATIVE_DWIDTH: integer := 64;
C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_nfa_finals_buckets_AWIDTH: integer := 32;
C_nfa_finals_buckets_DWIDTH: integer := 64;
C_nfa_finals_buckets_NATIVE_DWIDTH: integer := 64;
C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_nfa_forward_buckets_AWIDTH: integer := 32;
C_nfa_forward_buckets_DWIDTH: integer := 64;
C_nfa_forward_buckets_NATIVE_DWIDTH: integer := 64;
C_sample_buffer_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_sample_buffer_AWIDTH: integer := 32;
C_sample_buffer_DWIDTH: integer := 64;
C_sample_buffer_NATIVE_DWIDTH: integer := 64;
C_indices_REMOTE_DESTINATION_ADDRESS: integer := 0;
C_indices_AWIDTH: integer := 32;
C_indices_DWIDTH: integer := 64;
C_indices_NATIVE_DWIDTH: integer := 64;
C_SPLB_SLV0_BASEADDR: integer := 0;
C_SPLB_SLV0_HIGHADDR: integer := 15;
C_SPLB_SLV0_AWIDTH: integer := 32;
C_SPLB_SLV0_DWIDTH: integer := 32;
C_SPLB_SLV0_NUM_MASTERS: integer := 8;
C_SPLB_SLV0_MID_WIDTH: integer := 3;
C_SPLB_SLV0_NATIVE_DWIDTH: integer := 32;
C_SPLB_SLV0_P2P : integer := 0;
C_SPLB_SLV0_SUPPORT_BURSTS: integer := 0;
C_SPLB_SLV0_SMALLEST_MASTER: integer := 32;
C_SPLB_SLV0_INCLUDE_DPHASE_TIMER: integer := 0;
RESET_ACTIVE_LOW: integer := 1
);
port(
nfa_initials_buckets_MPLB_Clk: in vl_logic;
nfa_initials_buckets_MPLB_Rst: in vl_logic;
nfa_initials_buckets_M_request: out vl_logic;
nfa_initials_buckets_M_priority: out vl_logic_vector(1 downto 0);
nfa_initials_buckets_M_busLock: out vl_logic;
nfa_initials_buckets_M_RNW: out vl_logic;
nfa_initials_buckets_M_BE: out vl_logic_vector;
nfa_initials_buckets_M_MSize: out vl_logic_vector(1 downto 0);
nfa_initials_buckets_M_size: out vl_logic_vector(3 downto 0);
nfa_initials_buckets_M_type: out vl_logic_vector(2 downto 0);
nfa_initials_buckets_M_TAttribute: out vl_logic_vector(15 downto 0);
nfa_initials_buckets_M_lockErr: out vl_logic;
nfa_initials_buckets_M_abort: out vl_logic;
nfa_initials_buckets_M_UABus: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_M_ABus: out vl_logic_vector(31 downto 0);
nfa_initials_buckets_M_wrDBus: out vl_logic_vector;
nfa_initials_buckets_M_wrBurst: out vl_logic;
nfa_initials_buckets_M_rdBurst: out vl_logic;
nfa_initials_buckets_PLB_MAddrAck: in vl_logic;
nfa_initials_buckets_PLB_MSSize: in vl_logic_vector(1 downto 0);
nfa_initials_buckets_PLB_MRearbitrate: in vl_logic;
nfa_initials_buckets_PLB_MTimeout: in vl_logic;
nfa_initials_buckets_PLB_MBusy: in vl_logic;
nfa_initials_buckets_PLB_MRdErr: in vl_logic;
nfa_initials_buckets_PLB_MWrErr: in vl_logic;
nfa_initials_buckets_PLB_MIRQ: in vl_logic;
nfa_initials_buckets_PLB_MRdDBus: in vl_logic_vector;
nfa_initials_buckets_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
nfa_initials_buckets_PLB_MRdDAck: in vl_logic;
nfa_initials_buckets_PLB_MRdBTerm: in vl_logic;
nfa_initials_buckets_PLB_MWrDAck: in vl_logic;
nfa_initials_buckets_PLB_MWrBTerm: in vl_logic;
nfa_finals_buckets_MPLB_Clk: in vl_logic;
nfa_finals_buckets_MPLB_Rst: in vl_logic;
nfa_finals_buckets_M_request: out vl_logic;
nfa_finals_buckets_M_priority: out vl_logic_vector(1 downto 0);
nfa_finals_buckets_M_busLock: out vl_logic;
nfa_finals_buckets_M_RNW: out vl_logic;
nfa_finals_buckets_M_BE: out vl_logic_vector;
nfa_finals_buckets_M_MSize: out vl_logic_vector(1 downto 0);
nfa_finals_buckets_M_size: out vl_logic_vector(3 downto 0);
nfa_finals_buckets_M_type: out vl_logic_vector(2 downto 0);
nfa_finals_buckets_M_TAttribute: out vl_logic_vector(15 downto 0);
nfa_finals_buckets_M_lockErr: out vl_logic;
nfa_finals_buckets_M_abort: out vl_logic;
nfa_finals_buckets_M_UABus: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_M_ABus: out vl_logic_vector(31 downto 0);
nfa_finals_buckets_M_wrDBus: out vl_logic_vector;
nfa_finals_buckets_M_wrBurst: out vl_logic;
nfa_finals_buckets_M_rdBurst: out vl_logic;
nfa_finals_buckets_PLB_MAddrAck: in vl_logic;
nfa_finals_buckets_PLB_MSSize: in vl_logic_vector(1 downto 0);
nfa_finals_buckets_PLB_MRearbitrate: in vl_logic;
nfa_finals_buckets_PLB_MTimeout: in vl_logic;
nfa_finals_buckets_PLB_MBusy: in vl_logic;
nfa_finals_buckets_PLB_MRdErr: in vl_logic;
nfa_finals_buckets_PLB_MWrErr: in vl_logic;
nfa_finals_buckets_PLB_MIRQ: in vl_logic;
nfa_finals_buckets_PLB_MRdDBus: in vl_logic_vector;
nfa_finals_buckets_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
nfa_finals_buckets_PLB_MRdDAck: in vl_logic;
nfa_finals_buckets_PLB_MRdBTerm: in vl_logic;
nfa_finals_buckets_PLB_MWrDAck: in vl_logic;
nfa_finals_buckets_PLB_MWrBTerm: in vl_logic;
nfa_forward_buckets_MPLB_Clk: in vl_logic;
nfa_forward_buckets_MPLB_Rst: in vl_logic;
nfa_forward_buckets_M_request: out vl_logic;
nfa_forward_buckets_M_priority: out vl_logic_vector(1 downto 0);
nfa_forward_buckets_M_busLock: out vl_logic;
nfa_forward_buckets_M_RNW: out vl_logic;
nfa_forward_buckets_M_BE: out vl_logic_vector;
nfa_forward_buckets_M_MSize: out vl_logic_vector(1 downto 0);
nfa_forward_buckets_M_size: out vl_logic_vector(3 downto 0);
nfa_forward_buckets_M_type: out vl_logic_vector(2 downto 0);
nfa_forward_buckets_M_TAttribute: out vl_logic_vector(15 downto 0);
nfa_forward_buckets_M_lockErr: out vl_logic;
nfa_forward_buckets_M_abort: out vl_logic;
nfa_forward_buckets_M_UABus: out vl_logic_vector(31 downto 0);
nfa_forward_buckets_M_ABus: out vl_logic_vector(31 downto 0);
nfa_forward_buckets_M_wrDBus: out vl_logic_vector;
nfa_forward_buckets_M_wrBurst: out vl_logic;
nfa_forward_buckets_M_rdBurst: out vl_logic;
nfa_forward_buckets_PLB_MAddrAck: in vl_logic;
nfa_forward_buckets_PLB_MSSize: in vl_logic_vector(1 downto 0);
nfa_forward_buckets_PLB_MRearbitrate: in vl_logic;
nfa_forward_buckets_PLB_MTimeout: in vl_logic;
nfa_forward_buckets_PLB_MBusy: in vl_logic;
nfa_forward_buckets_PLB_MRdErr: in vl_logic;
nfa_forward_buckets_PLB_MWrErr: in vl_logic;
nfa_forward_buckets_PLB_MIRQ: in vl_logic;
nfa_forward_buckets_PLB_MRdDBus: in vl_logic_vector;
nfa_forward_buckets_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
nfa_forward_buckets_PLB_MRdDAck: in vl_logic;
nfa_forward_buckets_PLB_MRdBTerm: in vl_logic;
nfa_forward_buckets_PLB_MWrDAck: in vl_logic;
nfa_forward_buckets_PLB_MWrBTerm: in vl_logic;
sample_buffer_MPLB_Clk: in vl_logic;
sample_buffer_MPLB_Rst: in vl_logic;
sample_buffer_M_request: out vl_logic;
sample_buffer_M_priority: out vl_logic_vector(1 downto 0);
sample_buffer_M_busLock: out vl_logic;
sample_buffer_M_RNW: out vl_logic;
sample_buffer_M_BE: out vl_logic_vector;
sample_buffer_M_MSize: out vl_logic_vector(1 downto 0);
sample_buffer_M_size: out vl_logic_vector(3 downto 0);
sample_buffer_M_type: out vl_logic_vector(2 downto 0);
sample_buffer_M_TAttribute: out vl_logic_vector(15 downto 0);
sample_buffer_M_lockErr: out vl_logic;
sample_buffer_M_abort: out vl_logic;
sample_buffer_M_UABus: out vl_logic_vector(31 downto 0);
sample_buffer_M_ABus: out vl_logic_vector(31 downto 0);
sample_buffer_M_wrDBus: out vl_logic_vector;
sample_buffer_M_wrBurst: out vl_logic;
sample_buffer_M_rdBurst: out vl_logic;
sample_buffer_PLB_MAddrAck: in vl_logic;
sample_buffer_PLB_MSSize: in vl_logic_vector(1 downto 0);
sample_buffer_PLB_MRearbitrate: in vl_logic;
sample_buffer_PLB_MTimeout: in vl_logic;
sample_buffer_PLB_MBusy: in vl_logic;
sample_buffer_PLB_MRdErr: in vl_logic;
sample_buffer_PLB_MWrErr: in vl_logic;
sample_buffer_PLB_MIRQ: in vl_logic;
sample_buffer_PLB_MRdDBus: in vl_logic_vector;
sample_buffer_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
sample_buffer_PLB_MRdDAck: in vl_logic;
sample_buffer_PLB_MRdBTerm: in vl_logic;
sample_buffer_PLB_MWrDAck: in vl_logic;
sample_buffer_PLB_MWrBTerm: in vl_logic;
indices_MPLB_Clk: in vl_logic;
indices_MPLB_Rst: in vl_logic;
indices_M_request: out vl_logic;
indices_M_priority: out vl_logic_vector(1 downto 0);
indices_M_busLock: out vl_logic;
indices_M_RNW : out vl_logic;
indices_M_BE : out vl_logic_vector;
indices_M_MSize : out vl_logic_vector(1 downto 0);
indices_M_size : out vl_logic_vector(3 downto 0);
indices_M_type : out vl_logic_vector(2 downto 0);
indices_M_TAttribute: out vl_logic_vector(15 downto 0);
indices_M_lockErr: out vl_logic;
indices_M_abort : out vl_logic;
indices_M_UABus : out vl_logic_vector(31 downto 0);
indices_M_ABus : out vl_logic_vector(31 downto 0);
indices_M_wrDBus: out vl_logic_vector;
indices_M_wrBurst: out vl_logic;
indices_M_rdBurst: out vl_logic;
indices_PLB_MAddrAck: in vl_logic;
indices_PLB_MSSize: in vl_logic_vector(1 downto 0);
indices_PLB_MRearbitrate: in vl_logic;
indices_PLB_MTimeout: in vl_logic;
indices_PLB_MBusy: in vl_logic;
indices_PLB_MRdErr: in vl_logic;
indices_PLB_MWrErr: in vl_logic;
indices_PLB_MIRQ: in vl_logic;
indices_PLB_MRdDBus: in vl_logic_vector;
indices_PLB_MRdWdAddr: in vl_logic_vector(3 downto 0);
indices_PLB_MRdDAck: in vl_logic;
indices_PLB_MRdBTerm: in vl_logic;
indices_PLB_MWrDAck: in vl_logic;
indices_PLB_MWrBTerm: in vl_logic;
splb_slv0_SPLB_Clk: in vl_logic;
splb_slv0_SPLB_Rst: in vl_logic;
splb_slv0_PLB_ABus: in vl_logic_vector(31 downto 0);
splb_slv0_PLB_UABus: in vl_logic_vector(31 downto 0);
splb_slv0_PLB_PAValid: in vl_logic;
splb_slv0_PLB_SAValid: in vl_logic;
splb_slv0_PLB_rdPrim: in vl_logic;
splb_slv0_PLB_wrPrim: in vl_logic;
splb_slv0_PLB_masterID: in vl_logic_vector;
splb_slv0_PLB_abort: in vl_logic;
splb_slv0_PLB_busLock: in vl_logic;
splb_slv0_PLB_RNW: in vl_logic;
splb_slv0_PLB_BE: in vl_logic_vector;
splb_slv0_PLB_MSize: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_size: in vl_logic_vector(3 downto 0);
splb_slv0_PLB_type: in vl_logic_vector(2 downto 0);
splb_slv0_PLB_lockErr: in vl_logic;
splb_slv0_PLB_wrDBus: in vl_logic_vector;
splb_slv0_PLB_wrBurst: in vl_logic;
splb_slv0_PLB_rdBurst: in vl_logic;
splb_slv0_PLB_wrPendReq: in vl_logic;
splb_slv0_PLB_rdPendReq: in vl_logic;
splb_slv0_PLB_wrPendPri: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_rdPendPri: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_reqPri: in vl_logic_vector(1 downto 0);
splb_slv0_PLB_TAttribute: in vl_logic_vector(15 downto 0);
splb_slv0_Sl_addrAck: out vl_logic;
splb_slv0_Sl_SSize: out vl_logic_vector(1 downto 0);
splb_slv0_Sl_wait: out vl_logic;
splb_slv0_Sl_rearbitrate: out vl_logic;
splb_slv0_Sl_wrDAck: out vl_logic;
splb_slv0_Sl_wrComp: out vl_logic;
splb_slv0_Sl_wrBTerm: out vl_logic;
splb_slv0_Sl_rdDBus: out vl_logic_vector;
splb_slv0_Sl_rdWdAddr: out vl_logic_vector(3 downto 0);
splb_slv0_Sl_rdDAck: out vl_logic;
splb_slv0_Sl_rdComp: out vl_logic;
splb_slv0_Sl_rdBTerm: out vl_logic;
splb_slv0_Sl_MBusy: out vl_logic_vector;
splb_slv0_Sl_MWrErr: out vl_logic_vector;
splb_slv0_Sl_MRdErr: out vl_logic_vector;
splb_slv0_Sl_MIRQ: out vl_logic_vector;
aresetn : in vl_logic;
aclk : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_initials_buckets_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_finals_buckets_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_nfa_forward_buckets_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_sample_buffer_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_indices_REMOTE_DESTINATION_ADDRESS : constant is 1;
attribute mti_svvh_generic_type of C_indices_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_indices_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_indices_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_BASEADDR : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_HIGHADDR : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_AWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_NUM_MASTERS : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_MID_WIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_NATIVE_DWIDTH : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_P2P : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_SUPPORT_BURSTS : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_SMALLEST_MASTER : constant is 1;
attribute mti_svvh_generic_type of C_SPLB_SLV0_INCLUDE_DPHASE_TIMER : constant is 1;
attribute mti_svvh_generic_type of RESET_ACTIVE_LOW : constant is 1;
end nfa_accept_samples_generic_hw_top;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncrambw
-- File: syncrambw.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Synchronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncrambw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end;
architecture rtl of syncrambw is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2*dbits/8;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0) and (tech /= ut90);
signal xenable, xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
sbw : if has_srambw(tech) = 1 generate
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_be generic map (abits, dbits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
customout(customout'high downto custombits) <= (others => '0');
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncrambw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nosbw : if has_srambw(tech) = 0 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataoutx(i*8+7 downto i*8), enable(i), write(i), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
dataout <= dataoutx;
end generate;
custominx(custominx'high downto (dbits/8)*custombits) <= (others => '0');
custominx((dbits/8)*custombits-1 downto 0) <= customin;
nocust: if has_srambw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc772.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p08n01i00772ent_a IS
port ( C1 : inout Bit ;
C2 : out Bit );
END c01s01b01x02p08n01i00772ent_a;
ARCHITECTURE c01s01b01x02p08n01i00772arch_a OF c01s01b01x02p08n01i00772ent_a IS
BEGIN
c2 <= c1;
END c01s01b01x02p08n01i00772arch_a;
ENTITY c01s01b01x02p08n01i00772ent IS
port ( P1 : inout Bit ;
P2 : out Bit );
END c01s01b01x02p08n01i00772ent;
ARCHITECTURE c01s01b01x02p08n01i00772arch OF c01s01b01x02p08n01i00772ent IS
component c01s01b01x02p08n01i00772ent_b
port ( C1 : inout Bit ;
C2 : out Bit );
end component ;
for L : c01s01b01x02p08n01i00772ent_b use entity work.c01s01b01x02p08n01i00772ent_a(c01s01b01x02p08n01i00772arch_a);
BEGIN
L : c01s01b01x02p08n01i00772ent_b port map (p1, p2);
--Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p08n01i00772"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p08n01i00772arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc772.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p08n01i00772ent_a IS
port ( C1 : inout Bit ;
C2 : out Bit );
END c01s01b01x02p08n01i00772ent_a;
ARCHITECTURE c01s01b01x02p08n01i00772arch_a OF c01s01b01x02p08n01i00772ent_a IS
BEGIN
c2 <= c1;
END c01s01b01x02p08n01i00772arch_a;
ENTITY c01s01b01x02p08n01i00772ent IS
port ( P1 : inout Bit ;
P2 : out Bit );
END c01s01b01x02p08n01i00772ent;
ARCHITECTURE c01s01b01x02p08n01i00772arch OF c01s01b01x02p08n01i00772ent IS
component c01s01b01x02p08n01i00772ent_b
port ( C1 : inout Bit ;
C2 : out Bit );
end component ;
for L : c01s01b01x02p08n01i00772ent_b use entity work.c01s01b01x02p08n01i00772ent_a(c01s01b01x02p08n01i00772arch_a);
BEGIN
L : c01s01b01x02p08n01i00772ent_b port map (p1, p2);
--Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p08n01i00772"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p08n01i00772arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc772.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p08n01i00772ent_a IS
port ( C1 : inout Bit ;
C2 : out Bit );
END c01s01b01x02p08n01i00772ent_a;
ARCHITECTURE c01s01b01x02p08n01i00772arch_a OF c01s01b01x02p08n01i00772ent_a IS
BEGIN
c2 <= c1;
END c01s01b01x02p08n01i00772arch_a;
ENTITY c01s01b01x02p08n01i00772ent IS
port ( P1 : inout Bit ;
P2 : out Bit );
END c01s01b01x02p08n01i00772ent;
ARCHITECTURE c01s01b01x02p08n01i00772arch OF c01s01b01x02p08n01i00772ent IS
component c01s01b01x02p08n01i00772ent_b
port ( C1 : inout Bit ;
C2 : out Bit );
end component ;
for L : c01s01b01x02p08n01i00772ent_b use entity work.c01s01b01x02p08n01i00772ent_a(c01s01b01x02p08n01i00772arch_a);
BEGIN
L : c01s01b01x02p08n01i00772ent_b port map (p1, p2);
--Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p08n01i00772"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p08n01i00772arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package internoc_pack is
--constants
constant INVALID_INTERFACE : std_logic_vector(2 downto 0) := (others=>'1');
constant UART_INTERFACE : std_logic_vector(2 downto 0) := "001";
constant SPI_INTERFACE : std_logic_vector(2 downto 0) := "010";
constant I2C_INTERFACE : std_logic_vector(2 downto 0) := "100";
constant MASTER_MODE : std_logic := '0';
constant SLAVE_MODE : std_logic := '1';
--types
type INTERFACE_T is record
addr : std_logic_vector(4 downto 0);
mode : std_logic;
interface : std_logic_vector(2 downto 0);
end record;
type INTERFACE_MAP_T is array(natural range <>) of INTERFACE_T;
--functions
end package internoc_pack;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package internoc_pack is
--constants
constant INVALID_INTERFACE : std_logic_vector(2 downto 0) := (others=>'1');
constant UART_INTERFACE : std_logic_vector(2 downto 0) := "001";
constant SPI_INTERFACE : std_logic_vector(2 downto 0) := "010";
constant I2C_INTERFACE : std_logic_vector(2 downto 0) := "100";
constant MASTER_MODE : std_logic := '0';
constant SLAVE_MODE : std_logic := '1';
--types
type INTERFACE_T is record
addr : std_logic_vector(4 downto 0);
mode : std_logic;
interface : std_logic_vector(2 downto 0);
end record;
type INTERFACE_MAP_T is array(natural range <>) of INTERFACE_T;
--functions
end package internoc_pack;
|
Subsets and Splits