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-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien;
architecture generator of alien is
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 64;
constant FRAME_DELAY: integer := 50000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_y: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(24 downto 0);
signal alien_rgb, alien11_rgb, alien12_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, alive, position_in_frame,
restart)
begin
destruction <= '0';
alive_next <= alive;
if restart = '1' then
alive_next <= (others => '1');
elsif missile_arrived = '1' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien11_rgb when frame = '0' else
alien12_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_11:
entity work.alien11_rom(content)
port map(addr => addr, data => alien11_rgb);
alien_12:
entity work.alien12_rom(content)
port map(addr => addr, data => alien12_rgb);
end generator; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien;
architecture generator of alien is
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 64;
constant FRAME_DELAY: integer := 50000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_y: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(24 downto 0);
signal alien_rgb, alien11_rgb, alien12_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, alive, position_in_frame,
restart)
begin
destruction <= '0';
alive_next <= alive;
if restart = '1' then
alive_next <= (others => '1');
elsif missile_arrived = '1' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien11_rgb when frame = '0' else
alien12_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_11:
entity work.alien11_rom(content)
port map(addr => addr, data => alien11_rgb);
alien_12:
entity work.alien12_rom(content)
port map(addr => addr, data => alien12_rgb);
end generator; |
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity atomkernal is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of atomkernal is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"50";
when x"001" => DATA <= x"4C";
when x"002" => DATA <= x"4F";
when x"003" => DATA <= x"54";
when x"004" => DATA <= x"F5";
when x"005" => DATA <= x"4E";
when x"006" => DATA <= x"44";
when x"007" => DATA <= x"52";
when x"008" => DATA <= x"41";
when x"009" => DATA <= x"57";
when x"00A" => DATA <= x"F5";
when x"00B" => DATA <= x"42";
when x"00C" => DATA <= x"4D";
when x"00D" => DATA <= x"4F";
when x"00E" => DATA <= x"56";
when x"00F" => DATA <= x"45";
when x"010" => DATA <= x"F5";
when x"011" => DATA <= x"46";
when x"012" => DATA <= x"43";
when x"013" => DATA <= x"4C";
when x"014" => DATA <= x"45";
when x"015" => DATA <= x"41";
when x"016" => DATA <= x"52";
when x"017" => DATA <= x"F6";
when x"018" => DATA <= x"7B";
when x"019" => DATA <= x"44";
when x"01A" => DATA <= x"49";
when x"01B" => DATA <= x"4D";
when x"01C" => DATA <= x"F0";
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when x"01E" => DATA <= x"5B";
when x"01F" => DATA <= x"F2";
when x"020" => DATA <= x"A1";
when x"021" => DATA <= x"4F";
when x"022" => DATA <= x"4C";
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when x"024" => DATA <= x"F5";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"57";
when x"027" => DATA <= x"41";
when x"028" => DATA <= x"49";
when x"029" => DATA <= x"54";
when x"02A" => DATA <= x"F1";
when x"02B" => DATA <= x"4C";
when x"02C" => DATA <= x"C5";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"A4";
when x"02F" => DATA <= x"5E";
when x"030" => DATA <= x"B1";
when x"031" => DATA <= x"05";
when x"032" => DATA <= x"C9";
when x"033" => DATA <= x"40";
when x"034" => DATA <= x"90";
when x"035" => DATA <= x"12";
when x"036" => DATA <= x"C9";
when x"037" => DATA <= x"5B";
when x"038" => DATA <= x"B0";
when x"039" => DATA <= x"0E";
when x"03A" => DATA <= x"C8";
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when x"03D" => DATA <= x"D0";
when x"03E" => DATA <= x"09";
when x"03F" => DATA <= x"20";
when x"040" => DATA <= x"8B";
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when x"042" => DATA <= x"20";
when x"043" => DATA <= x"4F";
when x"044" => DATA <= x"C9";
when x"045" => DATA <= x"4C";
when x"046" => DATA <= x"62";
when x"047" => DATA <= x"C9";
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when x"049" => DATA <= x"24";
when x"04A" => DATA <= x"CA";
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when x"04C" => DATA <= x"FF";
when x"04D" => DATA <= x"A4";
when x"04E" => DATA <= x"5E";
when x"04F" => DATA <= x"C6";
when x"050" => DATA <= x"5E";
when x"051" => DATA <= x"B1";
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when x"053" => DATA <= x"C9";
when x"054" => DATA <= x"40";
when x"055" => DATA <= x"90";
when x"056" => DATA <= x"09";
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when x"059" => DATA <= x"B0";
when x"05A" => DATA <= x"05";
when x"05B" => DATA <= x"C8";
when x"05C" => DATA <= x"D1";
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when x"05E" => DATA <= x"F0";
when x"05F" => DATA <= x"25";
when x"060" => DATA <= x"A4";
when x"061" => DATA <= x"5E";
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when x"063" => DATA <= x"C8";
when x"064" => DATA <= x"BD";
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when x"066" => DATA <= x"F0";
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when x"068" => DATA <= x"0C";
when x"069" => DATA <= x"D1";
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when x"06C" => DATA <= x"F5";
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when x"070" => DATA <= x"EF";
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when x"072" => DATA <= x"FA";
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when x"074" => DATA <= x"EB";
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when x"076" => DATA <= x"53";
when x"077" => DATA <= x"BD";
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when x"079" => DATA <= x"F0";
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when x"07B" => DATA <= x"52";
when x"07C" => DATA <= x"84";
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when x"07F" => DATA <= x"04";
when x"080" => DATA <= x"E6";
when x"081" => DATA <= x"5E";
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when x"083" => DATA <= x"52";
when x"084" => DATA <= x"00";
when x"085" => DATA <= x"20";
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when x"088" => DATA <= x"4C";
when x"089" => DATA <= x"F1";
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when x"08B" => DATA <= x"C8";
when x"08C" => DATA <= x"84";
when x"08D" => DATA <= x"03";
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when x"08F" => DATA <= x"40";
when x"090" => DATA <= x"48";
when x"091" => DATA <= x"20";
when x"092" => DATA <= x"BC";
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when x"094" => DATA <= x"68";
when x"095" => DATA <= x"A8";
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when x"098" => DATA <= x"0A";
when x"099" => DATA <= x"36";
when x"09A" => DATA <= x"24";
when x"09B" => DATA <= x"0A";
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when x"09D" => DATA <= x"24";
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when x"09F" => DATA <= x"79";
when x"0A0" => DATA <= x"EB";
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when x"0A2" => DATA <= x"95";
when x"0A3" => DATA <= x"15";
when x"0A4" => DATA <= x"B5";
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when x"0A6" => DATA <= x"79";
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when x"0AA" => DATA <= x"24";
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when x"0AE" => DATA <= x"A5";
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when x"0B2" => DATA <= x"F0";
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when x"0B6" => DATA <= x"C4";
when x"0B7" => DATA <= x"90";
when x"0B8" => DATA <= x"1E";
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when x"0BA" => DATA <= x"BC";
when x"0BB" => DATA <= x"C8";
when x"0BC" => DATA <= x"CA";
when x"0BD" => DATA <= x"CA";
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when x"0BF" => DATA <= x"04";
when x"0C0" => DATA <= x"B4";
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when x"0C2" => DATA <= x"38";
when x"0C3" => DATA <= x"A5";
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when x"0C5" => DATA <= x"99";
when x"0C6" => DATA <= x"21";
when x"0C7" => DATA <= x"03";
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when x"0CA" => DATA <= x"85";
when x"0CB" => DATA <= x"23";
when x"0CC" => DATA <= x"A5";
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when x"0CE" => DATA <= x"99";
when x"0CF" => DATA <= x"3C";
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when x"0D2" => DATA <= x"26";
when x"0D3" => DATA <= x"4C";
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when x"0D5" => DATA <= x"F1";
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when x"0D7" => DATA <= x"A4";
when x"0D8" => DATA <= x"03";
when x"0D9" => DATA <= x"B1";
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when x"0DC" => DATA <= x"40";
when x"0DD" => DATA <= x"90";
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when x"0E0" => DATA <= x"5B";
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when x"0E3" => DATA <= x"C8";
when x"0E4" => DATA <= x"D1";
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when x"0E6" => DATA <= x"D0";
when x"0E7" => DATA <= x"EE";
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when x"0EA" => DATA <= x"48";
when x"0EB" => DATA <= x"C8";
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when x"0F2" => DATA <= x"A8";
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when x"0F5" => DATA <= x"99";
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when x"100" => DATA <= x"B4";
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when x"102" => DATA <= x"C8";
when x"103" => DATA <= x"D0";
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when x"105" => DATA <= x"F6";
when x"106" => DATA <= x"25";
when x"107" => DATA <= x"98";
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when x"115" => DATA <= x"65";
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when x"120" => DATA <= x"23";
when x"121" => DATA <= x"D1";
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when x"123" => DATA <= x"D0";
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when x"125" => DATA <= x"4A";
when x"126" => DATA <= x"91";
when x"127" => DATA <= x"23";
when x"128" => DATA <= x"D1";
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when x"12A" => DATA <= x"D0";
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when x"12D" => DATA <= x"34";
when x"12E" => DATA <= x"C4";
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when x"131" => DATA <= x"A4";
when x"132" => DATA <= x"03";
when x"133" => DATA <= x"B1";
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when x"135" => DATA <= x"C9";
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when x"138" => DATA <= x"05";
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when x"13C" => DATA <= x"AE";
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when x"140" => DATA <= x"C5";
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when x"150" => DATA <= x"66";
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when x"15E" => DATA <= x"8A";
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when x"16E" => DATA <= x"53";
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when x"171" => DATA <= x"24";
when x"172" => DATA <= x"53";
when x"173" => DATA <= x"19";
when x"174" => DATA <= x"A1";
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when x"177" => DATA <= x"5B";
when x"178" => DATA <= x"5B";
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when x"17A" => DATA <= x"69";
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when x"17C" => DATA <= x"24";
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when x"188" => DATA <= x"9C";
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when x"18F" => DATA <= x"34";
when x"190" => DATA <= x"11";
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when x"193" => DATA <= x"23";
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when x"196" => DATA <= x"62";
when x"197" => DATA <= x"5A";
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when x"199" => DATA <= x"26";
when x"19A" => DATA <= x"62";
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when x"19C" => DATA <= x"88";
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when x"19F" => DATA <= x"C8";
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when x"1A2" => DATA <= x"44";
when x"1A3" => DATA <= x"E8";
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when x"1A5" => DATA <= x"00";
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when x"1A8" => DATA <= x"84";
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when x"1AC" => DATA <= x"6E";
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when x"1B2" => DATA <= x"F2";
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when x"1B5" => DATA <= x"00";
when x"1B6" => DATA <= x"AA";
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when x"1B9" => DATA <= x"74";
when x"1BA" => DATA <= x"74";
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when x"1BC" => DATA <= x"72";
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when x"1C1" => DATA <= x"B2";
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when x"1C3" => DATA <= x"22";
when x"1C4" => DATA <= x"00";
when x"1C5" => DATA <= x"1A";
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when x"1C8" => DATA <= x"26";
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when x"1CB" => DATA <= x"88";
when x"1CC" => DATA <= x"C8";
when x"1CD" => DATA <= x"C4";
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when x"1CF" => DATA <= x"26";
when x"1D0" => DATA <= x"48";
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when x"1D2" => DATA <= x"44";
when x"1D3" => DATA <= x"A2";
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when x"1D5" => DATA <= x"00";
when x"1D6" => DATA <= x"02";
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when x"1DC" => DATA <= x"01";
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when x"1E2" => DATA <= x"00";
when x"1E3" => DATA <= x"00";
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when x"1E5" => DATA <= x"00";
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when x"1EE" => DATA <= x"00";
when x"1EF" => DATA <= x"00";
when x"1F0" => DATA <= x"E4";
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when x"1F2" => DATA <= x"80";
when x"1F3" => DATA <= x"00";
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when x"1F5" => DATA <= x"00";
when x"1F6" => DATA <= x"08";
when x"1F7" => DATA <= x"08";
when x"1F8" => DATA <= x"F8";
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when x"1FA" => DATA <= x"F4";
when x"1FB" => DATA <= x"0C";
when x"1FC" => DATA <= x"10";
when x"1FD" => DATA <= x"04";
when x"1FE" => DATA <= x"F4";
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when x"200" => DATA <= x"20";
when x"201" => DATA <= x"10";
when x"202" => DATA <= x"00";
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when x"204" => DATA <= x"0F";
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when x"206" => DATA <= x"01";
when x"207" => DATA <= x"01";
when x"208" => DATA <= x"11";
when x"209" => DATA <= x"11";
when x"20A" => DATA <= x"02";
when x"20B" => DATA <= x"02";
when x"20C" => DATA <= x"11";
when x"20D" => DATA <= x"11";
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when x"20F" => DATA <= x"12";
when x"210" => DATA <= x"02";
when x"211" => DATA <= x"00";
when x"212" => DATA <= x"08";
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when x"214" => DATA <= x"18";
when x"215" => DATA <= x"20";
when x"216" => DATA <= x"28";
when x"217" => DATA <= x"30";
when x"218" => DATA <= x"38";
when x"219" => DATA <= x"40";
when x"21A" => DATA <= x"48";
when x"21B" => DATA <= x"50";
when x"21C" => DATA <= x"58";
when x"21D" => DATA <= x"60";
when x"21E" => DATA <= x"68";
when x"21F" => DATA <= x"70";
when x"220" => DATA <= x"78";
when x"221" => DATA <= x"80";
when x"222" => DATA <= x"88";
when x"223" => DATA <= x"90";
when x"224" => DATA <= x"98";
when x"225" => DATA <= x"A0";
when x"226" => DATA <= x"A8";
when x"227" => DATA <= x"B0";
when x"228" => DATA <= x"B8";
when x"229" => DATA <= x"C0";
when x"22A" => DATA <= x"C8";
when x"22B" => DATA <= x"D0";
when x"22C" => DATA <= x"D8";
when x"22D" => DATA <= x"E0";
when x"22E" => DATA <= x"E8";
when x"22F" => DATA <= x"F0";
when x"230" => DATA <= x"F8";
when x"231" => DATA <= x"0C";
when x"232" => DATA <= x"2C";
when x"233" => DATA <= x"4C";
when x"234" => DATA <= x"4C";
when x"235" => DATA <= x"8C";
when x"236" => DATA <= x"AC";
when x"237" => DATA <= x"CC";
when x"238" => DATA <= x"EC";
when x"239" => DATA <= x"8A";
when x"23A" => DATA <= x"9A";
when x"23B" => DATA <= x"AA";
when x"23C" => DATA <= x"BA";
when x"23D" => DATA <= x"CA";
when x"23E" => DATA <= x"DA";
when x"23F" => DATA <= x"EA";
when x"240" => DATA <= x"FA";
when x"241" => DATA <= x"0E";
when x"242" => DATA <= x"2E";
when x"243" => DATA <= x"4E";
when x"244" => DATA <= x"6E";
when x"245" => DATA <= x"8E";
when x"246" => DATA <= x"AE";
when x"247" => DATA <= x"CE";
when x"248" => DATA <= x"EE";
when x"249" => DATA <= x"0D";
when x"24A" => DATA <= x"2D";
when x"24B" => DATA <= x"4D";
when x"24C" => DATA <= x"6D";
when x"24D" => DATA <= x"8D";
when x"24E" => DATA <= x"AD";
when x"24F" => DATA <= x"CD";
when x"250" => DATA <= x"ED";
when x"251" => DATA <= x"0D";
when x"252" => DATA <= x"0D";
when x"253" => DATA <= x"0C";
when x"254" => DATA <= x"0D";
when x"255" => DATA <= x"0E";
when x"256" => DATA <= x"0D";
when x"257" => DATA <= x"0C";
when x"258" => DATA <= x"0D";
when x"259" => DATA <= x"0D";
when x"25A" => DATA <= x"0D";
when x"25B" => DATA <= x"0C";
when x"25C" => DATA <= x"0D";
when x"25D" => DATA <= x"0D";
when x"25E" => DATA <= x"0D";
when x"25F" => DATA <= x"0C";
when x"260" => DATA <= x"0D";
when x"261" => DATA <= x"0F";
when x"262" => DATA <= x"0D";
when x"263" => DATA <= x"0C";
when x"264" => DATA <= x"0D";
when x"265" => DATA <= x"09";
when x"266" => DATA <= x"0D";
when x"267" => DATA <= x"0C";
when x"268" => DATA <= x"0D";
when x"269" => DATA <= x"08";
when x"26A" => DATA <= x"0D";
when x"26B" => DATA <= x"0C";
when x"26C" => DATA <= x"0D";
when x"26D" => DATA <= x"08";
when x"26E" => DATA <= x"0D";
when x"26F" => DATA <= x"0C";
when x"270" => DATA <= x"0D";
when x"271" => DATA <= x"0F";
when x"272" => DATA <= x"06";
when x"273" => DATA <= x"0B";
when x"274" => DATA <= x"0B";
when x"275" => DATA <= x"04";
when x"276" => DATA <= x"0A";
when x"277" => DATA <= x"08";
when x"278" => DATA <= x"08";
when x"279" => DATA <= x"0D";
when x"27A" => DATA <= x"0D";
when x"27B" => DATA <= x"0D";
when x"27C" => DATA <= x"0D";
when x"27D" => DATA <= x"0D";
when x"27E" => DATA <= x"0F";
when x"27F" => DATA <= x"0D";
when x"280" => DATA <= x"0F";
when x"281" => DATA <= x"07";
when x"282" => DATA <= x"07";
when x"283" => DATA <= x"07";
when x"284" => DATA <= x"07";
when x"285" => DATA <= x"05";
when x"286" => DATA <= x"09";
when x"287" => DATA <= x"03";
when x"288" => DATA <= x"03";
when x"289" => DATA <= x"01";
when x"28A" => DATA <= x"01";
when x"28B" => DATA <= x"01";
when x"28C" => DATA <= x"01";
when x"28D" => DATA <= x"02";
when x"28E" => DATA <= x"01";
when x"28F" => DATA <= x"01";
when x"290" => DATA <= x"01";
when x"291" => DATA <= x"A4";
when x"292" => DATA <= x"03";
when x"293" => DATA <= x"B1";
when x"294" => DATA <= x"05";
when x"295" => DATA <= x"E6";
when x"296" => DATA <= x"03";
when x"297" => DATA <= x"C9";
when x"298" => DATA <= x"20";
when x"299" => DATA <= x"F0";
when x"29A" => DATA <= x"F6";
when x"29B" => DATA <= x"60";
when x"29C" => DATA <= x"E6";
when x"29D" => DATA <= x"03";
when x"29E" => DATA <= x"4C";
when x"29F" => DATA <= x"1B";
when x"2A0" => DATA <= x"C3";
when x"2A1" => DATA <= x"B1";
when x"2A2" => DATA <= x"05";
when x"2A3" => DATA <= x"C9";
when x"2A4" => DATA <= x"5D";
when x"2A5" => DATA <= x"F0";
when x"2A6" => DATA <= x"F5";
when x"2A7" => DATA <= x"20";
when x"2A8" => DATA <= x"F6";
when x"2A9" => DATA <= x"C4";
when x"2AA" => DATA <= x"C6";
when x"2AB" => DATA <= x"03";
when x"2AC" => DATA <= x"20";
when x"2AD" => DATA <= x"8E";
when x"2AE" => DATA <= x"F3";
when x"2AF" => DATA <= x"C6";
when x"2B0" => DATA <= x"03";
when x"2B1" => DATA <= x"A5";
when x"2B2" => DATA <= x"52";
when x"2B3" => DATA <= x"48";
when x"2B4" => DATA <= x"A5";
when x"2B5" => DATA <= x"53";
when x"2B6" => DATA <= x"48";
when x"2B7" => DATA <= x"AD";
when x"2B8" => DATA <= x"21";
when x"2B9" => DATA <= x"03";
when x"2BA" => DATA <= x"48";
when x"2BB" => DATA <= x"A9";
when x"2BC" => DATA <= x"00";
when x"2BD" => DATA <= x"85";
when x"2BE" => DATA <= x"34";
when x"2BF" => DATA <= x"85";
when x"2C0" => DATA <= x"43";
when x"2C1" => DATA <= x"A9";
when x"2C2" => DATA <= x"05";
when x"2C3" => DATA <= x"8D";
when x"2C4" => DATA <= x"21";
when x"2C5" => DATA <= x"03";
when x"2C6" => DATA <= x"A5";
when x"2C7" => DATA <= x"01";
when x"2C8" => DATA <= x"85";
when x"2C9" => DATA <= x"16";
when x"2CA" => DATA <= x"A5";
when x"2CB" => DATA <= x"02";
when x"2CC" => DATA <= x"85";
when x"2CD" => DATA <= x"25";
when x"2CE" => DATA <= x"20";
when x"2CF" => DATA <= x"89";
when x"2D0" => DATA <= x"C5";
when x"2D1" => DATA <= x"20";
when x"2D2" => DATA <= x"79";
when x"2D3" => DATA <= x"F3";
when x"2D4" => DATA <= x"68";
when x"2D5" => DATA <= x"8D";
when x"2D6" => DATA <= x"21";
when x"2D7" => DATA <= x"03";
when x"2D8" => DATA <= x"68";
when x"2D9" => DATA <= x"20";
when x"2DA" => DATA <= x"7E";
when x"2DB" => DATA <= x"F3";
when x"2DC" => DATA <= x"68";
when x"2DD" => DATA <= x"20";
when x"2DE" => DATA <= x"76";
when x"2DF" => DATA <= x"F3";
when x"2E0" => DATA <= x"A0";
when x"2E1" => DATA <= x"00";
when x"2E2" => DATA <= x"C4";
when x"2E3" => DATA <= x"00";
when x"2E4" => DATA <= x"F0";
when x"2E5" => DATA <= x"09";
when x"2E6" => DATA <= x"B9";
when x"2E7" => DATA <= x"66";
when x"2E8" => DATA <= x"00";
when x"2E9" => DATA <= x"20";
when x"2EA" => DATA <= x"76";
when x"2EB" => DATA <= x"F3";
when x"2EC" => DATA <= x"C8";
when x"2ED" => DATA <= x"D0";
when x"2EE" => DATA <= x"F3";
when x"2EF" => DATA <= x"C0";
when x"2F0" => DATA <= x"03";
when x"2F1" => DATA <= x"F0";
when x"2F2" => DATA <= x"0C";
when x"2F3" => DATA <= x"20";
when x"2F4" => DATA <= x"79";
when x"2F5" => DATA <= x"F3";
when x"2F6" => DATA <= x"20";
when x"2F7" => DATA <= x"4C";
when x"2F8" => DATA <= x"CA";
when x"2F9" => DATA <= x"20";
when x"2FA" => DATA <= x"4C";
when x"2FB" => DATA <= x"CA";
when x"2FC" => DATA <= x"C8";
when x"2FD" => DATA <= x"D0";
when x"2FE" => DATA <= x"F0";
when x"2FF" => DATA <= x"A0";
when x"300" => DATA <= x"00";
when x"301" => DATA <= x"B1";
when x"302" => DATA <= x"05";
when x"303" => DATA <= x"C9";
when x"304" => DATA <= x"3B";
when x"305" => DATA <= x"F0";
when x"306" => DATA <= x"0A";
when x"307" => DATA <= x"C9";
when x"308" => DATA <= x"0D";
when x"309" => DATA <= x"F0";
when x"30A" => DATA <= x"06";
when x"30B" => DATA <= x"20";
when x"30C" => DATA <= x"4C";
when x"30D" => DATA <= x"CA";
when x"30E" => DATA <= x"C8";
when x"30F" => DATA <= x"D0";
when x"310" => DATA <= x"F0";
when x"311" => DATA <= x"20";
when x"312" => DATA <= x"54";
when x"313" => DATA <= x"CD";
when x"314" => DATA <= x"20";
when x"315" => DATA <= x"E4";
when x"316" => DATA <= x"C4";
when x"317" => DATA <= x"88";
when x"318" => DATA <= x"B1";
when x"319" => DATA <= x"05";
when x"31A" => DATA <= x"C8";
when x"31B" => DATA <= x"C9";
when x"31C" => DATA <= x"3B";
when x"31D" => DATA <= x"F0";
when x"31E" => DATA <= x"0C";
when x"31F" => DATA <= x"A5";
when x"320" => DATA <= x"06";
when x"321" => DATA <= x"C9";
when x"322" => DATA <= x"01";
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when x"324" => DATA <= x"03";
when x"325" => DATA <= x"4C";
when x"326" => DATA <= x"CF";
when x"327" => DATA <= x"C2";
when x"328" => DATA <= x"20";
when x"329" => DATA <= x"1D";
when x"32A" => DATA <= x"C5";
when x"32B" => DATA <= x"4C";
when x"32C" => DATA <= x"A1";
when x"32D" => DATA <= x"F2";
when x"32E" => DATA <= x"20";
when x"32F" => DATA <= x"91";
when x"330" => DATA <= x"F2";
when x"331" => DATA <= x"85";
when x"332" => DATA <= x"66";
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when x"334" => DATA <= x"91";
when x"335" => DATA <= x"F2";
when x"336" => DATA <= x"C5";
when x"337" => DATA <= x"66";
when x"338" => DATA <= x"D0";
when x"339" => DATA <= x"10";
when x"33A" => DATA <= x"C9";
when x"33B" => DATA <= x"40";
when x"33C" => DATA <= x"90";
when x"33D" => DATA <= x"0C";
when x"33E" => DATA <= x"C9";
when x"33F" => DATA <= x"5B";
when x"340" => DATA <= x"B0";
when x"341" => DATA <= x"08";
when x"342" => DATA <= x"38";
when x"343" => DATA <= x"20";
when x"344" => DATA <= x"8E";
when x"345" => DATA <= x"F0";
when x"346" => DATA <= x"20";
when x"347" => DATA <= x"CB";
when x"348" => DATA <= x"C3";
when x"349" => DATA <= x"A0";
when x"34A" => DATA <= x"00";
when x"34B" => DATA <= x"AD";
when x"34C" => DATA <= x"31";
when x"34D" => DATA <= x"03";
when x"34E" => DATA <= x"91";
when x"34F" => DATA <= x"52";
when x"350" => DATA <= x"AD";
when x"351" => DATA <= x"4C";
when x"352" => DATA <= x"03";
when x"353" => DATA <= x"C8";
when x"354" => DATA <= x"91";
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when x"356" => DATA <= x"A9";
when x"357" => DATA <= x"00";
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when x"359" => DATA <= x"91";
when x"35A" => DATA <= x"52";
when x"35B" => DATA <= x"C8";
when x"35C" => DATA <= x"91";
when x"35D" => DATA <= x"52";
when x"35E" => DATA <= x"D0";
when x"35F" => DATA <= x"36";
when x"360" => DATA <= x"20";
when x"361" => DATA <= x"91";
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when x"363" => DATA <= x"C9";
when x"364" => DATA <= x"3B";
when x"365" => DATA <= x"F0";
when x"366" => DATA <= x"04";
when x"367" => DATA <= x"C9";
when x"368" => DATA <= x"0D";
when x"369" => DATA <= x"D0";
when x"36A" => DATA <= x"F5";
when x"36B" => DATA <= x"AD";
when x"36C" => DATA <= x"31";
when x"36D" => DATA <= x"03";
when x"36E" => DATA <= x"85";
when x"36F" => DATA <= x"52";
when x"370" => DATA <= x"AD";
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when x"372" => DATA <= x"03";
when x"373" => DATA <= x"85";
when x"374" => DATA <= x"53";
when x"375" => DATA <= x"60";
when x"376" => DATA <= x"20";
when x"377" => DATA <= x"7E";
when x"378" => DATA <= x"F3";
when x"379" => DATA <= x"A9";
when x"37A" => DATA <= x"20";
when x"37B" => DATA <= x"4C";
when x"37C" => DATA <= x"4C";
when x"37D" => DATA <= x"CA";
when x"37E" => DATA <= x"A2";
when x"37F" => DATA <= x"FF";
when x"380" => DATA <= x"48";
when x"381" => DATA <= x"4A";
when x"382" => DATA <= x"4A";
when x"383" => DATA <= x"4A";
when x"384" => DATA <= x"4A";
when x"385" => DATA <= x"20";
when x"386" => DATA <= x"F9";
when x"387" => DATA <= x"C5";
when x"388" => DATA <= x"68";
when x"389" => DATA <= x"29";
when x"38A" => DATA <= x"0F";
when x"38B" => DATA <= x"4C";
when x"38C" => DATA <= x"F9";
when x"38D" => DATA <= x"C5";
when x"38E" => DATA <= x"A2";
when x"38F" => DATA <= x"00";
when x"390" => DATA <= x"86";
when x"391" => DATA <= x"00";
when x"392" => DATA <= x"86";
when x"393" => DATA <= x"64";
when x"394" => DATA <= x"86";
when x"395" => DATA <= x"65";
when x"396" => DATA <= x"20";
when x"397" => DATA <= x"91";
when x"398" => DATA <= x"F2";
when x"399" => DATA <= x"C9";
when x"39A" => DATA <= x"3A";
when x"39B" => DATA <= x"F0";
when x"39C" => DATA <= x"91";
when x"39D" => DATA <= x"C9";
when x"39E" => DATA <= x"3B";
when x"39F" => DATA <= x"F0";
when x"3A0" => DATA <= x"CA";
when x"3A1" => DATA <= x"C9";
when x"3A2" => DATA <= x"0D";
when x"3A3" => DATA <= x"F0";
when x"3A4" => DATA <= x"C6";
when x"3A5" => DATA <= x"C9";
when x"3A6" => DATA <= x"5C";
when x"3A7" => DATA <= x"F0";
when x"3A8" => DATA <= x"B7";
when x"3A9" => DATA <= x"A0";
when x"3AA" => DATA <= x"05";
when x"3AB" => DATA <= x"38";
when x"3AC" => DATA <= x"69";
when x"3AD" => DATA <= x"00";
when x"3AE" => DATA <= x"0A";
when x"3AF" => DATA <= x"0A";
when x"3B0" => DATA <= x"0A";
when x"3B1" => DATA <= x"0A";
when x"3B2" => DATA <= x"26";
when x"3B3" => DATA <= x"6A";
when x"3B4" => DATA <= x"26";
when x"3B5" => DATA <= x"69";
when x"3B6" => DATA <= x"88";
when x"3B7" => DATA <= x"D0";
when x"3B8" => DATA <= x"F8";
when x"3B9" => DATA <= x"E8";
when x"3BA" => DATA <= x"E0";
when x"3BB" => DATA <= x"03";
when x"3BC" => DATA <= x"D0";
when x"3BD" => DATA <= x"D8";
when x"3BE" => DATA <= x"06";
when x"3BF" => DATA <= x"6A";
when x"3C0" => DATA <= x"26";
when x"3C1" => DATA <= x"69";
when x"3C2" => DATA <= x"A2";
when x"3C3" => DATA <= x"40";
when x"3C4" => DATA <= x"A5";
when x"3C5" => DATA <= x"69";
when x"3C6" => DATA <= x"DD";
when x"3C7" => DATA <= x"54";
when x"3C8" => DATA <= x"F1";
when x"3C9" => DATA <= x"F0";
when x"3CA" => DATA <= x"04";
when x"3CB" => DATA <= x"CA";
when x"3CC" => DATA <= x"D0";
when x"3CD" => DATA <= x"F8";
when x"3CE" => DATA <= x"00";
when x"3CF" => DATA <= x"BC";
when x"3D0" => DATA <= x"94";
when x"3D1" => DATA <= x"F1";
when x"3D2" => DATA <= x"C4";
when x"3D3" => DATA <= x"6A";
when x"3D4" => DATA <= x"D0";
when x"3D5" => DATA <= x"F5";
when x"3D6" => DATA <= x"BD";
when x"3D7" => DATA <= x"10";
when x"3D8" => DATA <= x"F2";
when x"3D9" => DATA <= x"85";
when x"3DA" => DATA <= x"66";
when x"3DB" => DATA <= x"BC";
when x"3DC" => DATA <= x"50";
when x"3DD" => DATA <= x"F2";
when x"3DE" => DATA <= x"84";
when x"3DF" => DATA <= x"0F";
when x"3E0" => DATA <= x"66";
when x"3E1" => DATA <= x"64";
when x"3E2" => DATA <= x"66";
when x"3E3" => DATA <= x"65";
when x"3E4" => DATA <= x"88";
when x"3E5" => DATA <= x"D0";
when x"3E6" => DATA <= x"F9";
when x"3E7" => DATA <= x"A4";
when x"3E8" => DATA <= x"0F";
when x"3E9" => DATA <= x"C0";
when x"3EA" => DATA <= x"0D";
when x"3EB" => DATA <= x"D0";
when x"3EC" => DATA <= x"05";
when x"3ED" => DATA <= x"A2";
when x"3EE" => DATA <= x"00";
when x"3EF" => DATA <= x"4C";
when x"3F0" => DATA <= x"9B";
when x"3F1" => DATA <= x"F4";
when x"3F2" => DATA <= x"20";
when x"3F3" => DATA <= x"91";
when x"3F4" => DATA <= x"F2";
when x"3F5" => DATA <= x"C9";
when x"3F6" => DATA <= x"40";
when x"3F7" => DATA <= x"F0";
when x"3F8" => DATA <= x"5B";
when x"3F9" => DATA <= x"C9";
when x"3FA" => DATA <= x"28";
when x"3FB" => DATA <= x"F0";
when x"3FC" => DATA <= x"65";
when x"3FD" => DATA <= x"A2";
when x"3FE" => DATA <= x"01";
when x"3FF" => DATA <= x"C9";
when x"400" => DATA <= x"41";
when x"401" => DATA <= x"F0";
when x"402" => DATA <= x"EC";
when x"403" => DATA <= x"C6";
when x"404" => DATA <= x"03";
when x"405" => DATA <= x"20";
when x"406" => DATA <= x"8B";
when x"407" => DATA <= x"C7";
when x"408" => DATA <= x"20";
when x"409" => DATA <= x"91";
when x"40A" => DATA <= x"F2";
when x"40B" => DATA <= x"C9";
when x"40C" => DATA <= x"2C";
when x"40D" => DATA <= x"D0";
when x"40E" => DATA <= x"31";
when x"40F" => DATA <= x"20";
when x"410" => DATA <= x"91";
when x"411" => DATA <= x"F2";
when x"412" => DATA <= x"A4";
when x"413" => DATA <= x"25";
when x"414" => DATA <= x"F0";
when x"415" => DATA <= x"15";
when x"416" => DATA <= x"A2";
when x"417" => DATA <= x"09";
when x"418" => DATA <= x"C9";
when x"419" => DATA <= x"58";
when x"41A" => DATA <= x"F0";
when x"41B" => DATA <= x"7F";
when x"41C" => DATA <= x"CA";
when x"41D" => DATA <= x"C9";
when x"41E" => DATA <= x"59";
when x"41F" => DATA <= x"D0";
when x"420" => DATA <= x"79";
when x"421" => DATA <= x"A5";
when x"422" => DATA <= x"0F";
when x"423" => DATA <= x"C9";
when x"424" => DATA <= x"09";
when x"425" => DATA <= x"D0";
when x"426" => DATA <= x"74";
when x"427" => DATA <= x"A2";
when x"428" => DATA <= x"0E";
when x"429" => DATA <= x"D0";
when x"42A" => DATA <= x"70";
when x"42B" => DATA <= x"A2";
when x"42C" => DATA <= x"04";
when x"42D" => DATA <= x"C9";
when x"42E" => DATA <= x"58";
when x"42F" => DATA <= x"F0";
when x"430" => DATA <= x"6A";
when x"431" => DATA <= x"C9";
when x"432" => DATA <= x"59";
when x"433" => DATA <= x"D0";
when x"434" => DATA <= x"65";
when x"435" => DATA <= x"CA";
when x"436" => DATA <= x"A4";
when x"437" => DATA <= x"0F";
when x"438" => DATA <= x"C0";
when x"439" => DATA <= x"03";
when x"43A" => DATA <= x"B0";
when x"43B" => DATA <= x"5F";
when x"43C" => DATA <= x"A2";
when x"43D" => DATA <= x"08";
when x"43E" => DATA <= x"D0";
when x"43F" => DATA <= x"5B";
when x"440" => DATA <= x"C6";
when x"441" => DATA <= x"03";
when x"442" => DATA <= x"A2";
when x"443" => DATA <= x"02";
when x"444" => DATA <= x"A4";
when x"445" => DATA <= x"0F";
when x"446" => DATA <= x"C0";
when x"447" => DATA <= x"0C";
when x"448" => DATA <= x"F0";
when x"449" => DATA <= x"51";
when x"44A" => DATA <= x"A2";
when x"44B" => DATA <= x"05";
when x"44C" => DATA <= x"A5";
when x"44D" => DATA <= x"25";
when x"44E" => DATA <= x"F0";
when x"44F" => DATA <= x"4B";
when x"450" => DATA <= x"A2";
when x"451" => DATA <= x"0C";
when x"452" => DATA <= x"D0";
when x"453" => DATA <= x"47";
when x"454" => DATA <= x"20";
when x"455" => DATA <= x"8B";
when x"456" => DATA <= x"C7";
when x"457" => DATA <= x"A5";
when x"458" => DATA <= x"0F";
when x"459" => DATA <= x"A2";
when x"45A" => DATA <= x"06";
when x"45B" => DATA <= x"C9";
when x"45C" => DATA <= x"01";
when x"45D" => DATA <= x"F0";
when x"45E" => DATA <= x"3C";
when x"45F" => DATA <= x"E8";
when x"460" => DATA <= x"D0";
when x"461" => DATA <= x"39";
when x"462" => DATA <= x"20";
when x"463" => DATA <= x"8B";
when x"464" => DATA <= x"C7";
when x"465" => DATA <= x"20";
when x"466" => DATA <= x"91";
when x"467" => DATA <= x"F2";
when x"468" => DATA <= x"C9";
when x"469" => DATA <= x"29";
when x"46A" => DATA <= x"F0";
when x"46B" => DATA <= x"16";
when x"46C" => DATA <= x"C9";
when x"46D" => DATA <= x"2C";
when x"46E" => DATA <= x"D0";
when x"46F" => DATA <= x"2A";
when x"470" => DATA <= x"20";
when x"471" => DATA <= x"91";
when x"472" => DATA <= x"F2";
when x"473" => DATA <= x"C9";
when x"474" => DATA <= x"58";
when x"475" => DATA <= x"D0";
when x"476" => DATA <= x"23";
when x"477" => DATA <= x"20";
when x"478" => DATA <= x"91";
when x"479" => DATA <= x"F2";
when x"47A" => DATA <= x"C9";
when x"47B" => DATA <= x"29";
when x"47C" => DATA <= x"D0";
when x"47D" => DATA <= x"1C";
when x"47E" => DATA <= x"A2";
when x"47F" => DATA <= x"0B";
when x"480" => DATA <= x"D0";
when x"481" => DATA <= x"19";
when x"482" => DATA <= x"A2";
when x"483" => DATA <= x"0D";
when x"484" => DATA <= x"A5";
when x"485" => DATA <= x"0F";
when x"486" => DATA <= x"C9";
when x"487" => DATA <= x"0B";
when x"488" => DATA <= x"F0";
when x"489" => DATA <= x"11";
when x"48A" => DATA <= x"A2";
when x"48B" => DATA <= x"0A";
when x"48C" => DATA <= x"20";
when x"48D" => DATA <= x"91";
when x"48E" => DATA <= x"F2";
when x"48F" => DATA <= x"C9";
when x"490" => DATA <= x"2C";
when x"491" => DATA <= x"D0";
when x"492" => DATA <= x"07";
when x"493" => DATA <= x"20";
when x"494" => DATA <= x"91";
when x"495" => DATA <= x"F2";
when x"496" => DATA <= x"C9";
when x"497" => DATA <= x"59";
when x"498" => DATA <= x"F0";
when x"499" => DATA <= x"01";
when x"49A" => DATA <= x"00";
when x"49B" => DATA <= x"20";
when x"49C" => DATA <= x"60";
when x"49D" => DATA <= x"F3";
when x"49E" => DATA <= x"BD";
when x"49F" => DATA <= x"D5";
when x"4A0" => DATA <= x"F1";
when x"4A1" => DATA <= x"F0";
when x"4A2" => DATA <= x"04";
when x"4A3" => DATA <= x"25";
when x"4A4" => DATA <= x"64";
when x"4A5" => DATA <= x"D0";
when x"4A6" => DATA <= x"07";
when x"4A7" => DATA <= x"BD";
when x"4A8" => DATA <= x"E4";
when x"4A9" => DATA <= x"F1";
when x"4AA" => DATA <= x"25";
when x"4AB" => DATA <= x"65";
when x"4AC" => DATA <= x"F0";
when x"4AD" => DATA <= x"EC";
when x"4AE" => DATA <= x"18";
when x"4AF" => DATA <= x"BD";
when x"4B0" => DATA <= x"F3";
when x"4B1" => DATA <= x"F1";
when x"4B2" => DATA <= x"65";
when x"4B3" => DATA <= x"66";
when x"4B4" => DATA <= x"85";
when x"4B5" => DATA <= x"66";
when x"4B6" => DATA <= x"BD";
when x"4B7" => DATA <= x"02";
when x"4B8" => DATA <= x"F2";
when x"4B9" => DATA <= x"A2";
when x"4BA" => DATA <= x"00";
when x"4BB" => DATA <= x"86";
when x"4BC" => DATA <= x"04";
when x"4BD" => DATA <= x"A4";
when x"4BE" => DATA <= x"16";
when x"4BF" => DATA <= x"84";
when x"4C0" => DATA <= x"67";
when x"4C1" => DATA <= x"A4";
when x"4C2" => DATA <= x"25";
when x"4C3" => DATA <= x"84";
when x"4C4" => DATA <= x"68";
when x"4C5" => DATA <= x"C9";
when x"4C6" => DATA <= x"0F";
when x"4C7" => DATA <= x"F0";
when x"4C8" => DATA <= x"23";
when x"4C9" => DATA <= x"29";
when x"4CA" => DATA <= x"0F";
when x"4CB" => DATA <= x"A8";
when x"4CC" => DATA <= x"C8";
when x"4CD" => DATA <= x"84";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"C0";
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when x"4D1" => DATA <= x"D0";
when x"4D2" => DATA <= x"04";
when x"4D3" => DATA <= x"A4";
when x"4D4" => DATA <= x"68";
when x"4D5" => DATA <= x"D0";
when x"4D6" => DATA <= x"C3";
when x"4D7" => DATA <= x"A0";
when x"4D8" => DATA <= x"00";
when x"4D9" => DATA <= x"B9";
when x"4DA" => DATA <= x"66";
when x"4DB" => DATA <= x"00";
when x"4DC" => DATA <= x"91";
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when x"4DE" => DATA <= x"C8";
when x"4DF" => DATA <= x"EE";
when x"4E0" => DATA <= x"31";
when x"4E1" => DATA <= x"03";
when x"4E2" => DATA <= x"D0";
when x"4E3" => DATA <= x"03";
when x"4E4" => DATA <= x"EE";
when x"4E5" => DATA <= x"4C";
when x"4E6" => DATA <= x"03";
when x"4E7" => DATA <= x"C4";
when x"4E8" => DATA <= x"00";
when x"4E9" => DATA <= x"D0";
when x"4EA" => DATA <= x"EE";
when x"4EB" => DATA <= x"60";
when x"4EC" => DATA <= x"A9";
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when x"4EE" => DATA <= x"85";
when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"38";
when x"4F1" => DATA <= x"A5";
when x"4F2" => DATA <= x"67";
when x"4F3" => DATA <= x"ED";
when x"4F4" => DATA <= x"31";
when x"4F5" => DATA <= x"03";
when x"4F6" => DATA <= x"85";
when x"4F7" => DATA <= x"67";
when x"4F8" => DATA <= x"A5";
when x"4F9" => DATA <= x"68";
when x"4FA" => DATA <= x"ED";
when x"4FB" => DATA <= x"4C";
when x"4FC" => DATA <= x"03";
when x"4FD" => DATA <= x"85";
when x"4FE" => DATA <= x"68";
when x"4FF" => DATA <= x"38";
when x"500" => DATA <= x"A5";
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when x"502" => DATA <= x"E9";
when x"503" => DATA <= x"02";
when x"504" => DATA <= x"85";
when x"505" => DATA <= x"67";
when x"506" => DATA <= x"A8";
when x"507" => DATA <= x"A5";
when x"508" => DATA <= x"68";
when x"509" => DATA <= x"E9";
when x"50A" => DATA <= x"00";
when x"50B" => DATA <= x"F0";
when x"50C" => DATA <= x"1F";
when x"50D" => DATA <= x"C9";
when x"50E" => DATA <= x"FF";
when x"50F" => DATA <= x"F0";
when x"510" => DATA <= x"16";
when x"511" => DATA <= x"20";
when x"512" => DATA <= x"D1";
when x"513" => DATA <= x"F7";
when x"514" => DATA <= x"4F";
when x"515" => DATA <= x"55";
when x"516" => DATA <= x"54";
when x"517" => DATA <= x"20";
when x"518" => DATA <= x"4F";
when x"519" => DATA <= x"46";
when x"51A" => DATA <= x"20";
when x"51B" => DATA <= x"52";
when x"51C" => DATA <= x"41";
when x"51D" => DATA <= x"4E";
when x"51E" => DATA <= x"47";
when x"51F" => DATA <= x"45";
when x"520" => DATA <= x"3A";
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when x"523" => DATA <= x"84";
when x"524" => DATA <= x"67";
when x"525" => DATA <= x"30";
when x"526" => DATA <= x"B0";
when x"527" => DATA <= x"98";
when x"528" => DATA <= x"30";
when x"529" => DATA <= x"AD";
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when x"52B" => DATA <= x"E5";
when x"52C" => DATA <= x"98";
when x"52D" => DATA <= x"10";
when x"52E" => DATA <= x"A8";
when x"52F" => DATA <= x"30";
when x"530" => DATA <= x"E0";
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when x"532" => DATA <= x"E4";
when x"533" => DATA <= x"C4";
when x"534" => DATA <= x"88";
when x"535" => DATA <= x"84";
when x"536" => DATA <= x"52";
when x"537" => DATA <= x"A5";
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when x"539" => DATA <= x"85";
when x"53A" => DATA <= x"53";
when x"53B" => DATA <= x"98";
when x"53C" => DATA <= x"C8";
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when x"53E" => DATA <= x"52";
when x"53F" => DATA <= x"4C";
when x"540" => DATA <= x"9B";
when x"541" => DATA <= x"CD";
when x"542" => DATA <= x"A2";
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when x"546" => DATA <= x"A2";
when x"547" => DATA <= x"0C";
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when x"549" => DATA <= x"16";
when x"54A" => DATA <= x"E6";
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when x"54C" => DATA <= x"D0";
when x"54D" => DATA <= x"06";
when x"54E" => DATA <= x"20";
when x"54F" => DATA <= x"BC";
when x"550" => DATA <= x"C8";
when x"551" => DATA <= x"20";
when x"552" => DATA <= x"31";
when x"553" => DATA <= x"C2";
when x"554" => DATA <= x"20";
when x"555" => DATA <= x"BC";
when x"556" => DATA <= x"C8";
when x"557" => DATA <= x"20";
when x"558" => DATA <= x"31";
when x"559" => DATA <= x"C2";
when x"55A" => DATA <= x"20";
when x"55B" => DATA <= x"BC";
when x"55C" => DATA <= x"C8";
when x"55D" => DATA <= x"20";
when x"55E" => DATA <= x"E4";
when x"55F" => DATA <= x"C4";
when x"560" => DATA <= x"B5";
when x"561" => DATA <= x"15";
when x"562" => DATA <= x"85";
when x"563" => DATA <= x"5C";
when x"564" => DATA <= x"B5";
when x"565" => DATA <= x"24";
when x"566" => DATA <= x"85";
when x"567" => DATA <= x"5D";
when x"568" => DATA <= x"B5";
when x"569" => DATA <= x"14";
when x"56A" => DATA <= x"85";
when x"56B" => DATA <= x"5A";
when x"56C" => DATA <= x"B5";
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when x"56E" => DATA <= x"85";
when x"56F" => DATA <= x"5B";
when x"570" => DATA <= x"A2";
when x"571" => DATA <= x"00";
when x"572" => DATA <= x"86";
when x"573" => DATA <= x"04";
when x"574" => DATA <= x"A2";
when x"575" => DATA <= x"03";
when x"576" => DATA <= x"BD";
when x"577" => DATA <= x"C1";
when x"578" => DATA <= x"03";
when x"579" => DATA <= x"95";
when x"57A" => DATA <= x"52";
when x"57B" => DATA <= x"CA";
when x"57C" => DATA <= x"10";
when x"57D" => DATA <= x"F8";
when x"57E" => DATA <= x"A5";
when x"57F" => DATA <= x"16";
when x"580" => DATA <= x"29";
when x"581" => DATA <= x"04";
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when x"583" => DATA <= x"13";
when x"584" => DATA <= x"A2";
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when x"586" => DATA <= x"18";
when x"587" => DATA <= x"B5";
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when x"589" => DATA <= x"75";
when x"58A" => DATA <= x"52";
when x"58B" => DATA <= x"95";
when x"58C" => DATA <= x"5A";
when x"58D" => DATA <= x"B5";
when x"58E" => DATA <= x"5B";
when x"58F" => DATA <= x"75";
when x"590" => DATA <= x"53";
when x"591" => DATA <= x"95";
when x"592" => DATA <= x"5B";
when x"593" => DATA <= x"CA";
when x"594" => DATA <= x"CA";
when x"595" => DATA <= x"10";
when x"596" => DATA <= x"EF";
when x"597" => DATA <= x"A2";
when x"598" => DATA <= x"03";
when x"599" => DATA <= x"B5";
when x"59A" => DATA <= x"5A";
when x"59B" => DATA <= x"9D";
when x"59C" => DATA <= x"C1";
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when x"59E" => DATA <= x"CA";
when x"59F" => DATA <= x"10";
when x"5A0" => DATA <= x"F8";
when x"5A1" => DATA <= x"A5";
when x"5A2" => DATA <= x"16";
when x"5A3" => DATA <= x"29";
when x"5A4" => DATA <= x"03";
when x"5A5" => DATA <= x"F0";
when x"5A6" => DATA <= x"0B";
when x"5A7" => DATA <= x"85";
when x"5A8" => DATA <= x"5E";
when x"5A9" => DATA <= x"A5";
when x"5AA" => DATA <= x"16";
when x"5AB" => DATA <= x"29";
when x"5AC" => DATA <= x"08";
when x"5AD" => DATA <= x"F0";
when x"5AE" => DATA <= x"06";
when x"5AF" => DATA <= x"20";
when x"5B0" => DATA <= x"78";
when x"5B1" => DATA <= x"F6";
when x"5B2" => DATA <= x"4C";
when x"5B3" => DATA <= x"5B";
when x"5B4" => DATA <= x"C5";
when x"5B5" => DATA <= x"A2";
when x"5B6" => DATA <= x"02";
when x"5B7" => DATA <= x"38";
when x"5B8" => DATA <= x"B5";
when x"5B9" => DATA <= x"5A";
when x"5BA" => DATA <= x"F5";
when x"5BB" => DATA <= x"52";
when x"5BC" => DATA <= x"B4";
when x"5BD" => DATA <= x"52";
when x"5BE" => DATA <= x"94";
when x"5BF" => DATA <= x"5A";
when x"5C0" => DATA <= x"95";
when x"5C1" => DATA <= x"52";
when x"5C2" => DATA <= x"B4";
when x"5C3" => DATA <= x"53";
when x"5C4" => DATA <= x"B5";
when x"5C5" => DATA <= x"5B";
when x"5C6" => DATA <= x"F5";
when x"5C7" => DATA <= x"53";
when x"5C8" => DATA <= x"94";
when x"5C9" => DATA <= x"5B";
when x"5CA" => DATA <= x"95";
when x"5CB" => DATA <= x"53";
when x"5CC" => DATA <= x"95";
when x"5CD" => DATA <= x"56";
when x"5CE" => DATA <= x"10";
when x"5CF" => DATA <= x"0D";
when x"5D0" => DATA <= x"A9";
when x"5D1" => DATA <= x"00";
when x"5D2" => DATA <= x"38";
when x"5D3" => DATA <= x"F5";
when x"5D4" => DATA <= x"52";
when x"5D5" => DATA <= x"95";
when x"5D6" => DATA <= x"52";
when x"5D7" => DATA <= x"A9";
when x"5D8" => DATA <= x"00";
when x"5D9" => DATA <= x"F5";
when x"5DA" => DATA <= x"53";
when x"5DB" => DATA <= x"95";
when x"5DC" => DATA <= x"53";
when x"5DD" => DATA <= x"CA";
when x"5DE" => DATA <= x"CA";
when x"5DF" => DATA <= x"10";
when x"5E0" => DATA <= x"D6";
when x"5E1" => DATA <= x"A5";
when x"5E2" => DATA <= x"54";
when x"5E3" => DATA <= x"C5";
when x"5E4" => DATA <= x"52";
when x"5E5" => DATA <= x"A5";
when x"5E6" => DATA <= x"55";
when x"5E7" => DATA <= x"E5";
when x"5E8" => DATA <= x"53";
when x"5E9" => DATA <= x"90";
when x"5EA" => DATA <= x"31";
when x"5EB" => DATA <= x"A9";
when x"5EC" => DATA <= x"00";
when x"5ED" => DATA <= x"E5";
when x"5EE" => DATA <= x"54";
when x"5EF" => DATA <= x"85";
when x"5F0" => DATA <= x"57";
when x"5F1" => DATA <= x"A9";
when x"5F2" => DATA <= x"00";
when x"5F3" => DATA <= x"E5";
when x"5F4" => DATA <= x"55";
when x"5F5" => DATA <= x"38";
when x"5F6" => DATA <= x"6A";
when x"5F7" => DATA <= x"85";
when x"5F8" => DATA <= x"59";
when x"5F9" => DATA <= x"66";
when x"5FA" => DATA <= x"57";
when x"5FB" => DATA <= x"20";
when x"5FC" => DATA <= x"78";
when x"5FD" => DATA <= x"F6";
when x"5FE" => DATA <= x"A5";
when x"5FF" => DATA <= x"5C";
when x"600" => DATA <= x"CD";
when x"601" => DATA <= x"C3";
when x"602" => DATA <= x"03";
when x"603" => DATA <= x"D0";
when x"604" => DATA <= x"0A";
when x"605" => DATA <= x"A5";
when x"606" => DATA <= x"5D";
when x"607" => DATA <= x"CD";
when x"608" => DATA <= x"C4";
when x"609" => DATA <= x"03";
when x"60A" => DATA <= x"D0";
when x"60B" => DATA <= x"03";
when x"60C" => DATA <= x"4C";
when x"60D" => DATA <= x"5B";
when x"60E" => DATA <= x"C5";
when x"60F" => DATA <= x"20";
when x"610" => DATA <= x"55";
when x"611" => DATA <= x"F6";
when x"612" => DATA <= x"A5";
when x"613" => DATA <= x"59";
when x"614" => DATA <= x"30";
when x"615" => DATA <= x"E5";
when x"616" => DATA <= x"20";
when x"617" => DATA <= x"44";
when x"618" => DATA <= x"F6";
when x"619" => DATA <= x"4C";
when x"61A" => DATA <= x"FB";
when x"61B" => DATA <= x"F5";
when x"61C" => DATA <= x"A5";
when x"61D" => DATA <= x"53";
when x"61E" => DATA <= x"4A";
when x"61F" => DATA <= x"85";
when x"620" => DATA <= x"59";
when x"621" => DATA <= x"A5";
when x"622" => DATA <= x"52";
when x"623" => DATA <= x"6A";
when x"624" => DATA <= x"85";
when x"625" => DATA <= x"57";
when x"626" => DATA <= x"20";
when x"627" => DATA <= x"78";
when x"628" => DATA <= x"F6";
when x"629" => DATA <= x"A5";
when x"62A" => DATA <= x"5A";
when x"62B" => DATA <= x"CD";
when x"62C" => DATA <= x"C1";
when x"62D" => DATA <= x"03";
when x"62E" => DATA <= x"D0";
when x"62F" => DATA <= x"07";
when x"630" => DATA <= x"A5";
when x"631" => DATA <= x"5B";
when x"632" => DATA <= x"CD";
when x"633" => DATA <= x"C2";
when x"634" => DATA <= x"03";
when x"635" => DATA <= x"F0";
when x"636" => DATA <= x"D5";
when x"637" => DATA <= x"20";
when x"638" => DATA <= x"44";
when x"639" => DATA <= x"F6";
when x"63A" => DATA <= x"A5";
when x"63B" => DATA <= x"59";
when x"63C" => DATA <= x"10";
when x"63D" => DATA <= x"E8";
when x"63E" => DATA <= x"20";
when x"63F" => DATA <= x"55";
when x"640" => DATA <= x"F6";
when x"641" => DATA <= x"4C";
when x"642" => DATA <= x"26";
when x"643" => DATA <= x"F6";
when x"644" => DATA <= x"38";
when x"645" => DATA <= x"A5";
when x"646" => DATA <= x"57";
when x"647" => DATA <= x"E5";
when x"648" => DATA <= x"54";
when x"649" => DATA <= x"85";
when x"64A" => DATA <= x"57";
when x"64B" => DATA <= x"A5";
when x"64C" => DATA <= x"59";
when x"64D" => DATA <= x"E5";
when x"64E" => DATA <= x"55";
when x"64F" => DATA <= x"85";
when x"650" => DATA <= x"59";
when x"651" => DATA <= x"A2";
when x"652" => DATA <= x"00";
when x"653" => DATA <= x"F0";
when x"654" => DATA <= x"0F";
when x"655" => DATA <= x"18";
when x"656" => DATA <= x"A5";
when x"657" => DATA <= x"57";
when x"658" => DATA <= x"65";
when x"659" => DATA <= x"52";
when x"65A" => DATA <= x"85";
when x"65B" => DATA <= x"57";
when x"65C" => DATA <= x"A5";
when x"65D" => DATA <= x"59";
when x"65E" => DATA <= x"65";
when x"65F" => DATA <= x"53";
when x"660" => DATA <= x"85";
when x"661" => DATA <= x"59";
when x"662" => DATA <= x"A2";
when x"663" => DATA <= x"02";
when x"664" => DATA <= x"B5";
when x"665" => DATA <= x"56";
when x"666" => DATA <= x"10";
when x"667" => DATA <= x"09";
when x"668" => DATA <= x"B5";
when x"669" => DATA <= x"5A";
when x"66A" => DATA <= x"D0";
when x"66B" => DATA <= x"02";
when x"66C" => DATA <= x"D6";
when x"66D" => DATA <= x"5B";
when x"66E" => DATA <= x"D6";
when x"66F" => DATA <= x"5A";
when x"670" => DATA <= x"60";
when x"671" => DATA <= x"F6";
when x"672" => DATA <= x"5A";
when x"673" => DATA <= x"D0";
when x"674" => DATA <= x"FB";
when x"675" => DATA <= x"F6";
when x"676" => DATA <= x"5B";
when x"677" => DATA <= x"60";
when x"678" => DATA <= x"6C";
when x"679" => DATA <= x"FE";
when x"67A" => DATA <= x"03";
when x"67B" => DATA <= x"20";
when x"67C" => DATA <= x"C8";
when x"67D" => DATA <= x"C3";
when x"67E" => DATA <= x"A0";
when x"67F" => DATA <= x"00";
when x"680" => DATA <= x"A5";
when x"681" => DATA <= x"52";
when x"682" => DATA <= x"F0";
when x"683" => DATA <= x"3E";
when x"684" => DATA <= x"C9";
when x"685" => DATA <= x"05";
when x"686" => DATA <= x"90";
when x"687" => DATA <= x"02";
when x"688" => DATA <= x"A9";
when x"689" => DATA <= x"04";
when x"68A" => DATA <= x"A2";
when x"68B" => DATA <= x"80";
when x"68C" => DATA <= x"86";
when x"68D" => DATA <= x"54";
when x"68E" => DATA <= x"84";
when x"68F" => DATA <= x"53";
when x"690" => DATA <= x"85";
when x"691" => DATA <= x"52";
when x"692" => DATA <= x"AA";
when x"693" => DATA <= x"BD";
when x"694" => DATA <= x"CE";
when x"695" => DATA <= x"F6";
when x"696" => DATA <= x"A6";
when x"697" => DATA <= x"12";
when x"698" => DATA <= x"10";
when x"699" => DATA <= x"04";
when x"69A" => DATA <= x"C5";
when x"69B" => DATA <= x"12";
when x"69C" => DATA <= x"B0";
when x"69D" => DATA <= x"E1";
when x"69E" => DATA <= x"AA";
when x"69F" => DATA <= x"98";
when x"6A0" => DATA <= x"91";
when x"6A1" => DATA <= x"53";
when x"6A2" => DATA <= x"88";
when x"6A3" => DATA <= x"D0";
when x"6A4" => DATA <= x"FB";
when x"6A5" => DATA <= x"E6";
when x"6A6" => DATA <= x"54";
when x"6A7" => DATA <= x"E4";
when x"6A8" => DATA <= x"54";
when x"6A9" => DATA <= x"D0";
when x"6AA" => DATA <= x"F5";
when x"6AB" => DATA <= x"A4";
when x"6AC" => DATA <= x"52";
when x"6AD" => DATA <= x"B9";
when x"6AE" => DATA <= x"D8";
when x"6AF" => DATA <= x"F6";
when x"6B0" => DATA <= x"8D";
when x"6B1" => DATA <= x"FF";
when x"6B2" => DATA <= x"03";
when x"6B3" => DATA <= x"B9";
when x"6B4" => DATA <= x"D3";
when x"6B5" => DATA <= x"F6";
when x"6B6" => DATA <= x"8D";
when x"6B7" => DATA <= x"FE";
when x"6B8" => DATA <= x"03";
when x"6B9" => DATA <= x"B9";
when x"6BA" => DATA <= x"DD";
when x"6BB" => DATA <= x"F6";
when x"6BC" => DATA <= x"8D";
when x"6BD" => DATA <= x"00";
when x"6BE" => DATA <= x"B0";
when x"6BF" => DATA <= x"4C";
when x"6C0" => DATA <= x"58";
when x"6C1" => DATA <= x"C5";
when x"6C2" => DATA <= x"A9";
when x"6C3" => DATA <= x"40";
when x"6C4" => DATA <= x"99";
when x"6C5" => DATA <= x"00";
when x"6C6" => DATA <= x"80";
when x"6C7" => DATA <= x"99";
when x"6C8" => DATA <= x"00";
when x"6C9" => DATA <= x"81";
when x"6CA" => DATA <= x"88";
when x"6CB" => DATA <= x"D0";
when x"6CC" => DATA <= x"F7";
when x"6CD" => DATA <= x"F0";
when x"6CE" => DATA <= x"DC";
when x"6CF" => DATA <= x"84";
when x"6D0" => DATA <= x"86";
when x"6D1" => DATA <= x"8C";
when x"6D2" => DATA <= x"98";
when x"6D3" => DATA <= x"E2";
when x"6D4" => DATA <= x"3B";
when x"6D5" => DATA <= x"54";
when x"6D6" => DATA <= x"6D";
when x"6D7" => DATA <= x"AA";
when x"6D8" => DATA <= x"F6";
when x"6D9" => DATA <= x"F7";
when x"6DA" => DATA <= x"F7";
when x"6DB" => DATA <= x"F7";
when x"6DC" => DATA <= x"F7";
when x"6DD" => DATA <= x"00";
when x"6DE" => DATA <= x"30";
when x"6DF" => DATA <= x"70";
when x"6E0" => DATA <= x"B0";
when x"6E1" => DATA <= x"F0";
when x"6E2" => DATA <= x"A5";
when x"6E3" => DATA <= x"5B";
when x"6E4" => DATA <= x"05";
when x"6E5" => DATA <= x"5D";
when x"6E6" => DATA <= x"D0";
when x"6E7" => DATA <= x"52";
when x"6E8" => DATA <= x"A5";
when x"6E9" => DATA <= x"5A";
when x"6EA" => DATA <= x"C9";
when x"6EB" => DATA <= x"40";
when x"6EC" => DATA <= x"B0";
when x"6ED" => DATA <= x"4C";
when x"6EE" => DATA <= x"4A";
when x"6EF" => DATA <= x"85";
when x"6F0" => DATA <= x"5F";
when x"6F1" => DATA <= x"A9";
when x"6F2" => DATA <= x"2F";
when x"6F3" => DATA <= x"38";
when x"6F4" => DATA <= x"E5";
when x"6F5" => DATA <= x"5C";
when x"6F6" => DATA <= x"C9";
when x"6F7" => DATA <= x"30";
when x"6F8" => DATA <= x"B0";
when x"6F9" => DATA <= x"40";
when x"6FA" => DATA <= x"A2";
when x"6FB" => DATA <= x"FF";
when x"6FC" => DATA <= x"38";
when x"6FD" => DATA <= x"E8";
when x"6FE" => DATA <= x"E9";
when x"6FF" => DATA <= x"03";
when x"700" => DATA <= x"B0";
when x"701" => DATA <= x"FB";
when x"702" => DATA <= x"69";
when x"703" => DATA <= x"03";
when x"704" => DATA <= x"85";
when x"705" => DATA <= x"61";
when x"706" => DATA <= x"8A";
when x"707" => DATA <= x"0A";
when x"708" => DATA <= x"0A";
when x"709" => DATA <= x"0A";
when x"70A" => DATA <= x"0A";
when x"70B" => DATA <= x"0A";
when x"70C" => DATA <= x"05";
when x"70D" => DATA <= x"5F";
when x"70E" => DATA <= x"85";
when x"70F" => DATA <= x"5F";
when x"710" => DATA <= x"A9";
when x"711" => DATA <= x"80";
when x"712" => DATA <= x"69";
when x"713" => DATA <= x"00";
when x"714" => DATA <= x"85";
when x"715" => DATA <= x"60";
when x"716" => DATA <= x"A5";
when x"717" => DATA <= x"5A";
when x"718" => DATA <= x"4A";
when x"719" => DATA <= x"A5";
when x"71A" => DATA <= x"61";
when x"71B" => DATA <= x"2A";
when x"71C" => DATA <= x"A8";
when x"71D" => DATA <= x"B9";
when x"71E" => DATA <= x"CB";
when x"71F" => DATA <= x"F7";
when x"720" => DATA <= x"A0";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"A6";
when x"723" => DATA <= x"5E";
when x"724" => DATA <= x"CA";
when x"725" => DATA <= x"F0";
when x"726" => DATA <= x"0F";
when x"727" => DATA <= x"CA";
when x"728" => DATA <= x"F0";
when x"729" => DATA <= x"07";
when x"72A" => DATA <= x"49";
when x"72B" => DATA <= x"FF";
when x"72C" => DATA <= x"31";
when x"72D" => DATA <= x"5F";
when x"72E" => DATA <= x"91";
when x"72F" => DATA <= x"5F";
when x"730" => DATA <= x"60";
when x"731" => DATA <= x"51";
when x"732" => DATA <= x"5F";
when x"733" => DATA <= x"91";
when x"734" => DATA <= x"5F";
when x"735" => DATA <= x"60";
when x"736" => DATA <= x"11";
when x"737" => DATA <= x"5F";
when x"738" => DATA <= x"91";
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when x"73A" => DATA <= x"60";
when x"73B" => DATA <= x"A5";
when x"73C" => DATA <= x"5B";
when x"73D" => DATA <= x"05";
when x"73E" => DATA <= x"5D";
when x"73F" => DATA <= x"D0";
when x"740" => DATA <= x"F9";
when x"741" => DATA <= x"A5";
when x"742" => DATA <= x"5A";
when x"743" => DATA <= x"30";
when x"744" => DATA <= x"F5";
when x"745" => DATA <= x"4A";
when x"746" => DATA <= x"4A";
when x"747" => DATA <= x"4A";
when x"748" => DATA <= x"85";
when x"749" => DATA <= x"5F";
when x"74A" => DATA <= x"A9";
when x"74B" => DATA <= x"3F";
when x"74C" => DATA <= x"38";
when x"74D" => DATA <= x"E5";
when x"74E" => DATA <= x"5C";
when x"74F" => DATA <= x"C9";
when x"750" => DATA <= x"40";
when x"751" => DATA <= x"90";
when x"752" => DATA <= x"32";
when x"753" => DATA <= x"60";
when x"754" => DATA <= x"A5";
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when x"756" => DATA <= x"05";
when x"757" => DATA <= x"5D";
when x"758" => DATA <= x"D0";
when x"759" => DATA <= x"E0";
when x"75A" => DATA <= x"A5";
when x"75B" => DATA <= x"5A";
when x"75C" => DATA <= x"30";
when x"75D" => DATA <= x"DC";
when x"75E" => DATA <= x"4A";
when x"75F" => DATA <= x"4A";
when x"760" => DATA <= x"4A";
when x"761" => DATA <= x"85";
when x"762" => DATA <= x"5F";
when x"763" => DATA <= x"A9";
when x"764" => DATA <= x"5F";
when x"765" => DATA <= x"38";
when x"766" => DATA <= x"E5";
when x"767" => DATA <= x"5C";
when x"768" => DATA <= x"C9";
when x"769" => DATA <= x"60";
when x"76A" => DATA <= x"90";
when x"76B" => DATA <= x"19";
when x"76C" => DATA <= x"60";
when x"76D" => DATA <= x"A5";
when x"76E" => DATA <= x"5B";
when x"76F" => DATA <= x"05";
when x"770" => DATA <= x"5D";
when x"771" => DATA <= x"D0";
when x"772" => DATA <= x"C7";
when x"773" => DATA <= x"A5";
when x"774" => DATA <= x"5A";
when x"775" => DATA <= x"30";
when x"776" => DATA <= x"C3";
when x"777" => DATA <= x"4A";
when x"778" => DATA <= x"4A";
when x"779" => DATA <= x"4A";
when x"77A" => DATA <= x"85";
when x"77B" => DATA <= x"5F";
when x"77C" => DATA <= x"A9";
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when x"77E" => DATA <= x"38";
when x"77F" => DATA <= x"E5";
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when x"781" => DATA <= x"C9";
when x"782" => DATA <= x"C0";
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when x"784" => DATA <= x"B5";
when x"785" => DATA <= x"A0";
when x"786" => DATA <= x"00";
when x"787" => DATA <= x"84";
when x"788" => DATA <= x"60";
when x"789" => DATA <= x"0A";
when x"78A" => DATA <= x"26";
when x"78B" => DATA <= x"60";
when x"78C" => DATA <= x"0A";
when x"78D" => DATA <= x"26";
when x"78E" => DATA <= x"60";
when x"78F" => DATA <= x"0A";
when x"790" => DATA <= x"26";
when x"791" => DATA <= x"60";
when x"792" => DATA <= x"0A";
when x"793" => DATA <= x"26";
when x"794" => DATA <= x"60";
when x"795" => DATA <= x"65";
when x"796" => DATA <= x"5F";
when x"797" => DATA <= x"85";
when x"798" => DATA <= x"5F";
when x"799" => DATA <= x"A5";
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when x"79B" => DATA <= x"69";
when x"79C" => DATA <= x"80";
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when x"79E" => DATA <= x"60";
when x"79F" => DATA <= x"A5";
when x"7A0" => DATA <= x"5A";
when x"7A1" => DATA <= x"29";
when x"7A2" => DATA <= x"07";
when x"7A3" => DATA <= x"A8";
when x"7A4" => DATA <= x"B9";
when x"7A5" => DATA <= x"C9";
when x"7A6" => DATA <= x"F7";
when x"7A7" => DATA <= x"4C";
when x"7A8" => DATA <= x"20";
when x"7A9" => DATA <= x"F7";
when x"7AA" => DATA <= x"A5";
when x"7AB" => DATA <= x"5B";
when x"7AC" => DATA <= x"05";
when x"7AD" => DATA <= x"5D";
when x"7AE" => DATA <= x"D0";
when x"7AF" => DATA <= x"BC";
when x"7B0" => DATA <= x"A5";
when x"7B1" => DATA <= x"5A";
when x"7B2" => DATA <= x"4A";
when x"7B3" => DATA <= x"4A";
when x"7B4" => DATA <= x"4A";
when x"7B5" => DATA <= x"85";
when x"7B6" => DATA <= x"5F";
when x"7B7" => DATA <= x"A9";
when x"7B8" => DATA <= x"BF";
when x"7B9" => DATA <= x"38";
when x"7BA" => DATA <= x"E5";
when x"7BB" => DATA <= x"5C";
when x"7BC" => DATA <= x"C9";
when x"7BD" => DATA <= x"C0";
when x"7BE" => DATA <= x"B0";
when x"7BF" => DATA <= x"AC";
when x"7C0" => DATA <= x"A0";
when x"7C1" => DATA <= x"00";
when x"7C2" => DATA <= x"84";
when x"7C3" => DATA <= x"60";
when x"7C4" => DATA <= x"0A";
when x"7C5" => DATA <= x"26";
when x"7C6" => DATA <= x"60";
when x"7C7" => DATA <= x"10";
when x"7C8" => DATA <= x"C0";
when x"7C9" => DATA <= x"80";
when x"7CA" => DATA <= x"40";
when x"7CB" => DATA <= x"20";
when x"7CC" => DATA <= x"10";
when x"7CD" => DATA <= x"08";
when x"7CE" => DATA <= x"04";
when x"7CF" => DATA <= x"02";
when x"7D0" => DATA <= x"01";
when x"7D1" => DATA <= x"68";
when x"7D2" => DATA <= x"85";
when x"7D3" => DATA <= x"E8";
when x"7D4" => DATA <= x"68";
when x"7D5" => DATA <= x"85";
when x"7D6" => DATA <= x"E9";
when x"7D7" => DATA <= x"A0";
when x"7D8" => DATA <= x"00";
when x"7D9" => DATA <= x"E6";
when x"7DA" => DATA <= x"E8";
when x"7DB" => DATA <= x"D0";
when x"7DC" => DATA <= x"02";
when x"7DD" => DATA <= x"E6";
when x"7DE" => DATA <= x"E9";
when x"7DF" => DATA <= x"B1";
when x"7E0" => DATA <= x"E8";
when x"7E1" => DATA <= x"30";
when x"7E2" => DATA <= x"06";
when x"7E3" => DATA <= x"20";
when x"7E4" => DATA <= x"F4";
when x"7E5" => DATA <= x"FF";
when x"7E6" => DATA <= x"4C";
when x"7E7" => DATA <= x"D7";
when x"7E8" => DATA <= x"F7";
when x"7E9" => DATA <= x"6C";
when x"7EA" => DATA <= x"E8";
when x"7EB" => DATA <= x"00";
when x"7EC" => DATA <= x"A2";
when x"7ED" => DATA <= x"D4";
when x"7EE" => DATA <= x"20";
when x"7EF" => DATA <= x"F1";
when x"7F0" => DATA <= x"F7";
when x"7F1" => DATA <= x"B5";
when x"7F2" => DATA <= x"01";
when x"7F3" => DATA <= x"20";
when x"7F4" => DATA <= x"02";
when x"7F5" => DATA <= x"F8";
when x"7F6" => DATA <= x"E8";
when x"7F7" => DATA <= x"E8";
when x"7F8" => DATA <= x"B5";
when x"7F9" => DATA <= x"FE";
when x"7FA" => DATA <= x"20";
when x"7FB" => DATA <= x"02";
when x"7FC" => DATA <= x"F8";
when x"7FD" => DATA <= x"A9";
when x"7FE" => DATA <= x"20";
when x"7FF" => DATA <= x"4C";
when x"800" => DATA <= x"F4";
when x"801" => DATA <= x"FF";
when x"802" => DATA <= x"48";
when x"803" => DATA <= x"4A";
when x"804" => DATA <= x"4A";
when x"805" => DATA <= x"4A";
when x"806" => DATA <= x"4A";
when x"807" => DATA <= x"20";
when x"808" => DATA <= x"0B";
when x"809" => DATA <= x"F8";
when x"80A" => DATA <= x"68";
when x"80B" => DATA <= x"29";
when x"80C" => DATA <= x"0F";
when x"80D" => DATA <= x"C9";
when x"80E" => DATA <= x"0A";
when x"80F" => DATA <= x"90";
when x"810" => DATA <= x"02";
when x"811" => DATA <= x"69";
when x"812" => DATA <= x"06";
when x"813" => DATA <= x"69";
when x"814" => DATA <= x"30";
when x"815" => DATA <= x"4C";
when x"816" => DATA <= x"F4";
when x"817" => DATA <= x"FF";
when x"818" => DATA <= x"20";
when x"819" => DATA <= x"76";
when x"81A" => DATA <= x"F8";
when x"81B" => DATA <= x"A2";
when x"81C" => DATA <= x"00";
when x"81D" => DATA <= x"C9";
when x"81E" => DATA <= x"22";
when x"81F" => DATA <= x"F0";
when x"820" => DATA <= x"06";
when x"821" => DATA <= x"E8";
when x"822" => DATA <= x"D0";
when x"823" => DATA <= x"1B";
when x"824" => DATA <= x"4C";
when x"825" => DATA <= x"7D";
when x"826" => DATA <= x"FA";
when x"827" => DATA <= x"C8";
when x"828" => DATA <= x"B9";
when x"829" => DATA <= x"00";
when x"82A" => DATA <= x"01";
when x"82B" => DATA <= x"C9";
when x"82C" => DATA <= x"0D";
when x"82D" => DATA <= x"F0";
when x"82E" => DATA <= x"F5";
when x"82F" => DATA <= x"9D";
when x"830" => DATA <= x"40";
when x"831" => DATA <= x"01";
when x"832" => DATA <= x"E8";
when x"833" => DATA <= x"C9";
when x"834" => DATA <= x"22";
when x"835" => DATA <= x"D0";
when x"836" => DATA <= x"F0";
when x"837" => DATA <= x"C8";
when x"838" => DATA <= x"B9";
when x"839" => DATA <= x"00";
when x"83A" => DATA <= x"01";
when x"83B" => DATA <= x"C9";
when x"83C" => DATA <= x"22";
when x"83D" => DATA <= x"F0";
when x"83E" => DATA <= x"E8";
when x"83F" => DATA <= x"A9";
when x"840" => DATA <= x"0D";
when x"841" => DATA <= x"9D";
when x"842" => DATA <= x"3F";
when x"843" => DATA <= x"01";
when x"844" => DATA <= x"A9";
when x"845" => DATA <= x"40";
when x"846" => DATA <= x"85";
when x"847" => DATA <= x"C9";
when x"848" => DATA <= x"A9";
when x"849" => DATA <= x"01";
when x"84A" => DATA <= x"85";
when x"84B" => DATA <= x"CA";
when x"84C" => DATA <= x"A2";
when x"84D" => DATA <= x"C9";
when x"84E" => DATA <= x"60";
when x"84F" => DATA <= x"A0";
when x"850" => DATA <= x"00";
when x"851" => DATA <= x"B5";
when x"852" => DATA <= x"00";
when x"853" => DATA <= x"99";
when x"854" => DATA <= x"C9";
when x"855" => DATA <= x"00";
when x"856" => DATA <= x"E8";
when x"857" => DATA <= x"C8";
when x"858" => DATA <= x"C0";
when x"859" => DATA <= x"0A";
when x"85A" => DATA <= x"90";
when x"85B" => DATA <= x"F5";
when x"85C" => DATA <= x"A0";
when x"85D" => DATA <= x"FF";
when x"85E" => DATA <= x"A9";
when x"85F" => DATA <= x"0D";
when x"860" => DATA <= x"C8";
when x"861" => DATA <= x"C0";
when x"862" => DATA <= x"0E";
when x"863" => DATA <= x"B0";
when x"864" => DATA <= x"07";
when x"865" => DATA <= x"D1";
when x"866" => DATA <= x"C9";
when x"867" => DATA <= x"D0";
when x"868" => DATA <= x"F7";
when x"869" => DATA <= x"C0";
when x"86A" => DATA <= x"00";
when x"86B" => DATA <= x"60";
when x"86C" => DATA <= x"20";
when x"86D" => DATA <= x"D1";
when x"86E" => DATA <= x"F7";
when x"86F" => DATA <= x"4E";
when x"870" => DATA <= x"41";
when x"871" => DATA <= x"4D";
when x"872" => DATA <= x"45";
when x"873" => DATA <= x"EA";
when x"874" => DATA <= x"00";
when x"875" => DATA <= x"C8";
when x"876" => DATA <= x"B9";
when x"877" => DATA <= x"00";
when x"878" => DATA <= x"01";
when x"879" => DATA <= x"C9";
when x"87A" => DATA <= x"20";
when x"87B" => DATA <= x"F0";
when x"87C" => DATA <= x"F8";
when x"87D" => DATA <= x"60";
when x"87E" => DATA <= x"C9";
when x"87F" => DATA <= x"30";
when x"880" => DATA <= x"90";
when x"881" => DATA <= x"0F";
when x"882" => DATA <= x"C9";
when x"883" => DATA <= x"3A";
when x"884" => DATA <= x"90";
when x"885" => DATA <= x"08";
when x"886" => DATA <= x"E9";
when x"887" => DATA <= x"07";
when x"888" => DATA <= x"90";
when x"889" => DATA <= x"07";
when x"88A" => DATA <= x"C9";
when x"88B" => DATA <= x"40";
when x"88C" => DATA <= x"B0";
when x"88D" => DATA <= x"02";
when x"88E" => DATA <= x"29";
when x"88F" => DATA <= x"0F";
when x"890" => DATA <= x"60";
when x"891" => DATA <= x"38";
when x"892" => DATA <= x"60";
when x"893" => DATA <= x"A9";
when x"894" => DATA <= x"00";
when x"895" => DATA <= x"95";
when x"896" => DATA <= x"00";
when x"897" => DATA <= x"95";
when x"898" => DATA <= x"01";
when x"899" => DATA <= x"95";
when x"89A" => DATA <= x"02";
when x"89B" => DATA <= x"20";
when x"89C" => DATA <= x"76";
when x"89D" => DATA <= x"F8";
when x"89E" => DATA <= x"B9";
when x"89F" => DATA <= x"00";
when x"8A0" => DATA <= x"01";
when x"8A1" => DATA <= x"20";
when x"8A2" => DATA <= x"7E";
when x"8A3" => DATA <= x"F8";
when x"8A4" => DATA <= x"B0";
when x"8A5" => DATA <= x"15";
when x"8A6" => DATA <= x"0A";
when x"8A7" => DATA <= x"0A";
when x"8A8" => DATA <= x"0A";
when x"8A9" => DATA <= x"0A";
when x"8AA" => DATA <= x"94";
when x"8AB" => DATA <= x"02";
when x"8AC" => DATA <= x"A0";
when x"8AD" => DATA <= x"04";
when x"8AE" => DATA <= x"0A";
when x"8AF" => DATA <= x"36";
when x"8B0" => DATA <= x"00";
when x"8B1" => DATA <= x"36";
when x"8B2" => DATA <= x"01";
when x"8B3" => DATA <= x"88";
when x"8B4" => DATA <= x"D0";
when x"8B5" => DATA <= x"F8";
when x"8B6" => DATA <= x"B4";
when x"8B7" => DATA <= x"02";
when x"8B8" => DATA <= x"C8";
when x"8B9" => DATA <= x"D0";
when x"8BA" => DATA <= x"E3";
when x"8BB" => DATA <= x"B5";
when x"8BC" => DATA <= x"02";
when x"8BD" => DATA <= x"60";
when x"8BE" => DATA <= x"43";
when x"8BF" => DATA <= x"41";
when x"8C0" => DATA <= x"54";
when x"8C1" => DATA <= x"FA";
when x"8C2" => DATA <= x"2A";
when x"8C3" => DATA <= x"4C";
when x"8C4" => DATA <= x"4F";
when x"8C5" => DATA <= x"41";
when x"8C6" => DATA <= x"44";
when x"8C7" => DATA <= x"F9";
when x"8C8" => DATA <= x"58";
when x"8C9" => DATA <= x"53";
when x"8CA" => DATA <= x"41";
when x"8CB" => DATA <= x"56";
when x"8CC" => DATA <= x"45";
when x"8CD" => DATA <= x"FA";
when x"8CE" => DATA <= x"BB";
when x"8CF" => DATA <= x"52";
when x"8D0" => DATA <= x"55";
when x"8D1" => DATA <= x"4E";
when x"8D2" => DATA <= x"FA";
when x"8D3" => DATA <= x"20";
when x"8D4" => DATA <= x"4D";
when x"8D5" => DATA <= x"4F";
when x"8D6" => DATA <= x"4E";
when x"8D7" => DATA <= x"FA";
when x"8D8" => DATA <= x"1A";
when x"8D9" => DATA <= x"4E";
when x"8DA" => DATA <= x"4F";
when x"8DB" => DATA <= x"4D";
when x"8DC" => DATA <= x"4F";
when x"8DD" => DATA <= x"4E";
when x"8DE" => DATA <= x"FA";
when x"8DF" => DATA <= x"19";
when x"8E0" => DATA <= x"46";
when x"8E1" => DATA <= x"4C";
when x"8E2" => DATA <= x"4F";
when x"8E3" => DATA <= x"41";
when x"8E4" => DATA <= x"44";
when x"8E5" => DATA <= x"F9";
when x"8E6" => DATA <= x"55";
when x"8E7" => DATA <= x"44";
when x"8E8" => DATA <= x"4F";
when x"8E9" => DATA <= x"53";
when x"8EA" => DATA <= x"CC";
when x"8EB" => DATA <= x"EF";
when x"8EC" => DATA <= x"00";
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when x"8EE" => DATA <= x"26";
when x"8EF" => DATA <= x"A2";
when x"8F0" => DATA <= x"FF";
when x"8F1" => DATA <= x"D8";
when x"8F2" => DATA <= x"A0";
when x"8F3" => DATA <= x"00";
when x"8F4" => DATA <= x"84";
when x"8F5" => DATA <= x"DD";
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when x"8F7" => DATA <= x"76";
when x"8F8" => DATA <= x"F8";
when x"8F9" => DATA <= x"88";
when x"8FA" => DATA <= x"C8";
when x"8FB" => DATA <= x"E8";
when x"8FC" => DATA <= x"BD";
when x"8FD" => DATA <= x"BE";
when x"8FE" => DATA <= x"F8";
when x"8FF" => DATA <= x"30";
when x"900" => DATA <= x"18";
when x"901" => DATA <= x"D9";
when x"902" => DATA <= x"00";
when x"903" => DATA <= x"01";
when x"904" => DATA <= x"F0";
when x"905" => DATA <= x"F4";
when x"906" => DATA <= x"CA";
when x"907" => DATA <= x"E8";
when x"908" => DATA <= x"BD";
when x"909" => DATA <= x"BE";
when x"90A" => DATA <= x"F8";
when x"90B" => DATA <= x"10";
when x"90C" => DATA <= x"FA";
when x"90D" => DATA <= x"E8";
when x"90E" => DATA <= x"B9";
when x"90F" => DATA <= x"00";
when x"910" => DATA <= x"01";
when x"911" => DATA <= x"C9";
when x"912" => DATA <= x"2E";
when x"913" => DATA <= x"D0";
when x"914" => DATA <= x"DD";
when x"915" => DATA <= x"C8";
when x"916" => DATA <= x"CA";
when x"917" => DATA <= x"B0";
when x"918" => DATA <= x"E3";
when x"919" => DATA <= x"85";
when x"91A" => DATA <= x"CA";
when x"91B" => DATA <= x"BD";
when x"91C" => DATA <= x"BF";
when x"91D" => DATA <= x"F8";
when x"91E" => DATA <= x"85";
when x"91F" => DATA <= x"C9";
when x"920" => DATA <= x"18";
when x"921" => DATA <= x"A2";
when x"922" => DATA <= x"00";
when x"923" => DATA <= x"6C";
when x"924" => DATA <= x"C9";
when x"925" => DATA <= x"00";
when x"926" => DATA <= x"20";
when x"927" => DATA <= x"D1";
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when x"929" => DATA <= x"43";
when x"92A" => DATA <= x"4F";
when x"92B" => DATA <= x"4D";
when x"92C" => DATA <= x"3F";
when x"92D" => DATA <= x"EA";
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when x"92F" => DATA <= x"20";
when x"930" => DATA <= x"8E";
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when x"933" => DATA <= x"FA";
when x"934" => DATA <= x"F0";
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when x"936" => DATA <= x"20";
when x"937" => DATA <= x"2B";
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when x"93A" => DATA <= x"00";
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when x"93F" => DATA <= x"CB";
when x"940" => DATA <= x"E6";
when x"941" => DATA <= x"CB";
when x"942" => DATA <= x"D0";
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when x"944" => DATA <= x"E6";
when x"945" => DATA <= x"CC";
when x"946" => DATA <= x"A2";
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when x"948" => DATA <= x"20";
when x"949" => DATA <= x"08";
when x"94A" => DATA <= x"FA";
when x"94B" => DATA <= x"D0";
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when x"94E" => DATA <= x"66";
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when x"950" => DATA <= x"18";
when x"951" => DATA <= x"66";
when x"952" => DATA <= x"DD";
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when x"954" => DATA <= x"60";
when x"955" => DATA <= x"38";
when x"956" => DATA <= x"66";
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when x"959" => DATA <= x"18";
when x"95A" => DATA <= x"F8";
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when x"95C" => DATA <= x"CB";
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when x"95E" => DATA <= x"93";
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when x"960" => DATA <= x"F0";
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when x"967" => DATA <= x"76";
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when x"96A" => DATA <= x"C9";
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when x"96E" => DATA <= x"08";
when x"96F" => DATA <= x"78";
when x"970" => DATA <= x"20";
when x"971" => DATA <= x"4F";
when x"972" => DATA <= x"F8";
when x"973" => DATA <= x"08";
when x"974" => DATA <= x"20";
when x"975" => DATA <= x"3E";
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when x"977" => DATA <= x"28";
when x"978" => DATA <= x"F0";
when x"979" => DATA <= x"B5";
when x"97A" => DATA <= x"A9";
when x"97B" => DATA <= x"00";
when x"97C" => DATA <= x"85";
when x"97D" => DATA <= x"D0";
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when x"97F" => DATA <= x"D1";
when x"980" => DATA <= x"20";
when x"981" => DATA <= x"A2";
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when x"983" => DATA <= x"90";
when x"984" => DATA <= x"C9";
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when x"986" => DATA <= x"D0";
when x"987" => DATA <= x"E6";
when x"988" => DATA <= x"CC";
when x"989" => DATA <= x"D0";
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when x"9A2" => DATA <= x"A9";
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when x"9B1" => DATA <= x"20";
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when x"9B4" => DATA <= x"28";
when x"9B5" => DATA <= x"F0";
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when x"9BD" => DATA <= x"D0";
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when x"9C5" => DATA <= x"D0";
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when x"9CF" => DATA <= x"D5";
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when x"9D3" => DATA <= x"A9";
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when x"9D6" => DATA <= x"40";
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when x"9D8" => DATA <= x"20";
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when x"9DB" => DATA <= x"D0";
when x"9DC" => DATA <= x"C5";
when x"9DD" => DATA <= x"CA";
when x"9DE" => DATA <= x"D0";
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when x"9E0" => DATA <= x"20";
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when x"9E3" => DATA <= x"24";
when x"9E4" => DATA <= x"DB";
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when x"9E6" => DATA <= x"0B";
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when x"A00" => DATA <= x"53";
when x"A01" => DATA <= x"55";
when x"A02" => DATA <= x"4D";
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when x"A04" => DATA <= x"00";
when x"A05" => DATA <= x"26";
when x"A06" => DATA <= x"DB";
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when x"A0C" => DATA <= x"F6";
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when x"A0E" => DATA <= x"B5";
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when x"A11" => DATA <= x"02";
when x"A12" => DATA <= x"D0";
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when x"A14" => DATA <= x"B5";
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when x"A18" => DATA <= x"60";
when x"A19" => DATA <= x"CA";
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when x"A1C" => DATA <= x"FA";
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when x"A1E" => DATA <= x"EA";
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when x"A20" => DATA <= x"20";
when x"A21" => DATA <= x"58";
when x"A22" => DATA <= x"F9";
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when x"A24" => DATA <= x"DD";
when x"A25" => DATA <= x"70";
when x"A26" => DATA <= x"4C";
when x"A27" => DATA <= x"6C";
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when x"A29" => DATA <= x"00";
when x"A2A" => DATA <= x"08";
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when x"A2C" => DATA <= x"76";
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when x"A2E" => DATA <= x"20";
when x"A2F" => DATA <= x"3E";
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when x"A31" => DATA <= x"20";
when x"A32" => DATA <= x"8E";
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when x"A34" => DATA <= x"70";
when x"A35" => DATA <= x"02";
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when x"A37" => DATA <= x"60";
when x"A38" => DATA <= x"F0";
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when x"A3A" => DATA <= x"A0";
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when x"A3C" => DATA <= x"20";
when x"A3D" => DATA <= x"99";
when x"A3E" => DATA <= x"F9";
when x"A3F" => DATA <= x"20";
when x"A40" => DATA <= x"EC";
when x"A41" => DATA <= x"F7";
when x"A42" => DATA <= x"D0";
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when x"A44" => DATA <= x"20";
when x"A45" => DATA <= x"C9";
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when x"A47" => DATA <= x"20";
when x"A48" => DATA <= x"E2";
when x"A49" => DATA <= x"FB";
when x"A4A" => DATA <= x"20";
when x"A4B" => DATA <= x"92";
when x"A4C" => DATA <= x"F9";
when x"A4D" => DATA <= x"20";
when x"A4E" => DATA <= x"EC";
when x"A4F" => DATA <= x"F7";
when x"A50" => DATA <= x"26";
when x"A51" => DATA <= x"DB";
when x"A52" => DATA <= x"10";
when x"A53" => DATA <= x"09";
when x"A54" => DATA <= x"E8";
when x"A55" => DATA <= x"20";
when x"A56" => DATA <= x"F1";
when x"A57" => DATA <= x"F7";
when x"A58" => DATA <= x"B5";
when x"A59" => DATA <= x"FD";
when x"A5A" => DATA <= x"20";
when x"A5B" => DATA <= x"02";
when x"A5C" => DATA <= x"F8";
when x"A5D" => DATA <= x"20";
when x"A5E" => DATA <= x"ED";
when x"A5F" => DATA <= x"FF";
when x"A60" => DATA <= x"D0";
when x"A61" => DATA <= x"CF";
when x"A62" => DATA <= x"4C";
when x"A63" => DATA <= x"ED";
when x"A64" => DATA <= x"FF";
when x"A65" => DATA <= x"20";
when x"A66" => DATA <= x"93";
when x"A67" => DATA <= x"F8";
when x"A68" => DATA <= x"F0";
when x"A69" => DATA <= x"13";
when x"A6A" => DATA <= x"60";
when x"A6B" => DATA <= x"A2";
when x"A6C" => DATA <= x"CB";
when x"A6D" => DATA <= x"20";
when x"A6E" => DATA <= x"65";
when x"A6F" => DATA <= x"FA";
when x"A70" => DATA <= x"20";
when x"A71" => DATA <= x"76";
when x"A72" => DATA <= x"FA";
when x"A73" => DATA <= x"6C";
when x"A74" => DATA <= x"CB";
when x"A75" => DATA <= x"00";
when x"A76" => DATA <= x"20";
when x"A77" => DATA <= x"76";
when x"A78" => DATA <= x"F8";
when x"A79" => DATA <= x"C9";
when x"A7A" => DATA <= x"0D";
when x"A7B" => DATA <= x"F0";
when x"A7C" => DATA <= x"A2";
when x"A7D" => DATA <= x"20";
when x"A7E" => DATA <= x"D1";
when x"A7F" => DATA <= x"F7";
when x"A80" => DATA <= x"53";
when x"A81" => DATA <= x"59";
when x"A82" => DATA <= x"4E";
when x"A83" => DATA <= x"3F";
when x"A84" => DATA <= x"EA";
when x"A85" => DATA <= x"00";
when x"A86" => DATA <= x"38";
when x"A87" => DATA <= x"A5";
when x"A88" => DATA <= x"D1";
when x"A89" => DATA <= x"E5";
when x"A8A" => DATA <= x"CF";
when x"A8B" => DATA <= x"48";
when x"A8C" => DATA <= x"A5";
when x"A8D" => DATA <= x"D2";
when x"A8E" => DATA <= x"E5";
when x"A8F" => DATA <= x"D0";
when x"A90" => DATA <= x"A8";
when x"A91" => DATA <= x"68";
when x"A92" => DATA <= x"18";
when x"A93" => DATA <= x"65";
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when x"A95" => DATA <= x"85";
when x"A96" => DATA <= x"CD";
when x"A97" => DATA <= x"98";
when x"A98" => DATA <= x"65";
when x"A99" => DATA <= x"CC";
when x"A9A" => DATA <= x"85";
when x"A9B" => DATA <= x"CE";
when x"A9C" => DATA <= x"A0";
when x"A9D" => DATA <= x"04";
when x"A9E" => DATA <= x"B9";
when x"A9F" => DATA <= x"CA";
when x"AA0" => DATA <= x"00";
when x"AA1" => DATA <= x"20";
when x"AA2" => DATA <= x"D1";
when x"AA3" => DATA <= x"FF";
when x"AA4" => DATA <= x"88";
when x"AA5" => DATA <= x"D0";
when x"AA6" => DATA <= x"F7";
when x"AA7" => DATA <= x"B1";
when x"AA8" => DATA <= x"CF";
when x"AA9" => DATA <= x"20";
when x"AAA" => DATA <= x"D1";
when x"AAB" => DATA <= x"FF";
when x"AAC" => DATA <= x"E6";
when x"AAD" => DATA <= x"CF";
when x"AAE" => DATA <= x"D0";
when x"AAF" => DATA <= x"02";
when x"AB0" => DATA <= x"E6";
when x"AB1" => DATA <= x"D0";
when x"AB2" => DATA <= x"A2";
when x"AB3" => DATA <= x"CB";
when x"AB4" => DATA <= x"20";
when x"AB5" => DATA <= x"08";
when x"AB6" => DATA <= x"FA";
when x"AB7" => DATA <= x"D0";
when x"AB8" => DATA <= x"EE";
when x"AB9" => DATA <= x"28";
when x"ABA" => DATA <= x"60";
when x"ABB" => DATA <= x"20";
when x"ABC" => DATA <= x"18";
when x"ABD" => DATA <= x"F8";
when x"ABE" => DATA <= x"A2";
when x"ABF" => DATA <= x"CB";
when x"AC0" => DATA <= x"20";
when x"AC1" => DATA <= x"65";
when x"AC2" => DATA <= x"FA";
when x"AC3" => DATA <= x"A2";
when x"AC4" => DATA <= x"D1";
when x"AC5" => DATA <= x"20";
when x"AC6" => DATA <= x"65";
when x"AC7" => DATA <= x"FA";
when x"AC8" => DATA <= x"A2";
when x"AC9" => DATA <= x"CD";
when x"ACA" => DATA <= x"20";
when x"ACB" => DATA <= x"93";
when x"ACC" => DATA <= x"F8";
when x"ACD" => DATA <= x"08";
when x"ACE" => DATA <= x"A5";
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when x"AD0" => DATA <= x"A6";
when x"AD1" => DATA <= x"CC";
when x"AD2" => DATA <= x"28";
when x"AD3" => DATA <= x"D0";
when x"AD4" => DATA <= x"04";
when x"AD5" => DATA <= x"85";
when x"AD6" => DATA <= x"CD";
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when x"AD8" => DATA <= x"CE";
when x"AD9" => DATA <= x"85";
when x"ADA" => DATA <= x"CF";
when x"ADB" => DATA <= x"86";
when x"ADC" => DATA <= x"D0";
when x"ADD" => DATA <= x"20";
when x"ADE" => DATA <= x"76";
when x"ADF" => DATA <= x"FA";
when x"AE0" => DATA <= x"A2";
when x"AE1" => DATA <= x"C9";
when x"AE2" => DATA <= x"6C";
when x"AE3" => DATA <= x"0E";
when x"AE4" => DATA <= x"02";
when x"AE5" => DATA <= x"08";
when x"AE6" => DATA <= x"78";
when x"AE7" => DATA <= x"20";
when x"AE8" => DATA <= x"4F";
when x"AE9" => DATA <= x"F8";
when x"AEA" => DATA <= x"08";
when x"AEB" => DATA <= x"A9";
when x"AEC" => DATA <= x"06";
when x"AED" => DATA <= x"20";
when x"AEE" => DATA <= x"40";
when x"AEF" => DATA <= x"FC";
when x"AF0" => DATA <= x"A2";
when x"AF1" => DATA <= x"07";
when x"AF2" => DATA <= x"20";
when x"AF3" => DATA <= x"7A";
when x"AF4" => DATA <= x"FB";
when x"AF5" => DATA <= x"28";
when x"AF6" => DATA <= x"F0";
when x"AF7" => DATA <= x"8E";
when x"AF8" => DATA <= x"A2";
when x"AF9" => DATA <= x"04";
when x"AFA" => DATA <= x"B5";
when x"AFB" => DATA <= x"CE";
when x"AFC" => DATA <= x"95";
when x"AFD" => DATA <= x"D2";
when x"AFE" => DATA <= x"CA";
when x"AFF" => DATA <= x"D0";
when x"B00" => DATA <= x"F9";
when x"B01" => DATA <= x"86";
when x"B02" => DATA <= x"D0";
when x"B03" => DATA <= x"86";
when x"B04" => DATA <= x"D1";
when x"B05" => DATA <= x"A5";
when x"B06" => DATA <= x"D5";
when x"B07" => DATA <= x"D0";
when x"B08" => DATA <= x"02";
when x"B09" => DATA <= x"C6";
when x"B0A" => DATA <= x"D6";
when x"B0B" => DATA <= x"C6";
when x"B0C" => DATA <= x"D5";
when x"B0D" => DATA <= x"18";
when x"B0E" => DATA <= x"66";
when x"B0F" => DATA <= x"D2";
when x"B10" => DATA <= x"38";
when x"B11" => DATA <= x"A2";
when x"B12" => DATA <= x"FF";
when x"B13" => DATA <= x"A5";
when x"B14" => DATA <= x"D5";
when x"B15" => DATA <= x"E5";
when x"B16" => DATA <= x"D3";
when x"B17" => DATA <= x"85";
when x"B18" => DATA <= x"CF";
when x"B19" => DATA <= x"A5";
when x"B1A" => DATA <= x"D6";
when x"B1B" => DATA <= x"E5";
when x"B1C" => DATA <= x"D4";
when x"B1D" => DATA <= x"08";
when x"B1E" => DATA <= x"66";
when x"B1F" => DATA <= x"D2";
when x"B20" => DATA <= x"28";
when x"B21" => DATA <= x"90";
when x"B22" => DATA <= x"06";
when x"B23" => DATA <= x"18";
when x"B24" => DATA <= x"F0";
when x"B25" => DATA <= x"03";
when x"B26" => DATA <= x"86";
when x"B27" => DATA <= x"CF";
when x"B28" => DATA <= x"38";
when x"B29" => DATA <= x"66";
when x"B2A" => DATA <= x"D2";
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when x"B2C" => DATA <= x"20";
when x"B2D" => DATA <= x"3B";
when x"B2E" => DATA <= x"FB";
when x"B2F" => DATA <= x"E6";
when x"B30" => DATA <= x"D0";
when x"B31" => DATA <= x"E6";
when x"B32" => DATA <= x"D4";
when x"B33" => DATA <= x"E6";
when x"B34" => DATA <= x"CC";
when x"B35" => DATA <= x"26";
when x"B36" => DATA <= x"D2";
when x"B37" => DATA <= x"B0";
when x"B38" => DATA <= x"D5";
when x"B39" => DATA <= x"28";
when x"B3A" => DATA <= x"60";
when x"B3B" => DATA <= x"A2";
when x"B3C" => DATA <= x"07";
when x"B3D" => DATA <= x"20";
when x"B3E" => DATA <= x"7A";
when x"B3F" => DATA <= x"FB";
when x"B40" => DATA <= x"86";
when x"B41" => DATA <= x"DC";
when x"B42" => DATA <= x"A0";
when x"B43" => DATA <= x"04";
when x"B44" => DATA <= x"A9";
when x"B45" => DATA <= x"2A";
when x"B46" => DATA <= x"20";
when x"B47" => DATA <= x"D1";
when x"B48" => DATA <= x"FF";
when x"B49" => DATA <= x"88";
when x"B4A" => DATA <= x"D0";
when x"B4B" => DATA <= x"F8";
when x"B4C" => DATA <= x"B1";
when x"B4D" => DATA <= x"C9";
when x"B4E" => DATA <= x"20";
when x"B4F" => DATA <= x"D1";
when x"B50" => DATA <= x"FF";
when x"B51" => DATA <= x"C8";
when x"B52" => DATA <= x"C9";
when x"B53" => DATA <= x"0D";
when x"B54" => DATA <= x"D0";
when x"B55" => DATA <= x"F6";
when x"B56" => DATA <= x"A0";
when x"B57" => DATA <= x"08";
when x"B58" => DATA <= x"B9";
when x"B59" => DATA <= x"CA";
when x"B5A" => DATA <= x"00";
when x"B5B" => DATA <= x"20";
when x"B5C" => DATA <= x"D1";
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when x"B5E" => DATA <= x"88";
when x"B5F" => DATA <= x"D0";
when x"B60" => DATA <= x"F7";
when x"B61" => DATA <= x"20";
when x"B62" => DATA <= x"81";
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when x"B65" => DATA <= x"D2";
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when x"B67" => DATA <= x"0B";
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when x"B69" => DATA <= x"C8";
when x"B6A" => DATA <= x"B1";
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when x"B6C" => DATA <= x"20";
when x"B6D" => DATA <= x"D1";
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when x"B6F" => DATA <= x"C4";
when x"B70" => DATA <= x"CF";
when x"B71" => DATA <= x"D0";
when x"B72" => DATA <= x"F6";
when x"B73" => DATA <= x"A5";
when x"B74" => DATA <= x"DC";
when x"B75" => DATA <= x"20";
when x"B76" => DATA <= x"D1";
when x"B77" => DATA <= x"FF";
when x"B78" => DATA <= x"A2";
when x"B79" => DATA <= x"04";
when x"B7A" => DATA <= x"8E";
when x"B7B" => DATA <= x"02";
when x"B7C" => DATA <= x"B0";
when x"B7D" => DATA <= x"A2";
when x"B7E" => DATA <= x"78";
when x"B7F" => DATA <= x"D0";
when x"B80" => DATA <= x"02";
when x"B81" => DATA <= x"A2";
when x"B82" => DATA <= x"1E";
when x"B83" => DATA <= x"20";
when x"B84" => DATA <= x"66";
when x"B85" => DATA <= x"FE";
when x"B86" => DATA <= x"CA";
when x"B87" => DATA <= x"D0";
when x"B88" => DATA <= x"FA";
when x"B89" => DATA <= x"60";
when x"B8A" => DATA <= x"A2";
when x"B8B" => DATA <= x"06";
when x"B8C" => DATA <= x"D0";
when x"B8D" => DATA <= x"F5";
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when x"B8F" => DATA <= x"01";
when x"B90" => DATA <= x"B0";
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when x"B92" => DATA <= x"FB";
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when x"B94" => DATA <= x"F9";
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when x"B97" => DATA <= x"85";
when x"B98" => DATA <= x"C3";
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when x"B9A" => DATA <= x"10";
when x"B9B" => DATA <= x"85";
when x"B9C" => DATA <= x"C2";
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when x"B9F" => DATA <= x"B0";
when x"BA0" => DATA <= x"10";
when x"BA1" => DATA <= x"0F";
when x"BA2" => DATA <= x"50";
when x"BA3" => DATA <= x"0D";
when x"BA4" => DATA <= x"20";
when x"BA5" => DATA <= x"BD";
when x"BA6" => DATA <= x"FC";
when x"BA7" => DATA <= x"B0";
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when x"BA9" => DATA <= x"C6";
when x"BAA" => DATA <= x"C3";
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when x"BAC" => DATA <= x"F0";
when x"BAD" => DATA <= x"C6";
when x"BAE" => DATA <= x"C2";
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when x"BB1" => DATA <= x"70";
when x"BB2" => DATA <= x"01";
when x"BB3" => DATA <= x"60";
when x"BB4" => DATA <= x"A0";
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when x"BB6" => DATA <= x"08";
when x"BB7" => DATA <= x"20";
when x"BB8" => DATA <= x"E4";
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when x"BBA" => DATA <= x"28";
when x"BBB" => DATA <= x"A0";
when x"BBC" => DATA <= x"04";
when x"BBD" => DATA <= x"A9";
when x"BBE" => DATA <= x"2A";
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when x"BC0" => DATA <= x"D3";
when x"BC1" => DATA <= x"00";
when x"BC2" => DATA <= x"D0";
when x"BC3" => DATA <= x"03";
when x"BC4" => DATA <= x"88";
when x"BC5" => DATA <= x"D0";
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when x"BC7" => DATA <= x"60";
when x"BC8" => DATA <= x"C8";
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when x"BCA" => DATA <= x"D4";
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when x"BCC" => DATA <= x"99";
when x"BCD" => DATA <= x"ED";
when x"BCE" => DATA <= x"00";
when x"BCF" => DATA <= x"C9";
when x"BD0" => DATA <= x"0D";
when x"BD1" => DATA <= x"D0";
when x"BD2" => DATA <= x"F5";
when x"BD3" => DATA <= x"A0";
when x"BD4" => DATA <= x"FF";
when x"BD5" => DATA <= x"C8";
when x"BD6" => DATA <= x"B1";
when x"BD7" => DATA <= x"C9";
when x"BD8" => DATA <= x"D9";
when x"BD9" => DATA <= x"ED";
when x"BDA" => DATA <= x"00";
when x"BDB" => DATA <= x"D0";
when x"BDC" => DATA <= x"EA";
when x"BDD" => DATA <= x"C9";
when x"BDE" => DATA <= x"0D";
when x"BDF" => DATA <= x"D0";
when x"BE0" => DATA <= x"F4";
when x"BE1" => DATA <= x"60";
when x"BE2" => DATA <= x"A0";
when x"BE3" => DATA <= x"08";
when x"BE4" => DATA <= x"20";
when x"BE5" => DATA <= x"D4";
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when x"BE7" => DATA <= x"99";
when x"BE8" => DATA <= x"D3";
when x"BE9" => DATA <= x"00";
when x"BEA" => DATA <= x"88";
when x"BEB" => DATA <= x"D0";
when x"BEC" => DATA <= x"F7";
when x"BED" => DATA <= x"60";
when x"BEE" => DATA <= x"86";
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when x"BF0" => DATA <= x"84";
when x"BF1" => DATA <= x"C3";
when x"BF2" => DATA <= x"08";
when x"BF3" => DATA <= x"78";
when x"BF4" => DATA <= x"A9";
when x"BF5" => DATA <= x"78";
when x"BF6" => DATA <= x"85";
when x"BF7" => DATA <= x"C0";
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when x"BF9" => DATA <= x"BD";
when x"BFA" => DATA <= x"FC";
when x"BFB" => DATA <= x"90";
when x"BFC" => DATA <= x"F7";
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when x"BFE" => DATA <= x"C0";
when x"BFF" => DATA <= x"10";
when x"C00" => DATA <= x"F7";
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when x"C02" => DATA <= x"53";
when x"C03" => DATA <= x"85";
when x"C04" => DATA <= x"C4";
when x"C05" => DATA <= x"A2";
when x"C06" => DATA <= x"00";
when x"C07" => DATA <= x"AC";
when x"C08" => DATA <= x"02";
when x"C09" => DATA <= x"B0";
when x"C0A" => DATA <= x"20";
when x"C0B" => DATA <= x"CD";
when x"C0C" => DATA <= x"FC";
when x"C0D" => DATA <= x"F0";
when x"C0E" => DATA <= x"00";
when x"C0F" => DATA <= x"F0";
when x"C10" => DATA <= x"01";
when x"C11" => DATA <= x"E8";
when x"C12" => DATA <= x"C6";
when x"C13" => DATA <= x"C4";
when x"C14" => DATA <= x"D0";
when x"C15" => DATA <= x"F4";
when x"C16" => DATA <= x"E0";
when x"C17" => DATA <= x"0C";
when x"C18" => DATA <= x"66";
when x"C19" => DATA <= x"C0";
when x"C1A" => DATA <= x"90";
when x"C1B" => DATA <= x"E5";
when x"C1C" => DATA <= x"A5";
when x"C1D" => DATA <= x"C0";
when x"C1E" => DATA <= x"28";
when x"C1F" => DATA <= x"A4";
when x"C20" => DATA <= x"C3";
when x"C21" => DATA <= x"A6";
when x"C22" => DATA <= x"EC";
when x"C23" => DATA <= x"48";
when x"C24" => DATA <= x"18";
when x"C25" => DATA <= x"65";
when x"C26" => DATA <= x"DC";
when x"C27" => DATA <= x"85";
when x"C28" => DATA <= x"DC";
when x"C29" => DATA <= x"68";
when x"C2A" => DATA <= x"60";
when x"C2B" => DATA <= x"A5";
when x"C2C" => DATA <= x"CD";
when x"C2D" => DATA <= x"30";
when x"C2E" => DATA <= x"08";
when x"C2F" => DATA <= x"A5";
when x"C30" => DATA <= x"D4";
when x"C31" => DATA <= x"85";
when x"C32" => DATA <= x"CB";
when x"C33" => DATA <= x"A5";
when x"C34" => DATA <= x"D5";
when x"C35" => DATA <= x"85";
when x"C36" => DATA <= x"CC";
when x"C37" => DATA <= x"60";
when x"C38" => DATA <= x"B0";
when x"C39" => DATA <= x"04";
when x"C3A" => DATA <= x"A9";
when x"C3B" => DATA <= x"06";
when x"C3C" => DATA <= x"D0";
when x"C3D" => DATA <= x"02";
when x"C3E" => DATA <= x"A9";
when x"C3F" => DATA <= x"04";
when x"C40" => DATA <= x"A2";
when x"C41" => DATA <= x"07";
when x"C42" => DATA <= x"8E";
when x"C43" => DATA <= x"02";
when x"C44" => DATA <= x"B0";
when x"C45" => DATA <= x"24";
when x"C46" => DATA <= x"EA";
when x"C47" => DATA <= x"D0";
when x"C48" => DATA <= x"2D";
when x"C49" => DATA <= x"C9";
when x"C4A" => DATA <= x"05";
when x"C4B" => DATA <= x"F0";
when x"C4C" => DATA <= x"16";
when x"C4D" => DATA <= x"B0";
when x"C4E" => DATA <= x"09";
when x"C4F" => DATA <= x"20";
when x"C50" => DATA <= x"D1";
when x"C51" => DATA <= x"F7";
when x"C52" => DATA <= x"50";
when x"C53" => DATA <= x"4C";
when x"C54" => DATA <= x"41";
when x"C55" => DATA <= x"59";
when x"C56" => DATA <= x"D0";
when x"C57" => DATA <= x"15";
when x"C58" => DATA <= x"20";
when x"C59" => DATA <= x"D1";
when x"C5A" => DATA <= x"F7";
when x"C5B" => DATA <= x"52";
when x"C5C" => DATA <= x"45";
when x"C5D" => DATA <= x"43";
when x"C5E" => DATA <= x"4F";
when x"C5F" => DATA <= x"52";
when x"C60" => DATA <= x"44";
when x"C61" => DATA <= x"D0";
when x"C62" => DATA <= x"0A";
when x"C63" => DATA <= x"20";
when x"C64" => DATA <= x"D1";
when x"C65" => DATA <= x"F7";
when x"C66" => DATA <= x"52";
when x"C67" => DATA <= x"45";
when x"C68" => DATA <= x"57";
when x"C69" => DATA <= x"49";
when x"C6A" => DATA <= x"4E";
when x"C6B" => DATA <= x"44";
when x"C6C" => DATA <= x"EA";
when x"C6D" => DATA <= x"20";
when x"C6E" => DATA <= x"D1";
when x"C6F" => DATA <= x"F7";
when x"C70" => DATA <= x"20";
when x"C71" => DATA <= x"54";
when x"C72" => DATA <= x"41";
when x"C73" => DATA <= x"50";
when x"C74" => DATA <= x"45";
when x"C75" => DATA <= x"EA";
when x"C76" => DATA <= x"20";
when x"C77" => DATA <= x"E3";
when x"C78" => DATA <= x"FF";
when x"C79" => DATA <= x"4C";
when x"C7A" => DATA <= x"ED";
when x"C7B" => DATA <= x"FF";
when x"C7C" => DATA <= x"86";
when x"C7D" => DATA <= x"EC";
when x"C7E" => DATA <= x"84";
when x"C7F" => DATA <= x"C3";
when x"C80" => DATA <= x"08";
when x"C81" => DATA <= x"78";
when x"C82" => DATA <= x"48";
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when x"C84" => DATA <= x"23";
when x"C85" => DATA <= x"FC";
when x"C86" => DATA <= x"85";
when x"C87" => DATA <= x"C0";
when x"C88" => DATA <= x"20";
when x"C89" => DATA <= x"D8";
when x"C8A" => DATA <= x"FC";
when x"C8B" => DATA <= x"A9";
when x"C8C" => DATA <= x"0A";
when x"C8D" => DATA <= x"85";
when x"C8E" => DATA <= x"C1";
when x"C8F" => DATA <= x"18";
when x"C90" => DATA <= x"90";
when x"C91" => DATA <= x"0A";
when x"C92" => DATA <= x"A2";
when x"C93" => DATA <= x"07";
when x"C94" => DATA <= x"8E";
when x"C95" => DATA <= x"02";
when x"C96" => DATA <= x"B0";
when x"C97" => DATA <= x"20";
when x"C98" => DATA <= x"DA";
when x"C99" => DATA <= x"FC";
when x"C9A" => DATA <= x"30";
when x"C9B" => DATA <= x"13";
when x"C9C" => DATA <= x"A0";
when x"C9D" => DATA <= x"04";
when x"C9E" => DATA <= x"A9";
when x"C9F" => DATA <= x"04";
when x"CA0" => DATA <= x"8D";
when x"CA1" => DATA <= x"02";
when x"CA2" => DATA <= x"B0";
when x"CA3" => DATA <= x"20";
when x"CA4" => DATA <= x"D8";
when x"CA5" => DATA <= x"FC";
when x"CA6" => DATA <= x"EE";
when x"CA7" => DATA <= x"02";
when x"CA8" => DATA <= x"B0";
when x"CA9" => DATA <= x"20";
when x"CAA" => DATA <= x"D8";
when x"CAB" => DATA <= x"FC";
when x"CAC" => DATA <= x"88";
when x"CAD" => DATA <= x"D0";
when x"CAE" => DATA <= x"EF";
when x"CAF" => DATA <= x"38";
when x"CB0" => DATA <= x"66";
when x"CB1" => DATA <= x"C0";
when x"CB2" => DATA <= x"C6";
when x"CB3" => DATA <= x"C1";
when x"CB4" => DATA <= x"D0";
when x"CB5" => DATA <= x"DA";
when x"CB6" => DATA <= x"A4";
when x"CB7" => DATA <= x"C3";
when x"CB8" => DATA <= x"A6";
when x"CB9" => DATA <= x"EC";
when x"CBA" => DATA <= x"68";
when x"CBB" => DATA <= x"28";
when x"CBC" => DATA <= x"60";
when x"CBD" => DATA <= x"A2";
when x"CBE" => DATA <= x"00";
when x"CBF" => DATA <= x"AC";
when x"CC0" => DATA <= x"02";
when x"CC1" => DATA <= x"B0";
when x"CC2" => DATA <= x"E8";
when x"CC3" => DATA <= x"F0";
when x"CC4" => DATA <= x"07";
when x"CC5" => DATA <= x"20";
when x"CC6" => DATA <= x"CD";
when x"CC7" => DATA <= x"FC";
when x"CC8" => DATA <= x"F0";
when x"CC9" => DATA <= x"F8";
when x"CCA" => DATA <= x"E0";
when x"CCB" => DATA <= x"08";
when x"CCC" => DATA <= x"60";
when x"CCD" => DATA <= x"84";
when x"CCE" => DATA <= x"C5";
when x"CCF" => DATA <= x"AD";
when x"CD0" => DATA <= x"02";
when x"CD1" => DATA <= x"B0";
when x"CD2" => DATA <= x"A8";
when x"CD3" => DATA <= x"45";
when x"CD4" => DATA <= x"C5";
when x"CD5" => DATA <= x"29";
when x"CD6" => DATA <= x"20";
when x"CD7" => DATA <= x"60";
when x"CD8" => DATA <= x"A2";
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when x"CDA" => DATA <= x"A9";
when x"CDB" => DATA <= x"10";
when x"CDC" => DATA <= x"2C";
when x"CDD" => DATA <= x"02";
when x"CDE" => DATA <= x"B0";
when x"CDF" => DATA <= x"F0";
when x"CE0" => DATA <= x"FB";
when x"CE1" => DATA <= x"2C";
when x"CE2" => DATA <= x"02";
when x"CE3" => DATA <= x"B0";
when x"CE4" => DATA <= x"D0";
when x"CE5" => DATA <= x"FB";
when x"CE6" => DATA <= x"CA";
when x"CE7" => DATA <= x"10";
when x"CE8" => DATA <= x"F3";
when x"CE9" => DATA <= x"60";
when x"CEA" => DATA <= x"C9";
when x"CEB" => DATA <= x"06";
when x"CEC" => DATA <= x"F0";
when x"CED" => DATA <= x"1D";
when x"CEE" => DATA <= x"C9";
when x"CEF" => DATA <= x"15";
when x"CF0" => DATA <= x"F0";
when x"CF1" => DATA <= x"1F";
when x"CF2" => DATA <= x"A4";
when x"CF3" => DATA <= x"E0";
when x"CF4" => DATA <= x"30";
when x"CF5" => DATA <= x"23";
when x"CF6" => DATA <= x"C9";
when x"CF7" => DATA <= x"1B";
when x"CF8" => DATA <= x"F0";
when x"CF9" => DATA <= x"11";
when x"CFA" => DATA <= x"C9";
when x"CFB" => DATA <= x"07";
when x"CFC" => DATA <= x"F0";
when x"CFD" => DATA <= x"1C";
when x"CFE" => DATA <= x"20";
when x"CFF" => DATA <= x"44";
when x"D00" => DATA <= x"FD";
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when x"D02" => DATA <= x"0A";
when x"D03" => DATA <= x"20";
when x"D04" => DATA <= x"C5";
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when x"D06" => DATA <= x"D0";
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when x"D08" => DATA <= x"4C";
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when x"D0B" => DATA <= x"18";
when x"D0C" => DATA <= x"A2";
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when x"D0E" => DATA <= x"8E";
when x"D0F" => DATA <= x"00";
when x"D10" => DATA <= x"B0";
when x"D11" => DATA <= x"A2";
when x"D12" => DATA <= x"02";
when x"D13" => DATA <= x"08";
when x"D14" => DATA <= x"16";
when x"D15" => DATA <= x"DE";
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when x"D17" => DATA <= x"76";
when x"D18" => DATA <= x"DE";
when x"D19" => DATA <= x"60";
when x"D1A" => DATA <= x"A9";
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when x"D1C" => DATA <= x"A8";
when x"D1D" => DATA <= x"8D";
when x"D1E" => DATA <= x"03";
when x"D1F" => DATA <= x"B0";
when x"D20" => DATA <= x"CA";
when x"D21" => DATA <= x"D0";
when x"D22" => DATA <= x"FD";
when x"D23" => DATA <= x"49";
when x"D24" => DATA <= x"01";
when x"D25" => DATA <= x"C8";
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when x"D27" => DATA <= x"F5";
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when x"D29" => DATA <= x"C9";
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when x"D2B" => DATA <= x"90";
when x"D2C" => DATA <= x"17";
when x"D2D" => DATA <= x"69";
when x"D2E" => DATA <= x"1F";
when x"D2F" => DATA <= x"30";
when x"D30" => DATA <= x"02";
when x"D31" => DATA <= x"49";
when x"D32" => DATA <= x"60";
when x"D33" => DATA <= x"20";
when x"D34" => DATA <= x"6B";
when x"D35" => DATA <= x"FE";
when x"D36" => DATA <= x"91";
when x"D37" => DATA <= x"DE";
when x"D38" => DATA <= x"C8";
when x"D39" => DATA <= x"C0";
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when x"D3B" => DATA <= x"90";
when x"D3C" => DATA <= x"05";
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when x"D3E" => DATA <= x"EC";
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when x"D40" => DATA <= x"A0";
when x"D41" => DATA <= x"00";
when x"D42" => DATA <= x"84";
when x"D43" => DATA <= x"E0";
when x"D44" => DATA <= x"48";
when x"D45" => DATA <= x"20";
when x"D46" => DATA <= x"6B";
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when x"D48" => DATA <= x"B1";
when x"D49" => DATA <= x"DE";
when x"D4A" => DATA <= x"45";
when x"D4B" => DATA <= x"E1";
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when x"D4D" => DATA <= x"DE";
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when x"D4F" => DATA <= x"60";
when x"D50" => DATA <= x"20";
when x"D51" => DATA <= x"35";
when x"D52" => DATA <= x"FE";
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when x"D54" => DATA <= x"20";
when x"D55" => DATA <= x"20";
when x"D56" => DATA <= x"6B";
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when x"D58" => DATA <= x"91";
when x"D59" => DATA <= x"DE";
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when x"D5D" => DATA <= x"35";
when x"D5E" => DATA <= x"FE";
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when x"D60" => DATA <= x"42";
when x"D61" => DATA <= x"FD";
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when x"D63" => DATA <= x"EC";
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when x"D65" => DATA <= x"A4";
when x"D66" => DATA <= x"E0";
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when x"D6B" => DATA <= x"84";
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when x"D73" => DATA <= x"20";
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when x"D77" => DATA <= x"99";
when x"D78" => DATA <= x"00";
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when x"D7C" => DATA <= x"F7";
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when x"D7E" => DATA <= x"80";
when x"D7F" => DATA <= x"A0";
when x"D80" => DATA <= x"00";
when x"D81" => DATA <= x"85";
when x"D82" => DATA <= x"DF";
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when x"D84" => DATA <= x"DE";
when x"D85" => DATA <= x"F0";
when x"D86" => DATA <= x"BB";
when x"D87" => DATA <= x"20";
when x"D88" => DATA <= x"3A";
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when x"D8A" => DATA <= x"4C";
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when x"D8C" => DATA <= x"FD";
when x"D8D" => DATA <= x"18";
when x"D8E" => DATA <= x"A9";
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when x"D90" => DATA <= x"85";
when x"D91" => DATA <= x"E6";
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when x"D94" => DATA <= x"20";
when x"D95" => DATA <= x"13";
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when x"D98" => DATA <= x"44";
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when x"D9C" => DATA <= x"49";
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when x"DA8" => DATA <= x"20";
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when x"DAA" => DATA <= x"FC";
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when x"DAC" => DATA <= x"9A";
when x"DAD" => DATA <= x"FE";
when x"DAE" => DATA <= x"A4";
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when x"DB0" => DATA <= x"20";
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when x"DB2" => DATA <= x"FE";
when x"DB3" => DATA <= x"B1";
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when x"DB5" => DATA <= x"45";
when x"DB6" => DATA <= x"E1";
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when x"DB9" => DATA <= x"49";
when x"DBA" => DATA <= x"60";
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when x"DC0" => DATA <= x"A9";
when x"DC1" => DATA <= x"5F";
when x"DC2" => DATA <= x"49";
when x"DC3" => DATA <= x"20";
when x"DC4" => DATA <= x"D0";
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when x"DC6" => DATA <= x"45";
when x"DC7" => DATA <= x"E7";
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when x"DC9" => DATA <= x"01";
when x"DCA" => DATA <= x"B0";
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when x"DCC" => DATA <= x"02";
when x"DCD" => DATA <= x"49";
when x"DCE" => DATA <= x"60";
when x"DCF" => DATA <= x"4C";
when x"DD0" => DATA <= x"DF";
when x"DD1" => DATA <= x"FD";
when x"DD2" => DATA <= x"69";
when x"DD3" => DATA <= x"39";
when x"DD4" => DATA <= x"90";
when x"DD5" => DATA <= x"F2";
when x"DD6" => DATA <= x"49";
when x"DD7" => DATA <= x"10";
when x"DD8" => DATA <= x"2C";
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when x"DDA" => DATA <= x"B0";
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when x"DDC" => DATA <= x"02";
when x"DDD" => DATA <= x"49";
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when x"DDF" => DATA <= x"18";
when x"DE0" => DATA <= x"69";
when x"DE1" => DATA <= x"20";
when x"DE2" => DATA <= x"2C";
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when x"DE4" => DATA <= x"B0";
when x"DE5" => DATA <= x"70";
when x"DE6" => DATA <= x"02";
when x"DE7" => DATA <= x"29";
when x"DE8" => DATA <= x"1F";
when x"DE9" => DATA <= x"4C";
when x"DEA" => DATA <= x"60";
when x"DEB" => DATA <= x"FE";
when x"DEC" => DATA <= x"A5";
when x"DED" => DATA <= x"DE";
when x"DEE" => DATA <= x"A4";
when x"DEF" => DATA <= x"DF";
when x"DF0" => DATA <= x"C0";
when x"DF1" => DATA <= x"81";
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when x"DF3" => DATA <= x"38";
when x"DF4" => DATA <= x"C9";
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when x"DF7" => DATA <= x"34";
when x"DF8" => DATA <= x"A4";
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when x"DFA" => DATA <= x"30";
when x"DFB" => DATA <= x"0C";
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when x"DFD" => DATA <= x"D0";
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when x"DFF" => DATA <= x"20";
when x"E00" => DATA <= x"71";
when x"E01" => DATA <= x"FE";
when x"E02" => DATA <= x"B0";
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when x"E04" => DATA <= x"A0";
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when x"E06" => DATA <= x"84";
when x"E07" => DATA <= x"E6";
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when x"E0A" => DATA <= x"20";
when x"E0B" => DATA <= x"66";
when x"E0C" => DATA <= x"FE";
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when x"E0F" => DATA <= x"80";
when x"E10" => DATA <= x"99";
when x"E11" => DATA <= x"E0";
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when x"E13" => DATA <= x"C8";
when x"E14" => DATA <= x"D0";
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when x"E16" => DATA <= x"20";
when x"E17" => DATA <= x"6B";
when x"E18" => DATA <= x"FE";
when x"E19" => DATA <= x"B9";
when x"E1A" => DATA <= x"00";
when x"E1B" => DATA <= x"81";
when x"E1C" => DATA <= x"99";
when x"E1D" => DATA <= x"E0";
when x"E1E" => DATA <= x"80";
when x"E1F" => DATA <= x"C8";
when x"E20" => DATA <= x"D0";
when x"E21" => DATA <= x"F7";
when x"E22" => DATA <= x"A0";
when x"E23" => DATA <= x"1F";
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when x"E25" => DATA <= x"20";
when x"E26" => DATA <= x"91";
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when x"E29" => DATA <= x"10";
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when x"E2C" => DATA <= x"69";
when x"E2D" => DATA <= x"20";
when x"E2E" => DATA <= x"85";
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when x"E30" => DATA <= x"D0";
when x"E31" => DATA <= x"02";
when x"E32" => DATA <= x"E6";
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when x"E34" => DATA <= x"60";
when x"E35" => DATA <= x"88";
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when x"E37" => DATA <= x"19";
when x"E38" => DATA <= x"A0";
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when x"E3A" => DATA <= x"A5";
when x"E3B" => DATA <= x"DE";
when x"E3C" => DATA <= x"D0";
when x"E3D" => DATA <= x"0B";
when x"E3E" => DATA <= x"A6";
when x"E3F" => DATA <= x"DF";
when x"E40" => DATA <= x"E0";
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when x"E42" => DATA <= x"D0";
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when x"E44" => DATA <= x"68";
when x"E45" => DATA <= x"68";
when x"E46" => DATA <= x"4C";
when x"E47" => DATA <= x"65";
when x"E48" => DATA <= x"FD";
when x"E49" => DATA <= x"E9";
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when x"E4B" => DATA <= x"85";
when x"E4C" => DATA <= x"DE";
when x"E4D" => DATA <= x"B0";
when x"E4E" => DATA <= x"02";
when x"E4F" => DATA <= x"C6";
when x"E50" => DATA <= x"DF";
when x"E51" => DATA <= x"60";
when x"E52" => DATA <= x"20";
when x"E53" => DATA <= x"FB";
when x"E54" => DATA <= x"FE";
when x"E55" => DATA <= x"08";
when x"E56" => DATA <= x"48";
when x"E57" => DATA <= x"D8";
when x"E58" => DATA <= x"84";
when x"E59" => DATA <= x"E5";
when x"E5A" => DATA <= x"86";
when x"E5B" => DATA <= x"E4";
when x"E5C" => DATA <= x"20";
when x"E5D" => DATA <= x"EA";
when x"E5E" => DATA <= x"FC";
when x"E5F" => DATA <= x"68";
when x"E60" => DATA <= x"A6";
when x"E61" => DATA <= x"E4";
when x"E62" => DATA <= x"A4";
when x"E63" => DATA <= x"E5";
when x"E64" => DATA <= x"28";
when x"E65" => DATA <= x"60";
when x"E66" => DATA <= x"2C";
when x"E67" => DATA <= x"02";
when x"E68" => DATA <= x"B0";
when x"E69" => DATA <= x"10";
when x"E6A" => DATA <= x"FB";
when x"E6B" => DATA <= x"2C";
when x"E6C" => DATA <= x"02";
when x"E6D" => DATA <= x"B0";
when x"E6E" => DATA <= x"30";
when x"E6F" => DATA <= x"FB";
when x"E70" => DATA <= x"60";
when x"E71" => DATA <= x"A0";
when x"E72" => DATA <= x"3B";
when x"E73" => DATA <= x"18";
when x"E74" => DATA <= x"A9";
when x"E75" => DATA <= x"20";
when x"E76" => DATA <= x"A2";
when x"E77" => DATA <= x"0A";
when x"E78" => DATA <= x"2C";
when x"E79" => DATA <= x"01";
when x"E7A" => DATA <= x"B0";
when x"E7B" => DATA <= x"F0";
when x"E7C" => DATA <= x"08";
when x"E7D" => DATA <= x"EE";
when x"E7E" => DATA <= x"00";
when x"E7F" => DATA <= x"B0";
when x"E80" => DATA <= x"88";
when x"E81" => DATA <= x"CA";
when x"E82" => DATA <= x"D0";
when x"E83" => DATA <= x"F4";
when x"E84" => DATA <= x"4A";
when x"E85" => DATA <= x"08";
when x"E86" => DATA <= x"48";
when x"E87" => DATA <= x"AD";
when x"E88" => DATA <= x"00";
when x"E89" => DATA <= x"B0";
when x"E8A" => DATA <= x"29";
when x"E8B" => DATA <= x"F0";
when x"E8C" => DATA <= x"8D";
when x"E8D" => DATA <= x"00";
when x"E8E" => DATA <= x"B0";
when x"E8F" => DATA <= x"68";
when x"E90" => DATA <= x"28";
when x"E91" => DATA <= x"D0";
when x"E92" => DATA <= x"E3";
when x"E93" => DATA <= x"60";
when x"E94" => DATA <= x"08";
when x"E95" => DATA <= x"D8";
when x"E96" => DATA <= x"86";
when x"E97" => DATA <= x"E4";
when x"E98" => DATA <= x"84";
when x"E99" => DATA <= x"E5";
when x"E9A" => DATA <= x"2C";
when x"E9B" => DATA <= x"02";
when x"E9C" => DATA <= x"B0";
when x"E9D" => DATA <= x"50";
when x"E9E" => DATA <= x"05";
when x"E9F" => DATA <= x"20";
when x"EA0" => DATA <= x"71";
when x"EA1" => DATA <= x"FE";
when x"EA2" => DATA <= x"90";
when x"EA3" => DATA <= x"F6";
when x"EA4" => DATA <= x"20";
when x"EA5" => DATA <= x"8A";
when x"EA6" => DATA <= x"FB";
when x"EA7" => DATA <= x"20";
when x"EA8" => DATA <= x"71";
when x"EA9" => DATA <= x"FE";
when x"EAA" => DATA <= x"B0";
when x"EAB" => DATA <= x"FB";
when x"EAC" => DATA <= x"20";
when x"EAD" => DATA <= x"71";
when x"EAE" => DATA <= x"FE";
when x"EAF" => DATA <= x"B0";
when x"EB0" => DATA <= x"F6";
when x"EB1" => DATA <= x"98";
when x"EB2" => DATA <= x"A2";
when x"EB3" => DATA <= x"17";
when x"EB4" => DATA <= x"20";
when x"EB5" => DATA <= x"C5";
when x"EB6" => DATA <= x"FE";
when x"EB7" => DATA <= x"BD";
when x"EB8" => DATA <= x"E3";
when x"EB9" => DATA <= x"FE";
when x"EBA" => DATA <= x"85";
when x"EBB" => DATA <= x"E2";
when x"EBC" => DATA <= x"A9";
when x"EBD" => DATA <= x"FD";
when x"EBE" => DATA <= x"85";
when x"EBF" => DATA <= x"E3";
when x"EC0" => DATA <= x"98";
when x"EC1" => DATA <= x"6C";
when x"EC2" => DATA <= x"E2";
when x"EC3" => DATA <= x"00";
when x"EC4" => DATA <= x"CA";
when x"EC5" => DATA <= x"DD";
when x"EC6" => DATA <= x"CB";
when x"EC7" => DATA <= x"FE";
when x"EC8" => DATA <= x"90";
when x"EC9" => DATA <= x"FA";
when x"ECA" => DATA <= x"60";
when x"ECB" => DATA <= x"00";
when x"ECC" => DATA <= x"08";
when x"ECD" => DATA <= x"09";
when x"ECE" => DATA <= x"0A";
when x"ECF" => DATA <= x"0B";
when x"ED0" => DATA <= x"0C";
when x"ED1" => DATA <= x"0D";
when x"ED2" => DATA <= x"0E";
when x"ED3" => DATA <= x"0F";
when x"ED4" => DATA <= x"1E";
when x"ED5" => DATA <= x"7F";
when x"ED6" => DATA <= x"00";
when x"ED7" => DATA <= x"01";
when x"ED8" => DATA <= x"05";
when x"ED9" => DATA <= x"06";
when x"EDA" => DATA <= x"08";
when x"EDB" => DATA <= x"0E";
when x"EDC" => DATA <= x"0F";
when x"EDD" => DATA <= x"10";
when x"EDE" => DATA <= x"11";
when x"EDF" => DATA <= x"1C";
when x"EE0" => DATA <= x"20";
when x"EE1" => DATA <= x"21";
when x"EE2" => DATA <= x"3B";
when x"EE3" => DATA <= x"44";
when x"EE4" => DATA <= x"5C";
when x"EE5" => DATA <= x"38";
when x"EE6" => DATA <= x"62";
when x"EE7" => DATA <= x"87";
when x"EE8" => DATA <= x"69";
when x"EE9" => DATA <= x"40";
when x"EEA" => DATA <= x"8D";
when x"EEB" => DATA <= x"92";
when x"EEC" => DATA <= x"7D";
when x"EED" => DATA <= x"50";
when x"EEE" => DATA <= x"DF";
when x"EEF" => DATA <= x"D2";
when x"EF0" => DATA <= x"9A";
when x"EF1" => DATA <= x"A2";
when x"EF2" => DATA <= x"E2";
when x"EF3" => DATA <= x"AE";
when x"EF4" => DATA <= x"C0";
when x"EF5" => DATA <= x"DF";
when x"EF6" => DATA <= x"D8";
when x"EF7" => DATA <= x"D6";
when x"EF8" => DATA <= x"C8";
when x"EF9" => DATA <= x"C6";
when x"EFA" => DATA <= x"C2";
when x"EFB" => DATA <= x"48";
when x"EFC" => DATA <= x"C9";
when x"EFD" => DATA <= x"02";
when x"EFE" => DATA <= x"F0";
when x"EFF" => DATA <= x"27";
when x"F00" => DATA <= x"C9";
when x"F01" => DATA <= x"03";
when x"F02" => DATA <= x"F0";
when x"F03" => DATA <= x"34";
when x"F04" => DATA <= x"C5";
when x"F05" => DATA <= x"FE";
when x"F06" => DATA <= x"F0";
when x"F07" => DATA <= x"2E";
when x"F08" => DATA <= x"AD";
when x"F09" => DATA <= x"0C";
when x"F0A" => DATA <= x"B8";
when x"F0B" => DATA <= x"29";
when x"F0C" => DATA <= x"0E";
when x"F0D" => DATA <= x"F0";
when x"F0E" => DATA <= x"27";
when x"F0F" => DATA <= x"68";
when x"F10" => DATA <= x"2C";
when x"F11" => DATA <= x"01";
when x"F12" => DATA <= x"B8";
when x"F13" => DATA <= x"30";
when x"F14" => DATA <= x"FB";
when x"F15" => DATA <= x"8D";
when x"F16" => DATA <= x"01";
when x"F17" => DATA <= x"B8";
when x"F18" => DATA <= x"48";
when x"F19" => DATA <= x"AD";
when x"F1A" => DATA <= x"0C";
when x"F1B" => DATA <= x"B8";
when x"F1C" => DATA <= x"29";
when x"F1D" => DATA <= x"F0";
when x"F1E" => DATA <= x"09";
when x"F1F" => DATA <= x"0C";
when x"F20" => DATA <= x"8D";
when x"F21" => DATA <= x"0C";
when x"F22" => DATA <= x"B8";
when x"F23" => DATA <= x"09";
when x"F24" => DATA <= x"02";
when x"F25" => DATA <= x"D0";
when x"F26" => DATA <= x"0C";
when x"F27" => DATA <= x"A9";
when x"F28" => DATA <= x"7F";
when x"F29" => DATA <= x"8D";
when x"F2A" => DATA <= x"03";
when x"F2B" => DATA <= x"B8";
when x"F2C" => DATA <= x"AD";
when x"F2D" => DATA <= x"0C";
when x"F2E" => DATA <= x"B8";
when x"F2F" => DATA <= x"29";
when x"F30" => DATA <= x"F0";
when x"F31" => DATA <= x"09";
when x"F32" => DATA <= x"0E";
when x"F33" => DATA <= x"8D";
when x"F34" => DATA <= x"0C";
when x"F35" => DATA <= x"B8";
when x"F36" => DATA <= x"68";
when x"F37" => DATA <= x"60";
when x"F38" => DATA <= x"AD";
when x"F39" => DATA <= x"0C";
when x"F3A" => DATA <= x"B8";
when x"F3B" => DATA <= x"29";
when x"F3C" => DATA <= x"F0";
when x"F3D" => DATA <= x"B0";
when x"F3E" => DATA <= x"F4";
when x"F3F" => DATA <= x"A2";
when x"F40" => DATA <= x"17";
when x"F41" => DATA <= x"BD";
when x"F42" => DATA <= x"9A";
when x"F43" => DATA <= x"FF";
when x"F44" => DATA <= x"9D";
when x"F45" => DATA <= x"04";
when x"F46" => DATA <= x"02";
when x"F47" => DATA <= x"CA";
when x"F48" => DATA <= x"10";
when x"F49" => DATA <= x"F7";
when x"F4A" => DATA <= x"9A";
when x"F4B" => DATA <= x"8A";
when x"F4C" => DATA <= x"E8";
when x"F4D" => DATA <= x"86";
when x"F4E" => DATA <= x"EA";
when x"F4F" => DATA <= x"86";
when x"F50" => DATA <= x"E1";
when x"F51" => DATA <= x"86";
when x"F52" => DATA <= x"E7";
when x"F53" => DATA <= x"A2";
when x"F54" => DATA <= x"33";
when x"F55" => DATA <= x"9D";
when x"F56" => DATA <= x"EB";
when x"F57" => DATA <= x"02";
when x"F58" => DATA <= x"CA";
when x"F59" => DATA <= x"10";
when x"F5A" => DATA <= x"FA";
when x"F5B" => DATA <= x"A9";
when x"F5C" => DATA <= x"0A";
when x"F5D" => DATA <= x"85";
when x"F5E" => DATA <= x"FE";
when x"F5F" => DATA <= x"A9";
when x"F60" => DATA <= x"8A";
when x"F61" => DATA <= x"8D";
when x"F62" => DATA <= x"03";
when x"F63" => DATA <= x"B0";
when x"F64" => DATA <= x"A9";
when x"F65" => DATA <= x"07";
when x"F66" => DATA <= x"8D";
when x"F67" => DATA <= x"02";
when x"F68" => DATA <= x"B0";
when x"F69" => DATA <= x"20";
when x"F6A" => DATA <= x"D1";
when x"F6B" => DATA <= x"F7";
when x"F6C" => DATA <= x"06";
when x"F6D" => DATA <= x"0C";
when x"F6E" => DATA <= x"0F";
when x"F6F" => DATA <= x"41";
when x"F70" => DATA <= x"43";
when x"F71" => DATA <= x"4F";
when x"F72" => DATA <= x"52";
when x"F73" => DATA <= x"4E";
when x"F74" => DATA <= x"20";
when x"F75" => DATA <= x"41";
when x"F76" => DATA <= x"54";
when x"F77" => DATA <= x"4F";
when x"F78" => DATA <= x"4D";
when x"F79" => DATA <= x"0A";
when x"F7A" => DATA <= x"0A";
when x"F7B" => DATA <= x"0D";
when x"F7C" => DATA <= x"A9";
when x"F7D" => DATA <= x"82";
when x"F7E" => DATA <= x"85";
when x"F7F" => DATA <= x"12";
when x"F80" => DATA <= x"58";
when x"F81" => DATA <= x"A9";
when x"F82" => DATA <= x"55";
when x"F83" => DATA <= x"8D";
when x"F84" => DATA <= x"01";
when x"F85" => DATA <= x"29";
when x"F86" => DATA <= x"CD";
when x"F87" => DATA <= x"01";
when x"F88" => DATA <= x"29";
when x"F89" => DATA <= x"D0";
when x"F8A" => DATA <= x"0C";
when x"F8B" => DATA <= x"0A";
when x"F8C" => DATA <= x"8D";
when x"F8D" => DATA <= x"01";
when x"F8E" => DATA <= x"29";
when x"F8F" => DATA <= x"CD";
when x"F90" => DATA <= x"01";
when x"F91" => DATA <= x"29";
when x"F92" => DATA <= x"D0";
when x"F93" => DATA <= x"03";
when x"F94" => DATA <= x"4C";
when x"F95" => DATA <= x"00";
when x"F96" => DATA <= x"E0";
when x"F97" => DATA <= x"4C";
when x"F98" => DATA <= x"B6";
when x"F99" => DATA <= x"C2";
when x"F9A" => DATA <= x"00";
when x"F9B" => DATA <= x"A0";
when x"F9C" => DATA <= x"EF";
when x"F9D" => DATA <= x"F8";
when x"F9E" => DATA <= x"52";
when x"F9F" => DATA <= x"FE";
when x"FA0" => DATA <= x"94";
when x"FA1" => DATA <= x"FE";
when x"FA2" => DATA <= x"6E";
when x"FA3" => DATA <= x"F9";
when x"FA4" => DATA <= x"E5";
when x"FA5" => DATA <= x"FA";
when x"FA6" => DATA <= x"AC";
when x"FA7" => DATA <= x"C2";
when x"FA8" => DATA <= x"AC";
when x"FA9" => DATA <= x"C2";
when x"FAA" => DATA <= x"EE";
when x"FAB" => DATA <= x"FB";
when x"FAC" => DATA <= x"7C";
when x"FAD" => DATA <= x"FC";
when x"FAE" => DATA <= x"38";
when x"FAF" => DATA <= x"FC";
when x"FB0" => DATA <= x"78";
when x"FB1" => DATA <= x"C2";
when x"FB2" => DATA <= x"85";
when x"FB3" => DATA <= x"FF";
when x"FB4" => DATA <= x"68";
when x"FB5" => DATA <= x"48";
when x"FB6" => DATA <= x"29";
when x"FB7" => DATA <= x"10";
when x"FB8" => DATA <= x"D0";
when x"FB9" => DATA <= x"06";
when x"FBA" => DATA <= x"A5";
when x"FBB" => DATA <= x"FF";
when x"FBC" => DATA <= x"48";
when x"FBD" => DATA <= x"6C";
when x"FBE" => DATA <= x"04";
when x"FBF" => DATA <= x"02";
when x"FC0" => DATA <= x"A5";
when x"FC1" => DATA <= x"FF";
when x"FC2" => DATA <= x"28";
when x"FC3" => DATA <= x"08";
when x"FC4" => DATA <= x"6C";
when x"FC5" => DATA <= x"02";
when x"FC6" => DATA <= x"02";
when x"FC7" => DATA <= x"48";
when x"FC8" => DATA <= x"6C";
when x"FC9" => DATA <= x"00";
when x"FCA" => DATA <= x"02";
when x"FCB" => DATA <= x"6C";
when x"FCC" => DATA <= x"1A";
when x"FCD" => DATA <= x"02";
when x"FCE" => DATA <= x"6C";
when x"FCF" => DATA <= x"18";
when x"FD0" => DATA <= x"02";
when x"FD1" => DATA <= x"6C";
when x"FD2" => DATA <= x"16";
when x"FD3" => DATA <= x"02";
when x"FD4" => DATA <= x"6C";
when x"FD5" => DATA <= x"14";
when x"FD6" => DATA <= x"02";
when x"FD7" => DATA <= x"6C";
when x"FD8" => DATA <= x"12";
when x"FD9" => DATA <= x"02";
when x"FDA" => DATA <= x"6C";
when x"FDB" => DATA <= x"10";
when x"FDC" => DATA <= x"02";
when x"FDD" => DATA <= x"6C";
when x"FDE" => DATA <= x"0E";
when x"FDF" => DATA <= x"02";
when x"FE0" => DATA <= x"6C";
when x"FE1" => DATA <= x"0C";
when x"FE2" => DATA <= x"02";
when x"FE3" => DATA <= x"6C";
when x"FE4" => DATA <= x"0A";
when x"FE5" => DATA <= x"02";
when x"FE6" => DATA <= x"20";
when x"FE7" => DATA <= x"E3";
when x"FE8" => DATA <= x"FF";
when x"FE9" => DATA <= x"C9";
when x"FEA" => DATA <= x"0D";
when x"FEB" => DATA <= x"D0";
when x"FEC" => DATA <= x"07";
when x"FED" => DATA <= x"A9";
when x"FEE" => DATA <= x"0A";
when x"FEF" => DATA <= x"20";
when x"FF0" => DATA <= x"F4";
when x"FF1" => DATA <= x"FF";
when x"FF2" => DATA <= x"A9";
when x"FF3" => DATA <= x"0D";
when x"FF4" => DATA <= x"6C";
when x"FF5" => DATA <= x"08";
when x"FF6" => DATA <= x"02";
when x"FF7" => DATA <= x"6C";
when x"FF8" => DATA <= x"06";
when x"FF9" => DATA <= x"02";
when x"FFA" => DATA <= x"C7";
when x"FFB" => DATA <= x"FF";
when x"FFC" => DATA <= x"3F";
when x"FFD" => DATA <= x"FF";
when x"FFE" => DATA <= x"B2";
when x"FFF" => DATA <= x"FF";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_ulogic; -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxdb2 : std_ulogic; -- delayed rx data
rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
v.rxdb2 := r.rxdb;
if r.tcnt /= "11" then
if (r.rxdb2 and not r.rxdb) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb2 and r.fedge and not r.rxdb) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb2) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(6 downto 0) := r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf := r.rxf(6 downto 0) & ui.rxd;
if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
r.rxf(7)) = r.rxf(6 downto 0))
then v.rxdb := r.rxf(7); end if;
irxd := r.rxdb;
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb2 and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.ovf := '0'; v.break := '0'; v.thempty := '1';
v.tsempty := '1'; v.dready := '0'; v.fedge := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.scaler := "111111111111111011"; v.brate := (others => '1');
v.rxen := '0'; v.tcnt := "00";
v.txclk := (others => '0'); v.rxclk := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler <= r.brate;
uo.rtsn <= '0';
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dcom_uart
-- File: dcom_uart.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Asynchronous UART with baud-rate detection.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.uart.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity dcom_uart is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ui : in uart_in_type;
uo : out uart_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
uarti : in dcom_uart_in_type;
uarto : out dcom_uart_out_type
);
end;
architecture rtl of dcom_uart is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBUART, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type rxfsmtype is (idle, startbit, data, stopbit);
type txfsmtype is (idle, data, stopbit);
type uartregs is record
rxen : std_ulogic; -- receiver enabled
dready : std_ulogic; -- data ready
rsempty : std_ulogic; -- receiver shift register empty (internal)
tsempty : std_ulogic; -- transmitter shift register empty
thempty : std_ulogic; -- transmitter hold register empty
break : std_ulogic; -- break detected
ovf : std_ulogic; -- receiver overflow
frame : std_ulogic; -- framing error
rhold : std_logic_vector(7 downto 0);
rshift : std_logic_vector(7 downto 0);
tshift : std_logic_vector(10 downto 0);
thold : std_logic_vector(7 downto 0);
txstate : txfsmtype;
txclk : std_logic_vector(2 downto 0); -- tx clock divider
txtick : std_ulogic; -- tx clock (internal)
rxstate : rxfsmtype;
rxclk : std_logic_vector(2 downto 0); -- rx clock divider
rxdb : std_ulogic; -- rx data filtering buffer
rxtick : std_ulogic; -- rx clock (internal)
tick : std_ulogic; -- rx clock (internal)
scaler : std_logic_vector(17 downto 0);
brate : std_logic_vector(17 downto 0);
tcnt : std_logic_vector(1 downto 0); -- autobaud counter
rxdb2 : std_ulogic; -- delayed rx data
rxf : std_logic_vector(7 downto 0); -- rx data filtering buffer
fedge : std_ulogic; -- rx falling edge
end record;
signal r, rin : uartregs;
begin
uartop : process(rst, r, apbi, uarti, ui )
variable rdata : std_logic_vector(31 downto 0);
variable scaler : std_logic_vector(17 downto 0);
variable rxclk, txclk : std_logic_vector(2 downto 0);
variable irxd : std_ulogic;
variable v : uartregs;
begin
v := r;
v.txtick := '0'; v.rxtick := '0'; v.tick := '0'; rdata := (others => '0');
-- scaler
if r.tcnt = "11" then scaler := r.scaler - 1;
else scaler := r.scaler + 1; end if;
v.rxdb2 := r.rxdb;
if r.tcnt /= "11" then
if (r.rxdb2 and not r.rxdb) = '1' then v.fedge := '1'; end if;
if (r.fedge) = '1' then
v.scaler := scaler;
if (v.scaler(17) and not r.scaler(16)) = '1' then
v.scaler := "111111111111111011";
v.fedge := '0'; v.tcnt := "00";
end if;
end if;
if (r.rxdb2 and r.fedge and not r.rxdb) = '1' then
if (r.brate(17 downto 4)> r.scaler(17 downto 4)) then
v.brate := r.scaler; v.tcnt := "00";
end if;
v.scaler := "111111111111111011";
if (r.brate(17 downto 4) = r.scaler(17 downto 4)) then
v.tcnt := r.tcnt + 1;
if r.tcnt = "10" then
v.brate := "0000" & r.scaler(17 downto 4);
v.scaler := v.brate; v.rxen := '1';
end if;
end if;
end if;
else
if (r.break and r.rxdb2) = '1' then
v.scaler := "111111111111111011";
v.brate := (others => '1'); v.tcnt := "00";
v.break := '0'; v.rxen := '0';
end if;
end if;
if r.rxen = '1' then
v.scaler := scaler;
v.tick := scaler(15) and not r.scaler(15);
if v.tick = '1' then v.scaler := r.brate; end if;
end if;
-- read/write registers
if uarti.read = '1' then v.dready := '0'; end if;
case apbi.paddr(3 downto 2) is
when "01" =>
rdata(6 downto 0) := r.frame & '0' & r.ovf &
r.break & r.thempty & r.tsempty & r.dready;
when "10" =>
rdata(1 downto 0) := (r.tcnt(1) or r.tcnt(0)) & r.rxen;
when others =>
rdata(17 downto 0) := r.brate;
end case;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
v.frame := apbi.pwdata(6);
v.ovf := apbi.pwdata(4);
v.break := apbi.pwdata(3);
when "10" =>
v.tcnt := apbi.pwdata(1) & apbi.pwdata(1);
v.rxen := apbi.pwdata(0);
when "11" =>
v.brate := apbi.pwdata(17 downto 0);
v.scaler := apbi.pwdata(17 downto 0);
when others =>
end case;
end if;
-- tx clock
txclk := r.txclk + 1;
if r.tick = '1' then
v.txclk := txclk; v.txtick := r.txclk(2) and not txclk(2);
end if;
-- rx clock
rxclk := r.rxclk + 1;
if r.tick = '1' then
v.rxclk := rxclk; v.rxtick := r.rxclk(2) and not rxclk(2);
end if;
-- filter rx data
v.rxf := r.rxf(6 downto 0) & ui.rxd;
if ((r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) & r.rxf(7) &
r.rxf(7)) = r.rxf(6 downto 0))
then v.rxdb := r.rxf(7); end if;
irxd := r.rxdb;
-- transmitter operation
case r.txstate is
when idle => -- idle state
if (r.txtick = '1') then v.tsempty := '1'; end if;
if (r.rxen and (not r.thempty) and r.txtick) = '1' then
v.tshift := "10" & r.thold & '0'; v.txstate := data;
v.thempty := '1';
v.tsempty := '0'; v.txclk := "00" & r.tick; v.txtick := '0';
end if;
when data => -- transmitt data frame
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1);
if r.tshift(10 downto 1) = "1111111110" then
v.tshift(0) := '1'; v.txstate := stopbit;
end if;
end if;
when stopbit => -- transmitt stop bit
if r.txtick = '1' then
v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle;
end if;
end case;
-- writing of tx data register must be done after tx fsm to get correct
-- operation of thempty flag
if uarti.write = '1' then
v.thold := uarti.data(7 downto 0); v.thempty := '0';
end if;
-- receiver operation
case r.rxstate is
when idle => -- wait for start bit
if ((not r.rsempty) and not r.dready) = '1' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
if (r.rxen and r.rxdb2 and (not irxd)) = '1' then
v.rxstate := startbit; v.rshift := (others => '1'); v.rxclk := "100";
if v.rsempty = '0' then v.ovf := '1'; end if;
v.rsempty := '0'; v.rxtick := '0';
end if;
when startbit => -- check validity of start bit
if r.rxtick = '1' then
if irxd = '0' then
v.rshift := irxd & r.rshift(7 downto 1); v.rxstate := data;
else
v.rxstate := idle;
end if;
end if;
when data => -- receive data frame
if r.rxtick = '1' then
v.rshift := irxd & r.rshift(7 downto 1);
if r.rshift(0) = '0' then
v.rxstate := stopbit;
end if;
end if;
when stopbit => -- receive stop bit
if r.rxtick = '1' then
if irxd = '1' then
v.rsempty := '0';
if v.dready = '0' then
v.rhold := r.rshift; v.rsempty := '1'; v.dready := '1';
end if;
else
if r.rshift = "00000000" then
v.break := '1'; -- break
else
v.frame := '1'; -- framing error
end if;
v.rsempty := '1';
end if;
v.rxstate := idle;
end if;
end case;
-- reset operation
if rst = '0' then
v.frame := '0'; v.rsempty := '1';
v.ovf := '0'; v.break := '0'; v.thempty := '1';
v.tsempty := '1'; v.dready := '0'; v.fedge := '0';
v.txstate := idle; v.rxstate := idle; v.tshift(0) := '1';
v.scaler := "111111111111111011"; v.brate := (others => '1');
v.rxen := '0'; v.tcnt := "00";
v.txclk := (others => '0'); v.rxclk := (others => '0');
end if;
-- update registers
rin <= v;
-- drive outputs
uo.txd <= r.tshift(0);
uo.scaler <= r.brate;
uo.rtsn <= '0';
uarto.dready <= r.dready;
uarto.tsempty <= r.tsempty;
uarto.thempty <= r.thempty;
uarto.lock <= r.tcnt(1) and r.tcnt(0);
uarto.enable <= r.rxen;
uarto.data <= r.rhold;
apbo.prdata <= rdata;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
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|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity inter_node is
generic(
size_x : integer := 9;--12; --20 ; --12; --20 --20
size_y : integer := 9;--12; --20 ; --12; --20 --20
interp_x : integer := 4;--8; --4 ; --8; --2 --4
interp_y : integer := 4;--2; --4 ; --1; --2 --4
sample_size : integer := 8;--8; --8 ; --8;
samples_per_wr : integer := 8;--16; --16 ; --8; --4 --16
data_width : integer := 64;--128;--128 ; --64; --32 --128
addr_width : integer := 4;--1; --1 ; --1;
vc_sel_width : integer := 1;--1; --1 ; --1;
num_vc : integer := 2;--2; --2 ; --2;
flit_buff_depth : integer := 8--8 --8 --8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic--;
----debug
--state_out : out std_logic_vector(7 downto 0);
--counter : out std_logic_vector(7 downto 0);
--rd_addr_x_out : out std_logic_vector(7 downto 0);
--rd_addr_y_out : out std_logic_vector(7 downto 0);
--height_out : out std_logic_vector(7 downto 0);
--wr_addr_x_out : out std_logic_vector(7 downto 0);
--wr_addr_y_out : out std_logic_vector(7 downto 0);
--interp_input : out std_logic_vector(9*7*8-1 downto 0)
);
end entity inter_node;
architecture fsmd of inter_node is
---------------------------------------------------------------------------
-- Constants --------------------------------------------------------------
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Components -------------------------------------------------------------
---------------------------------------------------------------------------
component inter_core is
generic(
x_len : integer := 4;
y_len : integer := 4;
sample_size : integer := 8
);
port(
samples : in std_logic_vector((x_len+5)*(y_len+5)*sample_size-1 downto 0);
sel : in std_logic_vector(7 downto 0);
result : out std_logic_vector(x_len*y_len*sample_size-1 downto 0)
);
end component inter_core;
component inter_core_reg_file is
generic(
size_x : integer := 20;
size_y : integer := 20;
interp_x : integer := 1;
interp_y : integer := 1;
sample_size : integer := 4;
samples_per_wr : integer := 1
);
port(
clk : in std_logic;
rst : in std_logic;
--read interface
rd_addr_x : in std_logic_vector(7 downto 0);
rd_addr_y : in std_logic_vector(7 downto 0);
rd_samples : out std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
--write interface
wr_addr_x : in std_logic_vector(7 downto 0);
wr_addr_y : in std_logic_vector(7 downto 0);
wr_enable : in std_logic;
wr_samples : in std_logic_vector(samples_per_wr*sample_size-1 downto 0)
);
end component inter_core_reg_file;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
---------------------------------------------------------------------------
-- Types ------------------------------------------------------------------
---------------------------------------------------------------------------
type inter_states is (idle, sel_vc, init_rx, rx, rx_dequeue, wait_rx, init_tx, gen_resp, wait_tx, tx);
---------------------------------------------------------------------------
-- Signals ----------------------------------------------------------------
---------------------------------------------------------------------------
--component interfaces
signal rd_addr_x : std_logic_vector(7 downto 0);
signal rd_addr_y : std_logic_vector(7 downto 0);
signal rd_samples : std_logic_vector((interp_x+5)*(interp_y+5)*sample_size-1 downto 0);
signal wr_addr_x : std_logic_vector(7 downto 0);
signal wr_addr_y : std_logic_vector(7 downto 0);
signal wr_enable : std_logic;
signal wr_samples : std_logic_vector(samples_per_wr*sample_size-1 downto 0);
signal sel : std_logic_vector(7 downto 0);
signal result : std_logic_vector(interp_x*interp_y*sample_size-1 downto 0);
-- FSMD registers and signals
signal interp_mode_d : std_logic_vector(7 downto 0);
signal interp_mode_q : std_logic_vector(7 downto 0);
signal cmd_width_d : std_logic_vector(7 downto 0);
signal cmd_width_q : std_logic_vector(7 downto 0);
signal cmd_height_d : std_logic_vector(7 downto 0);
signal cmd_height_q : std_logic_vector(7 downto 0);
signal part_width_d : std_logic_vector(7 downto 0);
signal part_width_q : std_logic_vector(7 downto 0);
signal part_height_d : std_logic_vector(7 downto 0);
signal part_height_q : std_logic_vector(7 downto 0);
signal ref_num_d : std_logic_vector(31 downto 0);
signal ref_num_q : std_logic_vector(31 downto 0);
signal counter_d : unsigned(7 downto 0);
signal counter_q : unsigned(7 downto 0);
signal tx_max_count : unsigned(7 downto 0);
signal selected_vc_encoder : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal wr_addr_x_int : integer;
signal wr_addr_y_int : integer;
signal rd_addr_x_int : integer;
signal rd_addr_y_int : integer;
-- state machine signals
signal state : inter_states;
signal next_state : inter_states;
begin
---------------------------------------------------------------------------
-- Datapath ---------------------------------------------------------------
---------------------------------------------------------------------------
u0: component inter_core
generic map(
x_len => interp_x,
y_len => interp_y,
sample_size => sample_size
)
port map(
samples => rd_samples,
sel => sel,
result => result
);
u1: component inter_core_reg_file
generic map(
size_x => size_x,
size_y => size_y,
interp_x => interp_x,
interp_y => interp_y,
sample_size => sample_size,
samples_per_wr => samples_per_wr
)
port map(
clk => clk,
rst => rst,
rd_addr_x => rd_addr_x,
rd_addr_y => rd_addr_y,
rd_samples => rd_samples,
wr_addr_x => wr_addr_x,
wr_addr_y => wr_addr_y,
wr_enable => wr_enable,
wr_samples => wr_samples
);
u2: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => selected_vc_encoder
);
--datapath registers
process(clk, rst)
begin
if rst = '1' then
interp_mode_q <= (others => '0');
cmd_width_q <= (others => '0');
cmd_height_q <= (others => '0');
part_width_q <= (others => '0');
part_height_q <= (others => '0');
ref_num_q <= (others => '0');
counter_q <= (others => '0');
selected_vc_q <= (others => '0');
elsif rising_edge(clk) then
interp_mode_q <= interp_mode_d;
cmd_width_q <= cmd_width_d;
cmd_height_q <= cmd_height_d;
part_width_q <= part_width_d;
part_height_q <= part_height_d;
ref_num_q <= ref_num_d;
counter_q <= counter_d;
selected_vc_q <= selected_vc_d;
end if;
end process;
--Parser logic
ref_num_d <= recv_data(31 downto 0 ) when state = rx and counter_q = x"00" else ref_num_q;
interp_mode_d <= recv_data(7 downto 0 ) when state = rx and counter_q = x"01" else interp_mode_q;
--cmd_width_d <= recv_data(15 downto 8 ) when state = rx and counter_q = x"01" else cmd_width_q;
--cmd_height_d <= recv_data(24 downto 16 ) when state = rx and counter_q = x"01" else cmd_height_q;
part_width_d <= recv_data(15 downto 8) when state = rx and counter_q = x"01" else part_width_q;
part_height_d <= recv_data(23 downto 16) when state = rx and counter_q = x"01" else part_height_q;
sel <= interp_mode_q;
wr_samples <= recv_data(sample_size*samples_per_wr-1 downto 0);
selected_vc_one_hot <= "10" when selected_vc_d = "1" else "01"; --todo make generic
--calculate buffer write addresses
-- for now assume all 20x20 samples are sent every time
-- TODO: this is an oppurtunity for speed improvement latter on
-- time permitting...
-- this will require the use of the width/heigth inputs
wr_addr_x_int <= to_integer(unsigned(counter_q - to_unsigned(2, 8))) mod (size_x/samples_per_wr);
wr_addr_y_int <= to_integer(unsigned(counter_q - to_unsigned(2, 8))) / (size_x/samples_per_wr);
wr_addr_x <= std_logic_vector(to_unsigned(wr_addr_x_int, 8));
wr_addr_y <= std_logic_vector(to_unsigned(wr_addr_y_int, 8));
--buffer controls
wr_enable <= '1' when state = rx and counter_q >= to_unsigned(2, 8) else '0';
--counter update
counter_d <= counter_q + to_unsigned(1, 8) when state = rx_dequeue or state = gen_resp else
to_unsigned(0, 8) when state = init_tx or state = sel_vc else
counter_q;
--select virtual channel
selected_vc_d <= selected_vc_encoder when state = sel_vc else selected_vc_q;
--packet generation logic
assert interp_x*interp_y*sample_size = data_width report "inter_prediction_node: interpolation-block/flit-size mismatch" severity error;
send_data <= X"00000000" & ref_num_q when counter_q = x"01" else result;
rd_addr_x_int <= 2; -- todo: this really shouldn't be a constant, some parameters will not work...
rd_addr_x <= std_logic_vector(to_unsigned(rd_addr_x_int, 8));
rd_addr_y_int <= (to_integer(unsigned(counter_q)) - 2)*2 + 2;
rd_addr_y <= std_logic_vector(to_unsigned(rd_addr_y_int, 8));
tx_max_count <= unsigned(part_height_q) + to_unsigned(1, 8);
--output logic (Noc control stuff)
dequeue <= selected_vc_one_hot when state = rx_dequeue else (others => '0');
select_vc_read <= selected_vc_q;
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when (state = tx or state = wait_tx) and counter_q >= tx_max_count else '0';
send_flit <= '1' when state = tx else '0';
---------------------------------------------------------------------------
-- State Machine ----------------------------------------------------------
---------------------------------------------------------------------------
process(clk, rst)
begin
if rst = '1' then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
process(state, data_in_buffer, is_tail_flit, selected_vc_one_hot, ready_to_send, counter_q, tx_max_count)
begin
--default
next_state <= state;
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= init_rx;
end if;
if state = init_rx then
next_state <= rx;
end if;
if state = rx then
next_state <= rx_dequeue;
end if;
if state = rx_dequeue and is_tail_flit = '0' then
next_state <= wait_rx;
end if;
if state = rx_dequeue and is_tail_flit = '1' then
next_state <= init_tx;
end if;
if state = wait_rx and or_reduce(selected_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx;
end if;
if state = init_tx then
next_state <= gen_resp;
end if;
if state = gen_resp then
next_state <= wait_tx;
end if;
if state = wait_tx and ready_to_send = '1' then
next_state <= tx;
end if;
if state = tx and counter_q < tx_max_count then
next_state <= gen_resp;
end if;
if state = tx and counter_q >= tx_max_count then
next_state <= idle;
end if;
end process;
--debug
--state_out <= x"00" when state = idle else
-- x"01" when state = sel_vc else
-- x"02" when state = init_rx else
-- x"03" when state = rx else
-- x"04" when state = rx_dequeue else
-- x"05" when state = wait_rx else
-- x"06" when state = init_tx else
-- x"07" when state = gen_resp else
-- x"08" when state = wait_tx else
-- x"09" when state = tx else
-- x"FF";
--counter <= std_logic_vector(counter_q);
--rd_addr_x_out <= rd_addr_x;
--rd_addr_y_out <= rd_addr_y;
--height_out <= part_height_q;
--wr_addr_x_out <= wr_addr_x;
--wr_addr_y_out <= wr_addr_y;
--interp_input <= rd_samples;
end architecture fsmd; |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/RADIX22FFT_SDNF1_3_block3.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block3
-- Source Path: hdl_ofdm_tx/ifft/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY RADIX22FFT_SDNF1_3_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_9_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_9_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_13_re : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_13_im : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_9_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_10_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_10_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
dout_9_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block3 IS
-- Signals
SIGNAL twdlXdin_9_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_9_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_13_re_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL twdlXdin_13_im_signed : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(19 DOWNTO 0); -- sfix20
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_9_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_9_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_10_re_tmp : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_10_im_tmp : signed(18 DOWNTO 0); -- sfix19_En13
BEGIN
twdlXdin_9_re_signed <= signed(twdlXdin_9_re);
twdlXdin_9_im_signed <= signed(twdlXdin_9_im);
twdlXdin_13_re_signed <= signed(twdlXdin_13_re);
twdlXdin_13_im_signed <= signed(twdlXdin_13_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 20);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_9_re_signed,
twdlXdin_9_im_signed, twdlXdin_13_re_signed, twdlXdin_13_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(19 DOWNTO 0);
VARIABLE add_cast_0 : signed(19 DOWNTO 0);
VARIABLE sub_cast : signed(19 DOWNTO 0);
VARIABLE sub_cast_0 : signed(19 DOWNTO 0);
VARIABLE add_cast_1 : signed(19 DOWNTO 0);
VARIABLE add_cast_2 : signed(19 DOWNTO 0);
VARIABLE sub_cast_1 : signed(19 DOWNTO 0);
VARIABLE sub_cast_2 : signed(19 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_9_re_signed, 20);
add_cast_0 := resize(twdlXdin_13_re_signed, 20);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_9_re_signed, 20);
sub_cast_0 := resize(twdlXdin_13_re_signed, 20);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_9_im_signed, 20);
add_cast_2 := resize(twdlXdin_13_im_signed, 20);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_9_im_signed, 20);
sub_cast_2 := resize(twdlXdin_13_im_signed, 20);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
dout_9_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(18 DOWNTO 0);
dout_9_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(18 DOWNTO 0);
dout_10_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(18 DOWNTO 0);
dout_10_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(18 DOWNTO 0);
dout_9_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_9_re <= std_logic_vector(dout_9_re_tmp);
dout_9_im <= std_logic_vector(dout_9_im_tmp);
dout_10_re <= std_logic_vector(dout_10_re_tmp);
dout_10_im <= std_logic_vector(dout_10_im_tmp);
END rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Niklas Aldén
--
-- Create Date: 14:02:44 09/16/2014
-- Design Name:
-- Module Name: pre_process - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pre_process is
Port ( i_data : in STD_LOGIC_VECTOR (47 downto 0);
i_length : in STD_LOGIC_VECTOR (2 downto 0);
o_data_0 : out unsigned (31 downto 0);
o_data_1 : out unsigned (31 downto 0);
o_length : out STD_LOGIC_VECTOR (7 downto 0)
);
end pre_process;
architecture Behavioral of pre_process is
begin
data_path : process(i_length, i_data)
begin
if i_length = "001" then --1
o_data_0 <= x"000080" & unsigned(i_data(7 downto 0));
o_data_1 <= (others => '0');
o_length <= x"08";
elsif i_length = "010" then --2
o_data_0 <= x"0080" & unsigned(i_data(15 downto 0));
o_data_1 <= (others => '0');
o_length <= x"10";
elsif i_length = "011" then --3
o_data_0 <= x"80" & unsigned(i_data(23 downto 0));
o_data_1 <= (others => '0');
o_length <= x"18";
elsif i_length = "100" then --4
o_data_0 <= unsigned(i_data(31 downto 0));
o_data_1 <= x"00000080";
o_length <= x"20";
elsif i_length = "101" then --5
o_data_0 <= unsigned(i_data(31 downto 0));
o_data_1 <= x"000080" & unsigned(i_data(39 downto 32));
o_length <= x"28";
elsif i_length = "110" then --6
o_data_0 <= unsigned(i_data(31 downto 0));
o_data_1 <= x"0080" & unsigned(i_data(47 downto 32));
o_length <= x"30";
else --0
o_data_0 <= x"00000080";
o_data_1 <= (others => '0');
o_length <= x"00";
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_8;
USE axi_dma_v7_1_8.axi_dma;
ENTITY design_TEST_axi_dma_1_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_TEST_axi_dma_1_0;
ARCHITECTURE design_TEST_axi_dma_1_0_arch OF design_TEST_axi_dma_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_TEST_axi_dma_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_TEST_axi_dma_1_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_TEST_axi_dma_1_0_arch : ARCHITECTURE IS "design_TEST_axi_dma_1_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_TEST_axi_dma_1_0_arch: ARCHITECTURE IS "design_TEST_axi_dma_1_0,axi_dma,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=0,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=14,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=0,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=256,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 0,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 14,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 0,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 256,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => '0',
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_bvalid => '0',
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_arready => '0',
m_axi_mm2s_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_mm2s_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_mm2s_rlast => '0',
m_axi_mm2s_rvalid => '0',
m_axis_mm2s_tready => '0',
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END design_TEST_axi_dma_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_11;
USE proc_sys_reset_v5_0_11.proc_sys_reset;
ENTITY zynq_design_1_rst_ps7_0_100M_1 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zynq_design_1_rst_ps7_0_100M_1;
ARCHITECTURE zynq_design_1_rst_ps7_0_100M_1_arch OF zynq_design_1_rst_ps7_0_100M_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_design_1_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_design_1_rst_ps7_0_100M_1_arch : ARCHITECTURE IS "zynq_design_1_rst_ps7_0_100M_1,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_design_1_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "zynq_design_1_rst_ps7_0_100M_1,proc_sys_reset,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zynq_design_1_rst_ps7_0_100M_1_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcitrace
-- File: pcitrace.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: PCI trace buffer
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
entity pcitrace is
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of pcitrace is
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCITRACE, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type reg_type is record
sample : std_ulogic;
armed : std_ulogic;
busy : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
admask : std_logic_vector(31 downto 0);
adpattern : std_logic_vector(31 downto 0);
sigmask : std_logic_vector(15 downto 0);
sigpattern : std_logic_vector(15 downto 0);
count : std_logic_vector(7 downto 0);
end record;
type pci_reg_type is record
sample : std_ulogic;
armed : std_ulogic;
sync : std_ulogic;
start : std_ulogic;
timeout : std_logic_vector(depth-1 downto 0);
baddr : std_logic_vector(depth-1 downto 0);
count : std_logic_vector(7 downto 0);
end record;
signal r, rin : reg_type;
signal csad, csctrl : std_ulogic;
signal pr, prin : pci_reg_type;
signal bufout : std_logic_vector(47 downto 0);
signal pciad : std_logic_vector(31 downto 0);
signal vcc : std_ulogic;
signal pcictrlin, pcictrl : std_logic_vector(15 downto 0);
begin
vcc <= '1';
comb: process(pcii, apbi, rst, r, pr, bufout)
variable v : reg_type;
variable rdata : std_logic_vector(31 downto 0);
variable paddr : std_logic_vector(3 downto 0);
variable vcsad, vcssig : std_ulogic;
begin
v := r; vcsad := '0'; vcssig := '0'; rdata := (others => '0');
v.sample := r.armed and not pr.armed; v.busy := pr.sample;
if (r.sample and pr.armed) = '1' then v.armed := '0'; end if;
--registers
paddr := apbi.paddr(15) & apbi.paddr(4 downto 2);
if apbi.penable = '1' then
if (apbi.pwrite and apbi.psel(pindex)) = '1' then
case paddr is
when "0000" => v.admask := apbi.pwdata;
when "0001" => v.sigmask := apbi.pwdata(15 downto 0);
when "0010" => v.adpattern := apbi.pwdata;
when "0011" => v.sigpattern := apbi.pwdata(15 downto 0);
when "0100" => v.timeout := apbi.pwdata(depth-1 downto 0);
when "0101" => v.armed := '1';
when "0111" => v.count := apbi.pwdata(7 downto 0);
when others =>
if apbi.paddr(15 downto 14) = "10" then vcsad := '1';
elsif apbi.paddr(15 downto 14) = "11" then vcssig := '1'; end if;
end case;
end if;
case paddr is
when "0000" => rdata := r.admask;
when "0001" => rdata(15 downto 0) := r.sigmask;
when "0010" => rdata := r.adpattern;
when "0011" => rdata(15 downto 0) := r.sigpattern;
when "0100" => rdata(depth-1 downto 0) := r.timeout;
when "0101" => rdata(0) := r.busy;
when "0110" => rdata(3 downto 0) := conv_std_logic_vector(depth, 4);
when "0111" =>
rdata(depth-1+16 downto 16) := pr.baddr;
rdata(15 downto 0) := pr.count & r.count;
when others =>
if apbi.paddr(15 downto 14) = "10" then
vcsad := '1'; rdata := bufout(31 downto 0);
elsif apbi.paddr(15 downto 14) = "11" then
vcssig := '1'; rdata(15 downto 0) := bufout(47 downto 32);
end if;
end case;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.admask := (others => '0');
v.sigmask := (others => '0'); v.adpattern := (others => '0');
v.sigpattern := (others => '0'); v.timeout := (others => '0');
end if;
csad <= vcsad; csctrl <= vcssig; apbo.prdata <= rdata; rin <= v;
end process;
comb2 : process(r, pr, pciclk, pcii, pcictrl, rst)
variable v : pci_reg_type;
constant z : std_logic_vector(47 downto 0) := (others => '0');
begin
v := pr; v.sync := (r.sample and not pr.armed);
if (pr.sample = '1') then
v.baddr := pr.baddr + 1;
if ((((pcii.ad & pcictrl) xor (r.adpattern & r.sigpattern)) and (r.admask & r.sigmask)) = z) then
if pr.count = "00000000" then v.start := '0';
else v.count := pr.count -1; end if;
end if;
if (pr.start = '0') then
v.timeout := pr.timeout - 1;
if (v.timeout(depth-1) and not pr.timeout(depth-1)) = '1' then
v.sample := '0'; v.armed := '0';
end if;
end if;
end if;
if pr.sync = '1' then
v.start := '1'; v.sample := '1'; v.armed := '1';
v.timeout := r.timeout; v.count := r.count;
end if;
if rst = '0' then
v.sample := '0'; v.armed := '0'; v.start := '0';
v.timeout := (others => '0'); v.baddr := (others => '0');
v.count := (others => '0');
end if;
prin <= v;
end process ;
pcictrlin <= pcii.rst & pcii.idsel & pcii.frame & pcii.trdy & pcii.irdy &
pcii.devsel & pcii.gnt & pcii.stop & pcii.lock & pcii.perr &
pcii.serr & pcii.par & pcii.cbe;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
apbo.pirq <= (others => '0');
seq: process (clk)
begin
if clk'event and clk = '1' then r <= rin; end if;
end process seq;
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then pr <= prin; end if;
end process ;
ir : if iregs = 1 generate
pseq: process (pciclk)
begin
if pciclk'event and pciclk = '1' then
pcictrl <= pcictrlin; pciad <= pcii.ad;
end if;
end process ;
end generate;
noir : if iregs = 0 generate
pcictrl <= pcictrlin; pciad <= pcii.ad;
end generate;
admem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 32, sepclk => 1)
port map (clk, csad, apbi.paddr(depth+1 downto 2), bufout(31 downto 0),
pciclk, pr.sample, pr.baddr, pciad);
ctrlmem : syncram_2p generic map (tech => memtech, abits => depth, dbits => 16, sepclk => 1)
port map (clk, csctrl, apbi.paddr(depth+1 downto 2), bufout(47 downto 32),
pciclk, pr.sample, pr.baddr, pcictrl);
end;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_dut.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore_dut
-- Source Path: lms_pcore/lms_pcore_dut
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore_dut IS
PORT( clk : IN std_logic;
reset : IN std_logic;
dut_enable : IN std_logic; -- ufix1
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic; -- ufix1
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END lms_pcore_dut;
ARCHITECTURE rtl OF lms_pcore_dut IS
-- Component Declarations
COMPONENT LMS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic; -- ufix1
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : LMS
USE ENTITY work.LMS(rtl);
-- Signals
SIGNAL enb : std_logic;
SIGNAL ce_out_sig : std_logic; -- ufix1
SIGNAL e_k_sig : std_logic_vector(15 DOWNTO 0); -- ufix16
BEGIN
u_LMS : LMS
PORT MAP( clk => clk,
clk_enable => enb,
reset => reset,
x_k => x_k, -- sfix16_En14
d_k => d_k, -- sfix16_En14
ce_out => ce_out_sig, -- ufix1
e_k => e_k_sig -- sfix16_En14
);
enb <= dut_enable;
ce_out <= ce_out_sig;
e_k <= e_k_sig;
END rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_dut.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore_dut
-- Source Path: lms_pcore/lms_pcore_dut
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore_dut IS
PORT( clk : IN std_logic;
reset : IN std_logic;
dut_enable : IN std_logic; -- ufix1
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic; -- ufix1
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END lms_pcore_dut;
ARCHITECTURE rtl OF lms_pcore_dut IS
-- Component Declarations
COMPONENT LMS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic; -- ufix1
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : LMS
USE ENTITY work.LMS(rtl);
-- Signals
SIGNAL enb : std_logic;
SIGNAL ce_out_sig : std_logic; -- ufix1
SIGNAL e_k_sig : std_logic_vector(15 DOWNTO 0); -- ufix16
BEGIN
u_LMS : LMS
PORT MAP( clk => clk,
clk_enable => enb,
reset => reset,
x_k => x_k, -- sfix16_En14
d_k => d_k, -- sfix16_En14
ce_out => ce_out_sig, -- ufix1
e_k => e_k_sig -- sfix16_En14
);
enb <= dut_enable;
ce_out <= ce_out_sig;
e_k <= e_k_sig;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity b115to1MUX is
port( in0,in1,in2,in3,in4: in std_logic_vector(10 downto 0);
m: out std_logic_vector(10 downto 0);
sel: in std_logic_vector(2 downto 0));
end b115to1MUX;
architecture behavior of b115to1MUX is
begin
process(sel, in0, in1, in2, in3, in4)
begin
case sel is
when "000" => m<=in0;
when "001" => m<=in1;
when "010" => m<=in2;
when "011" => m<=in3;
when "100" => m<=in4;
when others => m<= (others=> 'Z');
end case;
end process;
end behavior; |
-------------------------------------------------------------------------------
--! @project Unrolled (factor 4) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DiffusionLayer is
generic( SHIFT1 : integer range 0 to 63;
SHIFT2 : integer range 0 to 63);
port( Input : in std_logic_vector(63 downto 0);
Output : out std_logic_vector(63 downto 0));
end entity DiffusionLayer;
architecture structural of DiffusionLayer is
begin
DiffLayer: process(Input) is
variable Temp0,Temp1 : std_logic_vector(63 downto 0);
begin
Temp0(63 downto 64-SHIFT1) := Input(SHIFT1-1 downto 0);
Temp0(63-SHIFT1 downto 0) := Input(63 downto SHIFT1);
Temp1(63 downto 64-SHIFT2) := Input(SHIFT2-1 downto 0);
Temp1(63-SHIFT2 downto 0) := Input(63 downto SHIFT2);
Output <= Temp0 xor Temp1 xor Input;
end process DiffLayer;
end architecture structural;
|
-- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
use std.textio.all;
package std_logic_1164 is
-- Unresolved logic state.
type std_ulogic is
(
'U', -- Uninitialized, this is also the default value.
'X', -- Unknown / conflict value (forcing level).
'0', -- 0 (forcing level).
'1', -- 1 (forcing level).
'Z', -- High impedance.
'W', -- Unknown / conflict (weak level).
'L', -- 0 (weak level).
'H', -- 1 (weak level).
'-' -- Don't care.
);
-- Vector of logic state.
type std_ulogic_vector is array (natural range <>) of std_ulogic;
-- Resolution function.
-- If S is empty, returns 'Z'.
-- If S has one element, return the element.
-- Otherwise, 'U' is the strongest.
-- then 'X'
-- then '0' and '1'
-- then 'W'
-- then 'H' and 'L'
-- then 'Z'.
function resolved (s : std_ulogic_vector) return std_ulogic;
-- Resolved logic state.
subtype std_logic is resolved std_ulogic;
-- Vector of std_logic.
subtype std_logic_vector is (resolved) std_ulogic_vector;
-- Subtypes of std_ulogic. The names give the values.
subtype X01 is resolved std_ulogic range 'X' to '1';
subtype X01Z is resolved std_ulogic range 'X' to 'Z';
subtype UX01 is resolved std_ulogic range 'U' to '1';
subtype UX01Z is resolved std_ulogic range 'U' to 'Z';
-- Logical operators.
-- For logical operations, the inputs are first normalized to UX01:
-- 0 and L are normalized to 0, 1 and 1 are normalized to 1, U isnt changed,
-- all other states are normalized to X.
-- Then the classical electric rules are followed.
function "and" (l : std_ulogic; r : std_ulogic) return UX01;
function "nand" (l : std_ulogic; r : std_ulogic) return UX01;
function "or" (l : std_ulogic; r : std_ulogic) return UX01;
function "nor" (l : std_ulogic; r : std_ulogic) return UX01;
function "xor" (l : std_ulogic; r : std_ulogic) return UX01;
function "xnor" (l : std_ulogic; r : std_ulogic) return UX01;
function "not" (l : std_ulogic) return UX01;
-- Logical operators for vectors.
-- An assertion of severity failure fails if the length of L and R aren't
-- equal. The result range is 1 to L'Length.
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "not" (l : std_ulogic_vector) return std_ulogic_vector;
function "and" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "and" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "nand" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "nand" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "or" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "or" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "nor" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "nor" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "xor" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "xor" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "xnor" (l : std_ulogic_vector; r : std_ulogic )
return std_ulogic_vector;
function "xnor" (l : std_ulogic; r : std_ulogic_vector)
return std_ulogic_vector;
function "and" (l : std_ulogic_vector) return std_ulogic;
function "nand" (l : std_ulogic_vector) return std_ulogic;
function "or" (l : std_ulogic_vector) return std_ulogic;
function "nor" (l : std_ulogic_vector) return std_ulogic;
function "xor" (l : std_ulogic_vector) return std_ulogic;
function "xnor" (l : std_ulogic_vector) return std_ulogic;
function "sll" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
function "srl" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
function "rol" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
function "ror" (l : std_ulogic_vector; r : integer)
return std_ulogic_vector;
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit;
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector;
function to_stdulogic (b : bit) return std_ulogic;
function to_stdlogicvector (b : bit_vector) return std_logic_vector;
function to_stdlogicvector (s : std_ulogic_vector) return std_logic_vector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector;
function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector;
alias to_bit_vector is
to_bitvector[std_ulogic_vector, bit return bit_vector];
alias to_bv is
to_bitvector[std_ulogic_vector, bit return bit_vector];
alias to_std_logic_vector is
to_stdlogicvector[bit_vector return std_logic_vector];
alias to_slv is
to_stdlogicvector[bit_vector return std_logic_vector];
alias to_std_logic_vector is
to_stdlogicvector[std_ulogic_vector return std_logic_vector];
alias to_slv is
to_stdlogicvector[std_ulogic_vector return std_logic_vector];
alias to_std_ulogic_vector is
to_stdulogicvector[bit_vector return std_ulogic_vector];
alias to_sulv is
to_stdulogicvector[bit_vector return std_ulogic_vector];
alias to_std_ulogic_vector is
to_stdulogicvector[std_logic_vector return std_ulogic_vector];
alias to_sulv is
to_stdulogicvector[std_logic_vector return std_ulogic_vector];
-- Normalization.
-- The result range (for vectors) is 1 to S'Length.
function to_01 (s : std_ulogic_vector; xmap : std_ulogic := '0')
return std_ulogic_vector;
function to_01 (s : std_ulogic; xmap : std_ulogic := '0')
return std_ulogic;
function to_01 (s : bit_vector; xmap : std_ulogic := '0')
return std_ulogic_vector;
function to_01 (s : bit; xmap : std_ulogic := '0')
return std_ulogic;
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01 (s : std_ulogic) return X01;
function to_X01 (b : bit_vector) return std_ulogic_vector;
function to_X01 (b : bit) return X01;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01Z (s : std_ulogic) return X01Z;
function to_X01Z (b : bit_vector) return std_ulogic_vector;
function to_X01Z (b : bit) return X01Z;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_UX01 (s : std_ulogic) return UX01;
function to_UX01 (b : bit_vector) return std_ulogic_vector;
function to_UX01 (b : bit) return UX01;
function "??" (l : std_ulogic) return boolean;
-- Edge detection.
-- An edge is detected in case of event on s, and X01 normalized value
-- rises from 0 to 1 or falls from 1 to 0.
function rising_edge (signal s : std_ulogic) return boolean;
function falling_edge (signal s : std_ulogic) return boolean;
-- Test for unknown. Only 0, 1, L and H are known values.
function is_X (s : std_ulogic_vector) return boolean;
function is_X (s : std_ulogic) return boolean;
-- String conversion
alias to_bstring is to_string [std_ulogic_vector return string];
alias to_binary_string is to_string [std_ulogic_vector return string];
function to_ostring (value : std_ulogic_vector) return string;
alias to_octal_string is to_ostring [std_ulogic_vector return string];
function to_hstring (value : std_ulogic_vector) return string;
alias to_hex_string is to_hstring [std_ulogic_vector return string];
-- Input/output
procedure write (l : inout line; value : std_ulogic;
justified : side := right; field : width := 0);
procedure write (l : inout line; value : std_ulogic_vector;
justified : side := right; field : width := 0);
alias bwrite is write [line, std_ulogic_vector, side, width];
alias binary_write is write [line, std_ulogic_vector, side, width];
procedure owrite (l : inout line; value : std_ulogic_vector;
justified : side := right; field : width := 0);
alias octal_write is owrite [line, std_ulogic_vector, side, width];
procedure hwrite (l : inout line; value : std_ulogic_vector;
justified : side := right; field : width := 0);
alias hex_write is hwrite [line, std_ulogic_vector, side, width];
procedure read (l : inout line;
value : out std_ulogic; good : out boolean);
procedure read (l : inout line; value : out std_ulogic);
procedure read (l : inout line;
value : out std_ulogic_vector; good : out boolean);
procedure read (l : inout line; value : out std_ulogic_vector);
alias bread is read [line, std_ulogic_vector, boolean];
alias bread is read [line, std_ulogic_vector];
alias binary_read is read [line, std_ulogic_vector, boolean];
alias binary_read is read [line, std_ulogic_vector];
procedure hread (l : inout line;
value : out std_ulogic_vector; good : out boolean);
procedure hread (l : inout line; value : out std_ulogic_vector);
alias hex_read is read [line, std_ulogic_vector, boolean];
alias hex_read is read [line, std_ulogic_vector];
procedure oread (l : inout line;
value : out std_ulogic_vector; good : out boolean);
procedure oread (l : inout line; value : out std_ulogic_vector);
alias octal_read is read [line, std_ulogic_vector, boolean];
alias octal_read is read [line, std_ulogic_vector];
end std_logic_1164;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity memory is
port(
address : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity memory;
architecture RTL of memory is
type mem_arr is array (integer range <>) of std_logic_vector(7 downto 0);
signal mem : mem_arr(0 to (2**address'length)-1) :=
%%
begin
data <= mem(to_integer(unsigned(address)));
end architecture RTL;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio : std_logic;
signal tick_counter : std_logic;
signal tick_counter_d1 : std_logic;
signal tick_counter_d2 : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
tick_counter <= not tick_counter;
end if;
end process DCLK;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
tick_counter_d1 <= '0';
tick_counter_d2 <= '0';
spdif_clk_en <= '0';
else
tick_counter_d1 <= tick_counter;
tick_counter_d2 <= tick_counter_d1;
spdif_clk_en <= '0';
if (tick_counter_d1 xor tick_counter_d2) = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
sample_data_ack <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
sample_data_ack <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
sample_data_ack <='1';
end if;
when READ_CHA =>
channel <= '0';
sample_data_ack <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
sample_data_ack <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
if resetn = '0' then
spdif_tx_o <= '0';
else
spdif_tx_o <= spdif_out;
end if;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= def_user_data;
end rtl;
|
-------------------------------------------------------------------------------
-- module_1_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity module_1_stub is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
coprocessor_0_LED_OUT_pin : out std_logic_vector(7 downto 0);
coprocessor_0_SW_IN_pin : in std_logic_vector(7 downto 0);
coprocessor_0_BTN_IN_pin : in std_logic_vector(4 downto 0)
);
end module_1_stub;
architecture STRUCTURE of module_1_stub is
component module_1 is
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB_pin : in std_logic;
processing_system7_0_PS_CLK_pin : in std_logic;
processing_system7_0_PS_PORB_pin : in std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : out std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
coprocessor_0_LED_OUT_pin : out std_logic_vector(7 downto 0);
coprocessor_0_SW_IN_pin : in std_logic_vector(7 downto 0);
coprocessor_0_BTN_IN_pin : in std_logic_vector(4 downto 0)
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of module_1 : component is "user_black_box";
begin
module_1_i : module_1
port map (
processing_system7_0_MIO => processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin => processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin => processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin => processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM => processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP,
coprocessor_0_LED_OUT_pin => coprocessor_0_LED_OUT_pin,
coprocessor_0_SW_IN_pin => coprocessor_0_SW_IN_pin,
coprocessor_0_BTN_IN_pin => coprocessor_0_BTN_IN_pin
);
end architecture STRUCTURE;
|
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
|
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
|
-- Tri-State driver component
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tristate IS
GENERIC(width : positive);
PORT(
ENABLE : IN std_logic;
INPUT : IN std_logic_vector(width-1 DOWNTO 0);
OUTPUT : OUT std_logic_vector(width-1 DOWNTO 0)
);
END tristate;
ARCHITECTURE primitive OF tristate IS
BEGIN
OUTPUT <= INPUT WHEN ENABLE='1' ELSE (OTHERS => 'Z');
END primitive;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12496)
`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty,
m_axis_updt_tready,
updt_tvalid,
updt_tlast)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty = '0')then
write_curdesc_lsb <= '1';
dataq_rden <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(ptr_queue_empty = '0')then
dataq_rden <= '1';
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid = '1' and m_axis_updt_tready = '1'
and updt_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
-- Channel Pointer Queue (Generate Synchronous FIFO)
I_UPDT_DATA_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_READ_DEPTH => UPDATE_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => ptr_queue_din ,
Wr_en => ptr_queue_wren ,
Rd_en => ptr_queue_rden ,
Dout => ptr_queue_dout ,
Full => ptr_queue_full ,
Empty => ptr_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- Channel Status Queue (Generate Synchronous FIFO)
I_UPDT_STS_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => STS_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0 ,
C_HAS_DCOUNT => 1 , --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_HAS_ALMOST_FULL => 0 ,
C_HAS_RD_ACK => 0 ,
C_HAS_RD_ERR => 0 ,
C_HAS_WR_ACK => 0 ,
C_HAS_WR_ERR => 0 ,
C_RD_ACK_LOW => 0 ,
C_RD_ERR_LOW => 0 ,
C_WR_ACK_LOW => 0 ,
C_WR_ERR_LOW => 0 ,
C_PRELOAD_REGS => 1 ,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => sts_queue_din ,
Wr_en => sts_queue_wren ,
Rd_en => sts_queue_rden ,
Dout => sts_queue_dout ,
Full => sts_queue_full ,
Empty => sts_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
end generate GEN_Q_FOR_SYNC;
GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate
begin
-- Generate Asynchronous FIFO
I_UPDT_DATA_FIFO : entity axi_vdma_v6_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_DEPTH => UPDATE_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => UPD_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => ptr_queue_wren ,
AFIFO_Din => ptr_queue_din ,
AFIFO_Rd_clk => s_axis_updt_aclk ,
AFIFO_Rd_en => ptr_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => ptr_queue_dout ,
AFIFO_Full => ptr_queue_full ,
AFIFO_Empty => ptr_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-- Generate Asynchronous FIFO
I_UPDT_STS_FIFO : entity axi_vdma_v6_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 ,
C_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => STS_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => s_axis_updt_aclk ,
AFIFO_Wr_en => sts_queue_wren ,
AFIFO_Din => sts_queue_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => sts_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => sts_queue_dout ,
AFIFO_Full => sts_queue_full ,
AFIFO_Empty => sts_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate GEN_Q_FOR_ASYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt_queue_empty <= ptr_queue_empty
or sts_queue_empty;
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
updt_tvalid <= not sts_queue_empty
and writing_status;
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
updt_tlast <= not sts_queue_empty
and writing_status
and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-----------------------------------------------------------------------
-- TDATA - drive data to datamover from status queue
-----------------------------------------------------------------------
m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= updt_tvalid;
m_axis_updt_tlast <= updt_tlast;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_sg_ftchq_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Seperated update queues into two seperate files, no queue and queue to
-- simplify maintainance.
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= updt_active and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty,
m_axis_updt_tready,
updt_tvalid,
updt_tlast)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty = '0')then
write_curdesc_lsb <= '1';
dataq_rden <= '1';
pntr_ns <= READ_CURDESC_MSB;
else
pntr_ns <= READ_CURDESC_LSB;
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(ptr_queue_empty = '0')then
dataq_rden <= '1';
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid = '1' and m_axis_updt_tready = '1'
and updt_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
when others =>
pntr_ns <= IDLE;
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
-- Channel Pointer Queue (Generate Synchronous FIFO)
I_UPDT_DATA_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => UPD_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_WRITE_DEPTH => UPDATE_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_READ_DEPTH => UPDATE_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 1, --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => ptr_queue_din ,
Wr_en => ptr_queue_wren ,
Rd_en => ptr_queue_rden ,
Dout => ptr_queue_dout ,
Full => ptr_queue_full ,
Empty => ptr_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- Channel Status Queue (Generate Synchronous FIFO)
I_UPDT_STS_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => STS_Q_MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_WRITE_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 , --add 1 for tlast storage
C_READ_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0 ,
C_HAS_DCOUNT => 1 , --req for proper fifo operation
C_DCOUNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_HAS_ALMOST_FULL => 0 ,
C_HAS_RD_ACK => 0 ,
C_HAS_RD_ERR => 0 ,
C_HAS_WR_ACK => 0 ,
C_HAS_WR_ERR => 0 ,
C_RD_ACK_LOW => 0 ,
C_RD_ERR_LOW => 0 ,
C_WR_ACK_LOW => 0 ,
C_WR_ERR_LOW => 0 ,
C_PRELOAD_REGS => 1 ,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => sts_queue_din ,
Wr_en => sts_queue_wren ,
Rd_en => sts_queue_rden ,
Dout => sts_queue_dout ,
Full => sts_queue_full ,
Empty => sts_queue_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
end generate GEN_Q_FOR_SYNC;
GEN_Q_FOR_ASYNC : if C_AXIS_IS_ASYNC = 1 generate
begin
-- Generate Asynchronous FIFO
I_UPDT_DATA_FIFO : entity axi_vdma_v6_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_DEPTH => UPDATE_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => UPD_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => ptr_queue_wren ,
AFIFO_Din => ptr_queue_din ,
AFIFO_Rd_clk => s_axis_updt_aclk ,
AFIFO_Rd_en => ptr_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => ptr_queue_dout ,
AFIFO_Full => ptr_queue_full ,
AFIFO_Empty => ptr_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-- Generate Asynchronous FIFO
I_UPDT_STS_FIFO : entity axi_vdma_v6_2.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH + 1 ,
C_DEPTH => UPDATE_STS_QUEUE_DEPTH ,
C_CNT_WIDTH => UPDATE_STS_QUEUE_CNT_WIDTH ,
C_USE_BLKMEM => STS_Q_MEMORY_TYPE ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => s_axis_updt_aclk ,
AFIFO_Wr_en => sts_queue_wren ,
AFIFO_Din => sts_queue_din ,
AFIFO_Rd_clk => m_axi_sg_aclk ,
AFIFO_Rd_en => sts_queue_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => sts_queue_dout ,
AFIFO_Full => sts_queue_full ,
AFIFO_Empty => sts_queue_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate GEN_Q_FOR_ASYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_S_AXIS_UPDPTR_TDATA_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt_queue_empty <= ptr_queue_empty
or sts_queue_empty;
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
updt_tvalid <= not sts_queue_empty
and writing_status;
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
updt_tlast <= not sts_queue_empty
and writing_status
and sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-----------------------------------------------------------------------
-- TDATA - drive data to datamover from status queue
-----------------------------------------------------------------------
m_axis_updt_tdata <= sts_queue_dout(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid <= updt_tvalid;
m_axis_updt_tlast <= updt_tlast;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= ptr_queue_dout(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re = '1')then
updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re = '1')then
dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re = '1')then
dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re = '1')then
dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
end implementation;
|
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`protect begin_protected
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc294.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n02i00294ent IS
END c03s01b03x01p01n02i00294ent;
ARCHITECTURE c03s01b03x01p01n02i00294arch OF c03s01b03x01p01n02i00294ent IS
signal T1 : TIME := -2147483647 ns;
signal T2 : TIME := +2147483467 ns; -- no_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(T1=-2147483647 ns and T2=+2147483467 ns)
report "***PASSED TEST:c03s01b03x01p01n02i00294"
severity NOTE;
assert (T1=-2147483647 ns and T2=+2147483467 ns)
report "***FAILED TEST: c03s01b03x01p01n02i00294 - The range of TIME is guaranteed to include the range -2147483647 to +2147483467."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n02i00294arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc294.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n02i00294ent IS
END c03s01b03x01p01n02i00294ent;
ARCHITECTURE c03s01b03x01p01n02i00294arch OF c03s01b03x01p01n02i00294ent IS
signal T1 : TIME := -2147483647 ns;
signal T2 : TIME := +2147483467 ns; -- no_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(T1=-2147483647 ns and T2=+2147483467 ns)
report "***PASSED TEST:c03s01b03x01p01n02i00294"
severity NOTE;
assert (T1=-2147483647 ns and T2=+2147483467 ns)
report "***FAILED TEST: c03s01b03x01p01n02i00294 - The range of TIME is guaranteed to include the range -2147483647 to +2147483467."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n02i00294arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc294.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n02i00294ent IS
END c03s01b03x01p01n02i00294ent;
ARCHITECTURE c03s01b03x01p01n02i00294arch OF c03s01b03x01p01n02i00294ent IS
signal T1 : TIME := -2147483647 ns;
signal T2 : TIME := +2147483467 ns; -- no_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(T1=-2147483647 ns and T2=+2147483467 ns)
report "***PASSED TEST:c03s01b03x01p01n02i00294"
severity NOTE;
assert (T1=-2147483647 ns and T2=+2147483467 ns)
report "***FAILED TEST: c03s01b03x01p01n02i00294 - The range of TIME is guaranteed to include the range -2147483647 to +2147483467."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n02i00294arch;
|
architecture RTL of ENT is
begin
-- vsg_disable_next_line process_016
process (A) is
begin
-- vsg_disable_next_line process_018
end process;
process (A) is
begin
end process;
-- vsg_disable_next_line process_016
-- vsg_disable_next_line process_002
process(A)is
begin
-- vsg_disable_next_line process_018
end process;
process (A) is
begin
end process;
-- vsg_disable_next_line architecture_024
end architecture;
|
-- DAS ATV-System Testplatform
-- Pinout:
-- HDMI_CLK: GPIO_1_IN0
-- HDMI_DE: GPIO_12
-- HDMI_VS: GPIO_11
-- HDMI_HS: GPIO_10
-- HDMI_R(5:0): GPIO_13, GPIO_14, GPIO_15, GPIO_16, GPIO_17, GPIO_18
-- HDMI_G(5:0): GPIO_110, GPIO_111, GPIO_112, GPIO_113, GPIO_114, GPIO_115
-- HDMI_B(5:0): GPIO_116, GPIO_117, GPIO_118, GPIO_119, GPIO_120, GPIO_121
-- DAC_CLK_I: GPIO_125
-- DAC_CLK_Q: GPIO_122
-- DAC_D(11:0): GPIO_21, GPIO_22, GPIO_20, GPIO_25, GPIO_23, GPIO_24, GPIO_26,
-- GPIO_27, GPIO_28, GPIO_29, GPIO_210, GPIO_211
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hdmi2pal is
port
(
CLK50 : in std_logic;
HDMI_CLK : in std_logic;
HDMI_DE : in std_logic;
HDMI_VS : in std_logic;
HDMI_HS : in std_logic;
HDMI_R : in std_logic_vector(5 downto 0);
HDMI_G : in std_logic_vector(5 downto 0);
HDMI_B : in std_logic_vector(5 downto 0);
DAC_CLK_I : out std_logic;
DAC_CLK_Q : out std_logic;
DAC_D : out std_logic_vector(11 downto 0);
LED : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of hdmi2pal is
function to_fcw(frequency : real) return positive is
constant sample_rate : real := 50_000_000.0;
constant bit_width : integer := 16;
begin
return integer(frequency / sample_rate * real(2**bit_width));
end function;
signal sync : std_logic;
signal burst : std_logic;
signal hdmi_freq : std_logic_vector(10 downto 0);
signal hdmi_ok : std_logic;
signal clk27 : std_logic;
signal clk27_locked : std_logic;
signal clk27_sw : std_logic;
signal clk108 : std_logic;
signal clk108_locked: std_logic;
signal clksel : std_logic;
signal sin_out : signed(11 downto 0);
begin
pll1 : entity work.pll
port map(
clkswitch => clksel,
inclk0 => HDMI_CLK,
inclk1 => clk27,
c0 => clk108,
locked => clk108_locked
);
DAC_CLK_I <= CLK50;
pll2 : entity work.pll2
port map(
inclk0 => CLK50,
c0 => clk27,
locked => clk27_locked
);
clksel <= '0' when hdmi_ok = '1' else '1';
ctrl : entity work.clkctrl
port map(
clkselect => clksel,
ena => '1',
inclk0x => HDMI_CLK,
inclk1x => clk27,
outclk => clk27_sw
);
hdmi_ok <= '1' when unsigned(hdmi_freq) = 270 else '0';
fcnt : entity work.frequency_counter
generic map(
res => 11,
gate => 500
)
port map(
clk => CLK50,
cnt_in => HDMI_CLK,
cnt_out => hdmi_freq
);
tgen : entity work.timing_gen
port map(
clk => HDMI_CLK,
vs => HDMI_VS,
hs => HDMI_HS,
de => HDMI_DE,
sync => sync,
burst => burst
);
sin_gen : entity work.nco
generic map(
A => 12,
F => 16,
P => 16,
N => 14,
FCW => to_fcw(1_000_000.0)
)
port map(
clk => CLK50,
sin => sin_out,
cos => open
);
DAC_D <= std_logic_vector(b"1000_0000_0000" - sin_out);
LED(7) <= sync;
LED(6) <= HDMI_DE;
LED(5) <= HDMI_HS;
LED(4) <= HDMI_VS;
LED(3) <= burst;
LED(2) <= hdmi_ok;
LED(1) <= clk27_locked;
LED(0) <= clk108_locked;
end rtl;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: dualBRAM_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY dualBRAM_tb IS
END ENTITY;
ARCHITECTURE dualBRAM_tb_ARCH OF dualBRAM_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
dualBRAM_synth_inst:ENTITY work.dualBRAM_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- $Id: tb_arty_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_arty_core - sim
-- Description: Test bench for arty - core device handling
--
-- Dependencies: -
--
-- To test: generic, any arty target
--
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0 Initial version (derived from tb_basys3_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_arty_core is
port (
I_SWI : out slv4; -- arty switches
I_BTN : out slv4 -- arty buttons
);
end tb_arty_core;
architecture sim of tb_arty_core is
signal R_SWI : slv4 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect key_block
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TgMazjcXBCFfPCwjdhXMmRCWWKji9+YY7mzQfD8dwxTq3nitpJj9/zHmf939W8iiO7+EUF0G7fhh
zuw9xzCagg54kgBxT0sb0z8RV5iWzxI0WW9esaKXtHQFhcgduhvLNG1H2r6Ww1D86rD0H2pKiJDn
KeYLzo/4IpKx657c3eqMz4NjqagFj4SDZuHVuMM6qsFjSW7+gtQbiH58TvTUP0ad7AVByAECF+1j
93K8MdB1kRIJS7DoV90vXk8bpY77f1m2UQ2H+cuu+WJVkDm64ied6AQaSSkZ7rzU0ug6fuOhGpgv
cw6gn60t94v0AanCQ1OOstP/bKPNJK1KP4o4MxHZlQwA25froINJvD/i+zhkn9ZU6oPTy2nXzb0i
s1wanbwyl7HSGbgDLxP6DbsOlmcGYhXNIjOHZuNA59oRVd16zYpDUFW5G4OA6eHmtXjZqKv0Lwco
9ALZ7lLa8w+FG6Qs/g0KZgCviMEuobNmqFn6QZ+a8cVz52sgTkKhMSdCdV68psLkEos2lUavtac3
CE4aCTaP0StnMMdHe3JSLEQ62SpsZdsP+JTIf/LKXZKbkjNJ3veljrAPOUmZGjL5I0aDx/qQV02Y
7AqMeAQDoDuulYqC+sNYycMiOro2OOfiX+zAzred5xQUW3W9iHqG3ho1N2coWJc6RkS/dQRHPXb/
aNxDMGTLBmCUxg2ozQ34fkG4TApG8mR2p1xmVeAmg/1EyBGVfVhZn6/caUI/jIIoR9+Z6hw3O6U+
saPpkizSZUkxu1KkqFomDyeW3sh36P4R8t1U+9fhQLmfj+2egGYXZThiZAZeSCLUo7l2ZxXEMOQv
q0pQvQWpPhnRjkoRGFCiHsnb0rI2j0kW8VdzbMqNXUXAgc5jQvucDY8HNFagW6ZuBqiyqN9S5Wmk
+/fb/TfgbA4kCdflBUUbSgPVhrZAo04e9vOu703x1FPc6efFXW6Gha8Li8vVzMyLCRrVisYgcuyz
zF0PXph0PERHCRcoE/j0PikmjUj0MYm1HnW83+cxm+IoZx3gHyz5Gew17ymnUMcAUzY0rlBt6wv5
y37RCl+ICHf8Gbp/nk4KfaFn2YI+DK70aaTV1ykRCjZYNCdJ8PsQ/igoicVTWpRy127r+YKzK2vH
EsI8T/DYAO1p8ZmPzROEeaqUg1B97Ti9O4mb7A4rjWKREjzODpAx9nKX1cQ8OofuHHvQni0sxctY
P4UsKV/C4ABoCnWWN/ubPDGIi7ibU8BH/+4LPcnEZFWyf/Moo8ZfNQKVgFLl/OQs1H0mir/y9adg
hgi91zJuixM/dBrVGowtQ9G+RworRyRtcg==
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity UartClkDiv is
port(
CLKin : in std_logic;
CLKTXD_out : inout std_logic:='0';
CLKRXD_out : inout std_logic:='0');
end UartClkDiv;
architecture Behavioral of UartClkDiv is
signal count : integer :=1;
signal count2 : integer :=1;
----------------------------------------------------------------------
begin
-------------------------------------------------
process(CLKin)
begin
if(CLKin'event and CLKin='1') then
count <= count + 1;
if(count = 434) then --<FOR CLKIN 100MZ>--
CLKTXD_out <= not CLKTXD_out;
count <=1;
end if;
end if;
end process;
-------------------------------------------------
process(CLKin)
begin
if(CLKin'event and CLKin='1') then
count2 <= count2 + 1;
if(count2 = 27) then --<FOR CLKIN 100MZ>--
CLKRXD_out <= not CLKRXD_out;
count2 <=1;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
entity hwt_semaphore is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector( 0 to C_BURST_AWIDTH-1 );
o_RAMData : out std_logic_vector( 0 to C_BURST_DWIDTH-1 );
i_RAMData : in std_logic_vector( 0 to C_BURST_DWIDTH-1 );
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end entity;
architecture Behavioral of hwt_semaphore is
attribute keep_hierarchy : string;
attribute keep_hierarchy of Behavioral: architecture is "true";
constant C_SEMAPHORE_A : std_logic_vector(31 downto 0) := X"00000000";
constant C_SEMAPHORE_B : std_logic_vector(31 downto 0) := X"00000001";
type t_state is ( STATE_WAIT_A,
STATE_POST_B);
signal state : t_state;
begin
state_proc: process( clk, reset )
begin
if reset = '1' then
reconos_reset( o_osif, i_osif );
state <= STATE_WAIT_A;
elsif rising_edge( clk ) then
reconos_begin( o_osif, i_osif );
if reconos_ready( i_osif ) then
case state is
when STATE_WAIT_A =>
reconos_sem_wait(o_osif,i_osif,C_SEMAPHORE_A);
state <= STATE_POST_B;
when STATE_POST_B =>
reconos_sem_post(o_osif,i_osif,C_SEMAPHORE_B);
state <= STATE_WAIT_A;
end case;
end if;
end if;
end process;
end architecture;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0'when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0'when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0'when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0'when rd_en = '1' else '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0'when rd_en = '1' else '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0'when rd_en = '1' else '1';
concurrent_wr_en_b <= '0' when rd_en = '1' else '1';
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- UART Loopback Testbench
--
-- Self checking testbench that wires the UART in loopback configuration (Rx
-- data is echoed back to Tx). An ASCII text is transmitted from the external
-- device and the testbench checks that the same text is received by the
-- external device.
--
--------------------------------------------------------------------------------
-- This work is licensed under the MIT License (see the LICENSE file for terms)
-- Copyright 2016 Lymperis Voudouris
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity tb_uart is
end entity tb_uart;
architecture behv of tb_uart is
------------------------------------------
-- uart_tx
------------------------------------------
-- Emulates an external UART device Tx
-- txdata : Data to transmit
-- tx : Tx data line
-- T_UART : UART period (bit duration)
procedure uart_tx (
variable txdata : in std_logic_vector(7 downto 0);
signal tx : inout std_logic;
constant T_UART : in time) is
begin
tx <= '0'; -- start bit
wait for T_UART;
for i in 0 to 7 loop
tx <= txdata(i);
wait for T_UART;
end loop;
tx <= '1'; -- stop bit
wait for T_UART;
end uart_tx;
------------------------------------------
-- uart_rx
------------------------------------------
-- Emulates an external UART device Rx
-- rx : Rx data line
-- rxdata : Data received
-- T_UART : UART period (bit duration)
procedure uart_rx (
signal rx : in std_logic;
variable rxdata : out std_logic_vector(7 downto 0);
constant T_UART : in time) is
begin
wait until falling_edge(rx);
wait for T_UART/2;
for n in 0 to 7 loop
wait for T_UART;
rxdata(n) := rx;
end loop;
wait for T_UART;
assert (rx = '1') report "Incorrect UART stop bit" severity error;
end uart_rx;
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
constant C_UART_PERIOD : time := 800 ns; -- 1.25 Mbaud
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal tx_i : std_logic := '1';
signal tx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal tx_data_wr_i : std_logic := '0';
signal tx_fifo_full_i : std_logic := '0';
signal rx_i : std_logic := '1';
signal rx_data_i : std_logic_vector(7 downto 0) := (others=>'0');
signal rx_data_rd_i : std_logic := '0';
signal rx_fifo_empty_i : std_logic := '0';
signal transmitted_text : string(1 to 9) := "TEST_1234";
begin
clk <= not clk after C_CLK_PERIOD/2;
rst <= '1', '0' after 1000 ns;
-- Loopback. Connect rx fifo output to tx fifo input
tx_data_i <= rx_data_i;
-- External device UART transmitter
proc_external_uart_tx:
process
variable txdata : std_logic_vector(7 downto 0) := (others=>'0');
begin
wait until falling_edge(rst);
-- transmit each character of the string (least significant char first)
for n in transmitted_text'range loop
wait for 133 ns; -- wait some arbitrary amount of time
txdata := std_logic_vector(to_unsigned(character'pos(transmitted_text(n)), 8));
uart_tx(txdata, rx_i, C_UART_PERIOD);
end loop;
wait;
end process;
-- Read/Write UART Rx/Tx FIFOs
proc_loopback:
process
begin
wait until falling_edge(rst);
-- Repeat for every character
for n in transmitted_text'range loop
-- wait until rx fifo has some data
if (rx_fifo_empty_i='1') then
wait until rx_fifo_empty_i = '0';
end if;
-- Read pulse
wait until rising_edge(clk);
rx_data_rd_i <= '1';
wait until rising_edge(clk);
rx_data_rd_i <= '0';
-- check if tx fifo is full before writing
-- any data (not really necessary in loopback
-- configuration)
if (tx_fifo_full_i = '1') then
wait until tx_fifo_full_i = '0';
end if;
-- Write pulse
wait until rising_edge(clk);
tx_data_wr_i <= '1';
wait until rising_edge(clk);
tx_data_wr_i <= '0';
end loop;
wait;
end process;
-- External device UART receiver
proc_external_uart_rx:
process
variable rxdata : std_logic_vector(7 downto 0) := (others=>'0');
variable received_text : string(transmitted_text'range);
begin
-- Receive characters and store them in a string
for n in transmitted_text'range loop
uart_rx(tx_i, rxdata, C_UART_PERIOD);
received_text(n) := character'val(to_integer(unsigned(rxdata)));
end loop;
-- Fail simulation if received text is not equal to the transmitted text
assert (received_text = transmitted_text)
report "Received text: " & received_text & " is not equal to trasmitted text: " & transmitted_text
severity failure;
-- All is well. Report success
assert false
report "Successfuly received transmitted text: " & received_text
severity note;
wait;
end process;
------------------------------------------------
-- UART
------------------------------------------------
uart_inst : entity work.uart(rtl)
generic map(
G_BAUD_RATE => 1250000,
G_CLOCK_FREQ => 100.0e6
)
port map(
clk => clk,
rst => rst,
tx_data_in => tx_data_i,
tx_data_wr_in => tx_data_wr_i,
tx_fifo_full_out => tx_fifo_full_i,
tx_out => tx_i,
rx_in => rx_i,
rx_data_rd_in => rx_data_rd_i,
rx_data_out => rx_data_i,
rx_fifo_empty_out => rx_fifo_empty_i
);
end architecture behv; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.mechanical_systems.all;
entity stop_r is
generic ( k_stop : real := 1.0e6;
ang_max : real := 1.05;
ang_min : real := -1.05;
damp_stop : real := 1.0e2 );
port ( terminal ang1, ang2 : rotational );
end entity stop_r;
----------------------------------------------------------------
architecture ideal of stop_r is
quantity qvelocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
qvelocity == ang'dot;
if ang > ang_max use -- Hit upper stop, generate opposing torque
trq == k_stop * (ang - ang_max) + (damp_stop * qvelocity);
elsif ang > ang_min use -- Between stops, no opposing torque
trq == 0.0;
else -- Hit lower stop, generate opposing torque
trq == k_stop * (ang - ang_min) + (damp_stop * qvelocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2 is
port (
a, b: in std_logic;
z : out std_logic
);
end NOR2;
architecture Arch of NOR2 is
begin
Z <= a nor b;
end Arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2 is
port (
a, b: in std_logic;
z : out std_logic
);
end NOR2;
architecture Arch of NOR2 is
begin
Z <= a nor b;
end Arch; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOR2 is
port (
a, b: in std_logic;
z : out std_logic
);
end NOR2;
architecture Arch of NOR2 is
begin
Z <= a nor b;
end Arch; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- La video ram es implementada con la dual port ram, por ende A es la escritura y B lectura.
entity video_ram is
generic(
-- Bits por fila/columna
N_bits_row : integer := 10;
N_bits_col : integer := 10;
-- Numero de filas/columnas
N_rows : integer := 480; ---NO SE USAN
N_cols : integer := 640
);
port(
clock: in std_logic;
write_enable : in std_logic;
barrido: in std_logic;
A_row : in std_logic_vector(N_bits_row-1 downto 0);
B_row : in std_logic_vector(N_bits_row-1 downto 0);
A_col : in std_logic_vector(N_bits_col-1 downto 0);
B_col : in std_logic_vector(N_bits_col-1 downto 0);
data_A : in std_logic;
data_B : out std_logic
);
end entity video_ram;
architecture video_ram_arch of video_ram is
--Declaracion de componentes a utilizar (se utiliza la dual port ram)
component dual_port_ram is
generic(
data_width : natural := 1;
addr_width : natural := 18
);
port(
clock: in std_logic;
write_enable : in std_logic;
barrido : in std_logic;
addr_A : in std_logic_vector(addr_width-1 downto 0);
addr_B : in std_logic_vector(addr_width-1 downto 0);
data_A : in std_logic_vector(data_width-1 downto 0);
data_B : out std_logic_vector(data_width-1 downto 0)
);
end component;
--Senales auxiliares
signal address_A :std_logic_vector(N_bits_row+N_bits_col -1 downto 0):= (others => '0');
signal address_B :std_logic_vector(N_bits_row+N_bits_col -1 downto 0):= (others => '0');
begin
address_A <= A_row & A_col; --La dirección A es la concantenacion de fila y columna ---CREO Q HAY Q OPTIMIZAR ESTO
address_B <= B_row & B_col; --La dirección B es la concantenacion de fila y columna ---mirar gen_dirs.vhd
--Instanciación de los componentes a utilizar
video_dual_port_ram: dual_port_ram
generic map(
data_width => 1,
addr_width => 5---N_bits_row + N_bits_col ---TESTEO
)
port map(
clock =>clock,
write_enable =>write_enable,
barrido => barrido,
addr_A =>"00000",---address_A,
addr_B =>"00000",---address_B,
data_A(0) =>data_A,
data_B(0) =>data_B
);
end video_ram_arch;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_ok_2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ok_2_e-c.vhd,v 1.2 2005/07/15 16:20:01 wig Exp $
-- $Date: 2005/07/15 16:20:01 $
-- $Log: inst_ok_2_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:20:01 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_ok_2_rtl_conf / inst_ok_2_e
--
configuration inst_ok_2_rtl_conf of inst_ok_2_e is
for rtl
-- Generated Configuration
end for;
end inst_ok_2_rtl_conf;
--
-- End of Generated Configuration inst_ok_2_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IPv4_source is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
source : out std_logic_vector(31 downto 0)
);
end IPv4_source;
architecture Behavioral of IPv4_source is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
source <= (others=>'0');
elsif address_counter = 27 then
source(31 downto 24) <= data_in;
elsif address_counter = 28 then
source(23 downto 16) <= data_in;
elsif address_counter = 29 then
source(15 downto 8) <= data_in;
elsif address_counter = 30 then
source(7 downto 0) <= data_in;
end if;
end if;
end process;
end Behavioral; |
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0;
USE axi_timer_v2_0.axi_timer;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_timer:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_timer_v2_0;
USE axi_timer_v2_0.axi_timer;
ENTITY Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0 IS
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0;
ARCHITECTURE Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_timer IS
GENERIC (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : STD_LOGIC;
C_TRIG1_ASSERT : STD_LOGIC;
C_GEN0_ASSERT : STD_LOGIC;
C_GEN1_ASSERT : STD_LOGIC;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER
);
PORT (
capturetrig0 : IN STD_LOGIC;
capturetrig1 : IN STD_LOGIC;
generateout0 : OUT STD_LOGIC;
generateout1 : OUT STD_LOGIC;
pwm0 : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
freeze : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT axi_timer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "axi_timer,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch : ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0,axi_timer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch: ARCHITECTURE IS "Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0,axi_timer,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_timer,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_COUNT_WIDTH=32,C_ONE_TIMER_ONLY=0,C_TRIG0_ASSERT=1,C_TRIG1_ASSERT=1,C_GEN0_ASSERT=1,C_GEN1_ASSERT=1,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ADDR_WIDTH=5}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
BEGIN
U0 : axi_timer
GENERIC MAP (
C_FAMILY => "zynq",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 5
)
PORT MAP (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
generateout0 => generateout0,
generateout1 => generateout1,
pwm0 => pwm0,
interrupt => interrupt,
freeze => freeze,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
END Test_AXI_Master_simple_v1_0_hw_1_axi_timer_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity spirom_wb8 is
Port(
-- bus signal naming according to Wishbone B4 spec
CLK_I: in std_logic;
STB_I: in std_logic;
ADR_I: in std_logic_vector(XLEN-1 downto 0);
DAT_O: out std_logic_vector(7 downto 0);
ACK_O: out std_logic;
-- SPI signal lines
I_spi_miso: in std_logic := '0';
O_spi_sel: out std_logic := '1';
O_spi_clk: out std_logic := '0';
O_spi_mosi: out std_logic := '0'
);
end spirom_wb8;
architecture Behavioral of spirom_wb8 is
signal tx_data, rx_data: std_logic_vector(7 downto 0) := X"00";
signal tx_start: boolean := false;
signal spi_busy: boolean := true;
begin
spimaster_instance: entity work.spimaster port map(
I_clk => CLK_I,
I_tx_data => tx_data,
I_tx_start => tx_start,
I_spi_miso => I_spi_miso,
O_spi_clk => O_spi_clk,
O_spi_mosi => O_spi_mosi,
O_rx_data => rx_data,
O_busy => spi_busy
);
process(CLK_I)
type ctrlstates is (IDLE, OPCODE, ADDR1, ADDR2, ADDR3, READ1, READ2, WAITSTATE, TX1, TX2);
variable state, retstate: ctrlstates := IDLE;
variable doack: std_logic := '0';
begin
if rising_edge(CLK_I) then
doack := '0';
O_spi_sel <= '0'; -- select device
case state is
when IDLE =>
O_spi_sel <= '1'; -- deselect device
if not spi_busy and STB_I = '1' then
state := OPCODE;
end if;
when OPCODE =>
tx_data <= X"03";
state := TX1;
retstate := ADDR1;
when ADDR1 =>
tx_data <= ADR_I(23 downto 16);
state := TX1;
retstate := ADDR2;
when ADDR2 =>
tx_data <= ADR_I(15 downto 8);
state := TX1;
retstate := ADDR3;
when ADDR3 =>
tx_data <= ADR_I(7 downto 0);
state := TX1;
retstate := READ1;
when READ1 =>
tx_data <= X"00";
state := TX1;
retstate := READ2;
when READ2 =>
doack := '1';
state := WAITSTATE;
when WAITSTATE =>
state := IDLE;
when TX1 =>
-- signal beginning of transmission
tx_start <= true;
-- wait for ack that transmission is in progress
if spi_busy then
state := TX2;
end if;
when TX2 =>
tx_start <= false;
-- wait until transmission has ended
if not spi_busy then
state := retstate;
end if;
end case;
end if;
DAT_O <= rx_data;
ACK_O <= doack and STB_I;
end process;
end Behavioral;
|
entity call2 is
end;
architecture behav of call2 is
procedure p (n : natural) is
begin
for i in 1 to n loop
report "hello";
wait for 1 ns;
end loop;
end p;
begin
process
begin
p (5);
report "SUCCESS";
wait;
end process;
end behav;
|
entity call2 is
end;
architecture behav of call2 is
procedure p (n : natural) is
begin
for i in 1 to n loop
report "hello";
wait for 1 ns;
end loop;
end p;
begin
process
begin
p (5);
report "SUCCESS";
wait;
end process;
end behav;
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dsp_cmdregs is
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
op_done : in std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
offset_0 : out unsigned((cmdreg_width - 1) downto 0);
offset_1 : out unsigned((cmdreg_width - 1) downto 0);
offset_2 : out unsigned((cmdreg_width - 1) downto 0);
length0 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length1 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length2 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : out std_logic_vector((opflag_width - 1) downto 0);
opcode_select : out std_logic_vector((opcode_width - 1) downto 0);
irq : out std_logic;
debug : out std_logic_vector(15 downto 0)
);
end dsp_cmdregs;
--=----------------------------------------------------------------------------
architecture archi_dsp_cmdregs of dsp_cmdregs is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_refresh_cmdreg_length : integer := 10;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dsp_cmdpipe
port (
reset : in std_logic;
clk : in std_logic;
cmd_out : out t_dsp_cmdregs;
read : in std_logic;
empty : out std_logic;
cmd_in : in t_dsp_cmdregs;
write : in std_logic;
full : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_cmdregs : t_dsp_cmdregs;
signal s_dsp_cmdregs_buf : t_dsp_cmdregs;
signal s_dsp_cmdpipe_out : t_dsp_cmdregs;
signal s_dsp_bus : t_dsp_bus;
signal s_dsp_bus_conv_circ : t_dsp_bus;
signal s_op_conv_circ_en : std_logic;
signal s_opflag_select_inreg : std_logic_vector((opflag_width - 1) downto 0);
signal s_opcode_select_inreg : std_logic_vector((opcode_width - 1) downto 0);
signal s_op_run_resync : std_logic;
signal s_op_run_sync : std_logic;
signal s_op_done_sync : std_logic;
signal s_op_done_resync : std_logic;
signal s_lut_out : std_logic_vector((lut_out_width - 1) downto 0);
signal s_load_pipe : std_logic;
signal s_status_reg : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_read : std_logic;
signal s_empty : std_logic;
signal s_write : std_logic;
signal s_full : std_logic;
signal s_run_flag : std_logic;
signal s_pipe_loaded : std_logic;
signal s_op_run : std_logic;
signal s_op_done_irq : std_logic;
signal s_empty_irq : std_logic;
signal s_current_sr : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_empty_reg : std_logic;
signal s_op_done_reg : std_logic;
signal s_empty_ie : std_logic;
signal s_op_done_ie : std_logic;
begin -- archs_dsp_cmdregs
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dsp_cmdpipe_1 : dsp_cmdpipe
port map (
reset => reset,
clk => clk_cpu,
cmd_out => s_dsp_cmdpipe_out,
read => s_read,
empty => s_empty,
cmd_in => s_dsp_cmdregs_buf,
write => s_write,
full => s_full);
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Register bank accessible from controler
-------------------------------------------------------------------------------
p_cmdreg_buf : process (clk_cpu, reset)
begin -- process p_cmdreg_buf
if reset = '0' then
s_dsp_cmdregs_buf <= dsp_cmdregs_init;
elsif rising_edge(clk_cpu) then -- rising clock edge
if(wr_en_cmdreg = '1') then
s_dsp_cmdregs_buf(conv_integer(addr_cmdreg)) <= data_in_cmdreg;
else
s_dsp_cmdregs_buf(DSPADDR_SR) <= s_status_reg;
end if;
data_out_cmdreg <= s_dsp_cmdregs_buf(conv_integer(addr_cmdreg));
end if;
end process p_cmdreg_buf;
-------------------------------------------------------------------------------
-- Bits of status register (readable from cpu)
-------------------------------------------------------------------------------
s_status_reg(DSP_SRBIT_LOADED) <= s_full;
s_status_reg(DSP_SRBIT_DONE) <= s_op_done_resync;
s_status_reg(DSP_SRBIT_RUN) <= s_run_flag and (not s_load_pipe);
s_run_flag <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_RUN);
s_status_reg(DSP_SRBIT_DONE_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IE);
s_status_reg(DSP_SRBIT_EMPTY_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IE);
s_status_reg(DSP_SRBIT_DONE_IF) <= s_op_done_irq;
s_status_reg(DSP_SRBIT_EMPTY_IF) <= s_empty_irq;
s_status_reg(cmdreg_width - 1 downto DSP_SRBIT_UNUSED) <= (others => '0');
s_op_done_irq <= '1' when op_done = '1' and s_op_done_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IF);
s_empty_irq <= '1' when s_empty = '1' and s_empty_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IF);
s_empty_ie <= s_status_reg(DSP_SRBIT_EMPTY_IE);
s_op_done_ie <= s_current_sr(DSP_SRBIT_DONE_IE);
irq <= (s_empty and s_empty_ie) or (op_done and s_op_done_ie);
p_irq : process (clk_cpu)
begin -- process p_irq
if rising_edge(clk_cpu) then -- rising clock edge
s_op_done_reg <= op_done;
s_empty_reg <= s_empty;
end if;
end process p_irq;
-------------------------------------------------------------------------------
-- Control injection of datas in pipe
-------------------------------------------------------------------------------
p_ctrl_pipe : process (clk_cpu)
begin -- process p_cmdreg_buf
if rising_edge(clk_cpu) then -- rising clock edge
if s_load_pipe = '1' then
s_write <= '1';
s_pipe_loaded <= '1';
elsif s_run_flag = '0' then
s_pipe_loaded <= '0';
s_write <= '0';
else
s_write <= '0';
end if;
end if;
end process p_ctrl_pipe;
s_load_pipe <= s_run_flag and (not s_pipe_loaded) and (not s_full);
-------------------------------------------------------------------------------
-- Control the pipe output
-------------------------------------------------------------------------------
p_pipe_out : process (clk_cpu, reset)
begin -- process p_pipe_out
if reset = '0' then
s_op_run <= '0';
elsif rising_edge(clk_cpu) then -- rising clock edge
if s_op_done_resync = '1' then
s_op_run <= '0';
s_read <= '0';
elsif s_op_run = '0' and s_empty = '0' then
s_read <= '1';
s_op_run <= '1';
s_dsp_cmdregs <= s_dsp_cmdpipe_out;
else
s_read <= '0';
end if;
s_op_done_sync <= op_done;
s_op_done_resync <= s_op_done_sync;
end if;
end process p_pipe_out;
-------------------------------------------------------------------------------
-- Synchronization of command signals to the dspunit clock
-------------------------------------------------------------------------------
p_synccmd : process (clk)
begin -- process p_synccmd
if rising_edge(clk) then -- rising clock edge
s_op_run_sync <= s_op_run;
s_op_run_resync <= s_op_run_sync;
-- cmdregs can be considered as stable when s_op_run_resync='1'
if s_op_run_resync = '1' then
s_opcode_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opcode_width - 1) downto 0);
s_opflag_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opflag_width + opcode_width - 1) downto (opcode_width));
else
s_opcode_select_inreg <= (others => '0');
s_opflag_select_inreg <= (others => '0');
end if;
opcode_select <= s_opcode_select_inreg;
opflag_select <= s_opflag_select_inreg;
offset_0 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR0));
offset_1 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR1));
offset_2 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR2));
length0 <= s_dsp_cmdregs(DSPADDR_LENGTH0);
length1 <= s_dsp_cmdregs(DSPADDR_LENGTH1);
length2 <= s_dsp_cmdregs(DSPADDR_LENGTH2);
end if;
end process p_synccmd;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
debug <= s_dsp_cmdregs(DSPADDR_SR);
s_current_sr <= s_dsp_cmdregs(DSPADDR_SR);
end archi_dsp_cmdregs;
-------------------------------------------------------------------------------
|
-- ----------------------------------------------------------------------
-- DspUnit : Advanced So(P)C Sequential Signal Processor
-- Copyright (C) 2007-2010 by Adrien LELONG (www.lelongdunet.com)
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the
-- Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-- ----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.dspalu_pac.all;
use work.dspunit_pac.all;
-------------------------------------------------------------------------------
entity dsp_cmdregs is
port (
clk : in std_logic;
clk_cpu : in std_logic;
reset : in std_logic;
op_done : in std_logic;
addr_cmdreg : in std_logic_vector((cmdreg_addr_width - 1) downto 0);
data_in_cmdreg : in std_logic_vector((cmdreg_data_width - 1) downto 0);
wr_en_cmdreg : in std_logic;
data_out_cmdreg : out std_logic_vector((cmdreg_data_width - 1) downto 0);
offset_0 : out unsigned((cmdreg_width - 1) downto 0);
offset_1 : out unsigned((cmdreg_width - 1) downto 0);
offset_2 : out unsigned((cmdreg_width - 1) downto 0);
length0 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length1 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
length2 : out std_logic_vector((cmdreg_data_width - 1) downto 0);
opflag_select : out std_logic_vector((opflag_width - 1) downto 0);
opcode_select : out std_logic_vector((opcode_width - 1) downto 0);
irq : out std_logic;
debug : out std_logic_vector(15 downto 0)
);
end dsp_cmdregs;
--=----------------------------------------------------------------------------
architecture archi_dsp_cmdregs of dsp_cmdregs is
-----------------------------------------------------------------------------
-- @constants definition
-----------------------------------------------------------------------------
constant c_refresh_cmdreg_length : integer := 10;
--=--------------------------------------------------------------------------
--
-- @component declarations
--
-----------------------------------------------------------------------------
component dsp_cmdpipe
port (
reset : in std_logic;
clk : in std_logic;
cmd_out : out t_dsp_cmdregs;
read : in std_logic;
empty : out std_logic;
cmd_in : in t_dsp_cmdregs;
write : in std_logic;
full : out std_logic
);
end component;
--=--------------------------------------------------------------------------
-- @signals definition
-----------------------------------------------------------------------------
signal s_dsp_cmdregs : t_dsp_cmdregs;
signal s_dsp_cmdregs_buf : t_dsp_cmdregs;
signal s_dsp_cmdpipe_out : t_dsp_cmdregs;
signal s_dsp_bus : t_dsp_bus;
signal s_dsp_bus_conv_circ : t_dsp_bus;
signal s_op_conv_circ_en : std_logic;
signal s_opflag_select_inreg : std_logic_vector((opflag_width - 1) downto 0);
signal s_opcode_select_inreg : std_logic_vector((opcode_width - 1) downto 0);
signal s_op_run_resync : std_logic;
signal s_op_run_sync : std_logic;
signal s_op_done_sync : std_logic;
signal s_op_done_resync : std_logic;
signal s_lut_out : std_logic_vector((lut_out_width - 1) downto 0);
signal s_load_pipe : std_logic;
signal s_status_reg : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_read : std_logic;
signal s_empty : std_logic;
signal s_write : std_logic;
signal s_full : std_logic;
signal s_run_flag : std_logic;
signal s_pipe_loaded : std_logic;
signal s_op_run : std_logic;
signal s_op_done_irq : std_logic;
signal s_empty_irq : std_logic;
signal s_current_sr : std_logic_vector((cmdreg_width - 1) downto 0);
signal s_empty_reg : std_logic;
signal s_op_done_reg : std_logic;
signal s_empty_ie : std_logic;
signal s_op_done_ie : std_logic;
begin -- archs_dsp_cmdregs
-----------------------------------------------------------------------------
--
-- @instantiations
--
-----------------------------------------------------------------------------
dsp_cmdpipe_1 : dsp_cmdpipe
port map (
reset => reset,
clk => clk_cpu,
cmd_out => s_dsp_cmdpipe_out,
read => s_read,
empty => s_empty,
cmd_in => s_dsp_cmdregs_buf,
write => s_write,
full => s_full);
--=---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Register bank accessible from controler
-------------------------------------------------------------------------------
p_cmdreg_buf : process (clk_cpu, reset)
begin -- process p_cmdreg_buf
if reset = '0' then
s_dsp_cmdregs_buf <= dsp_cmdregs_init;
elsif rising_edge(clk_cpu) then -- rising clock edge
if(wr_en_cmdreg = '1') then
s_dsp_cmdregs_buf(conv_integer(addr_cmdreg)) <= data_in_cmdreg;
else
s_dsp_cmdregs_buf(DSPADDR_SR) <= s_status_reg;
end if;
data_out_cmdreg <= s_dsp_cmdregs_buf(conv_integer(addr_cmdreg));
end if;
end process p_cmdreg_buf;
-------------------------------------------------------------------------------
-- Bits of status register (readable from cpu)
-------------------------------------------------------------------------------
s_status_reg(DSP_SRBIT_LOADED) <= s_full;
s_status_reg(DSP_SRBIT_DONE) <= s_op_done_resync;
s_status_reg(DSP_SRBIT_RUN) <= s_run_flag and (not s_load_pipe);
s_run_flag <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_RUN);
s_status_reg(DSP_SRBIT_DONE_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IE);
s_status_reg(DSP_SRBIT_EMPTY_IE) <= s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IE);
s_status_reg(DSP_SRBIT_DONE_IF) <= s_op_done_irq;
s_status_reg(DSP_SRBIT_EMPTY_IF) <= s_empty_irq;
s_status_reg(cmdreg_width - 1 downto DSP_SRBIT_UNUSED) <= (others => '0');
s_op_done_irq <= '1' when op_done = '1' and s_op_done_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_DONE_IF);
s_empty_irq <= '1' when s_empty = '1' and s_empty_reg = '0' else s_dsp_cmdregs_buf(DSPADDR_SR)(DSP_SRBIT_EMPTY_IF);
s_empty_ie <= s_status_reg(DSP_SRBIT_EMPTY_IE);
s_op_done_ie <= s_current_sr(DSP_SRBIT_DONE_IE);
irq <= (s_empty and s_empty_ie) or (op_done and s_op_done_ie);
p_irq : process (clk_cpu)
begin -- process p_irq
if rising_edge(clk_cpu) then -- rising clock edge
s_op_done_reg <= op_done;
s_empty_reg <= s_empty;
end if;
end process p_irq;
-------------------------------------------------------------------------------
-- Control injection of datas in pipe
-------------------------------------------------------------------------------
p_ctrl_pipe : process (clk_cpu)
begin -- process p_cmdreg_buf
if rising_edge(clk_cpu) then -- rising clock edge
if s_load_pipe = '1' then
s_write <= '1';
s_pipe_loaded <= '1';
elsif s_run_flag = '0' then
s_pipe_loaded <= '0';
s_write <= '0';
else
s_write <= '0';
end if;
end if;
end process p_ctrl_pipe;
s_load_pipe <= s_run_flag and (not s_pipe_loaded) and (not s_full);
-------------------------------------------------------------------------------
-- Control the pipe output
-------------------------------------------------------------------------------
p_pipe_out : process (clk_cpu, reset)
begin -- process p_pipe_out
if reset = '0' then
s_op_run <= '0';
elsif rising_edge(clk_cpu) then -- rising clock edge
if s_op_done_resync = '1' then
s_op_run <= '0';
s_read <= '0';
elsif s_op_run = '0' and s_empty = '0' then
s_read <= '1';
s_op_run <= '1';
s_dsp_cmdregs <= s_dsp_cmdpipe_out;
else
s_read <= '0';
end if;
s_op_done_sync <= op_done;
s_op_done_resync <= s_op_done_sync;
end if;
end process p_pipe_out;
-------------------------------------------------------------------------------
-- Synchronization of command signals to the dspunit clock
-------------------------------------------------------------------------------
p_synccmd : process (clk)
begin -- process p_synccmd
if rising_edge(clk) then -- rising clock edge
s_op_run_sync <= s_op_run;
s_op_run_resync <= s_op_run_sync;
-- cmdregs can be considered as stable when s_op_run_resync='1'
if s_op_run_resync = '1' then
s_opcode_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opcode_width - 1) downto 0);
s_opflag_select_inreg <= s_dsp_cmdregs(DSPADDR_OPCODE)((opflag_width + opcode_width - 1) downto (opcode_width));
else
s_opcode_select_inreg <= (others => '0');
s_opflag_select_inreg <= (others => '0');
end if;
opcode_select <= s_opcode_select_inreg;
opflag_select <= s_opflag_select_inreg;
offset_0 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR0));
offset_1 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR1));
offset_2 <= unsigned(s_dsp_cmdregs(DSPADDR_STARTADDR2));
length0 <= s_dsp_cmdregs(DSPADDR_LENGTH0);
length1 <= s_dsp_cmdregs(DSPADDR_LENGTH1);
length2 <= s_dsp_cmdregs(DSPADDR_LENGTH2);
end if;
end process p_synccmd;
--=---------------------------------------------------------------------------
--
-- @concurrent signal assignments
--
-----------------------------------------------------------------------------
debug <= s_dsp_cmdregs(DSPADDR_SR);
s_current_sr <= s_dsp_cmdregs(DSPADDR_SR);
end archi_dsp_cmdregs;
-------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:02:49 07/24/2015
-- Design Name:
-- Module Name: fetch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fetch is
Port ( irnew : in STD_LOGIC_VECTOR (15 downto 0); --·Ã´æÄ£¿éÊäÈëµÄIR
pcnew : in STD_LOGIC_VECTOR (15 downto 0); --?Øдģ¿?£¬?üÐÂPC
clk : in STD_LOGIC; --½ÚÅÄ
pcupdate : in STD_LOGIC; --¸æËßÒª¸üÐÂPCÁË
reset : in STD_LOGIC; --¸´Î»
t0 : in STD_LOGIC;
t1 : in STD_LOGIC;
irout : out STD_LOGIC_VECTOR (15 downto 0); --Êä³öµÄIR
pcout : out STD_LOGIC_VECTOR (15 downto 0);
irrep : out STD_LOGIC); --ʹÄÜ
end fetch;
architecture Behavioral of fetch is
signal pc : STD_LOGIC_VECTOR (15 downto 0);
begin
-- process(clk, reset, t0, t1, pcupdate)
-- begin
-- if reset = '1' then
-- irrep <= '0';
-- pc <= "0000000000000000";
-- elsif t0 = '1' then
-- irrep <= '1';
-- irout <= irnew;
-- elsif t1 = '1' then
-- irrep <= '0';
-- if (clk = '1' and clk' event) then
-- pc <= pc + 1;
-- end if;
-- elsif pcupdate = '1' then
-- pc <= pcnew;
-- irrep <= '0';
--
-- end if;
-- pcout <= pc;
-- end process;
process(clk, reset, pcupdate, t1, t0)
begin
if reset = '1' then
pc <= "0000000000000000";
elsif pcupdate = '1' then
pc <= pcnew;
elsif t1 = '1' and clk = '1' and clk' event then
pc <= pc + 1;
end if;
pcout <= pc;
end process;
process(clk, t0, t1)
begin
if t0 = '1' then
irrep <= '1';
irout <= irnew;
elsif t1 <= '1' then
irrep <= '0';
end if;
end process;
end Behavioral;
|
-- test_ng.vhd
library ieee;
use ieee.std_logic_1164.all;
entity SAMPLE is
generic (
WORD_BITS : integer := 8;
STRB_BITS : integer := 1;
O_WIDTH : integer := 1;
QUEUE_SIZE : integer := 3
);
port (
CLK : in std_logic;
RST : in std_logic;
O_DATA : out std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0);
O_STRB : out std_logic_vector(O_WIDTH*STRB_BITS-1 downto 0);
O_VAL : out std_logic;
O_RDY : in std_logic
);
end entity;
architecture RTL of SAMPLE is
type WORD_TYPE is record
DATA : std_logic_vector(WORD_BITS-1 downto 0);
STRB : std_logic_vector(STRB_BITS-1 downto 0);
VAL : boolean;
end record;
constant WORD_NULL : WORD_TYPE := (DATA => (others => '0'),
STRB => (others => '0'),
VAL => FALSE);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
signal curr_queue : WORD_VECTOR(0 to QUEUE_SIZE-1);
begin
curr_queue <= (others => WORD_NULL);
process (curr_queue) begin
for i in 0 to O_WIDTH-1 loop
O_DATA((i+1)*WORD_BITS-1 downto i*WORD_BITS) <= curr_queue(i).DATA;
O_STRB((i+1)*STRB_BITS-1 downto i*STRB_BITS) <= curr_queue(i).STRB;
end loop;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
entity issue434 is
end entity;
architecture MODEL of issue434 is
constant PERIOD : time := 10 ns;
constant DELAY : time := 1 ns;
constant WORD_BITS : integer := 8;
constant STRB_BITS : integer := WORD_BITS/8;
constant O_WIDTH : integer := 2;
constant QUEUE_SIZE : integer := 4;
signal CLK_ENA : std_logic;
signal CLK : std_logic;
signal RST : std_logic;
signal O_DATA : std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0);
signal O_STRB : std_logic_vector(O_WIDTH*STRB_BITS-1 downto 0);
signal O_VAL : std_logic;
signal O_RDY : std_logic;
begin
DUT: entity WORK.SAMPLE
generic map (
WORD_BITS => WORD_BITS ,
STRB_BITS => STRB_BITS ,
O_WIDTH => O_WIDTH ,
QUEUE_SIZE => QUEUE_SIZE
)
port map(
CLK => CLK ,
RST => RST ,
O_DATA => O_DATA ,
O_STRB => O_STRB ,
O_VAL => O_VAL ,
O_RDY => O_RDY
);
process begin
loop
CLK <= '1'; wait for PERIOD/2;
CLK <= '0'; wait for PERIOD/2;
exit when(CLK_ENA = '0');
end loop;
CLK <= '0';
wait;
end process;
process
procedure WAIT_CLK(CNT:integer) is
begin
if (CNT > 0) then
for i in 1 to CNT loop
wait until (CLK'event and CLK = '1');
end loop;
end if;
wait for DELAY;
end WAIT_CLK;
begin
CLK_ENA <= '1';
RST <= '1';
O_RDY <= '0';
WAIT_CLK(1);
RST <= '0';
WAIT_CLK(10);
CLK_ENA <= '0';
assert o_data = X"0000";
wait;
end process;
end MODEL;
|
--************************************************************************************************
-- External multeplexer for AVR core
-- Version 2.2
-- Designed by Ruslan Lepetenok 05.11.2001
-- Modified 29.08.2003
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity external_mux is port(
ramre : in std_logic;
dbus_out : out std_logic_vector(7 downto 0);
ram_data_out : in std_logic_vector(7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end external_mux;
architecture RTL of external_mux is
signal ext_mux_out : ext_mux_din_type;
begin
ext_mux_out(0) <= io_port_bus(0) when io_port_en_bus(0)='1' else (others => '0');
data_mux_for_read:for i in 1 to ext_mux_out'high generate
ext_mux_out(i) <= io_port_bus(i) when io_port_en_bus(i)='1' else ext_mux_out(i-1);
end generate;
dbus_out <= ram_data_out when ramre='1' else ext_mux_out(ext_mux_out'high);
interrupt_ack:for i in ind_irq_ack'range generate
ind_irq_ack(i) <= '1' when (irqackad=i+1 and irqack='1') else '0';
end generate;
end RTL;
|
--************************************************************************************************
-- External multeplexer for AVR core
-- Version 2.2
-- Designed by Ruslan Lepetenok 05.11.2001
-- Modified 29.08.2003
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity external_mux is port(
ramre : in std_logic;
dbus_out : out std_logic_vector(7 downto 0);
ram_data_out : in std_logic_vector(7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end external_mux;
architecture RTL of external_mux is
signal ext_mux_out : ext_mux_din_type;
begin
ext_mux_out(0) <= io_port_bus(0) when io_port_en_bus(0)='1' else (others => '0');
data_mux_for_read:for i in 1 to ext_mux_out'high generate
ext_mux_out(i) <= io_port_bus(i) when io_port_en_bus(i)='1' else ext_mux_out(i-1);
end generate;
dbus_out <= ram_data_out when ramre='1' else ext_mux_out(ext_mux_out'high);
interrupt_ack:for i in ind_irq_ack'range generate
ind_irq_ack(i) <= '1' when (irqackad=i+1 and irqack='1') else '0';
end generate;
end RTL;
|
--************************************************************************************************
-- External multeplexer for AVR core
-- Version 2.2
-- Designed by Ruslan Lepetenok 05.11.2001
-- Modified 29.08.2003
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity external_mux is port(
ramre : in std_logic;
dbus_out : out std_logic_vector(7 downto 0);
ram_data_out : in std_logic_vector(7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end external_mux;
architecture RTL of external_mux is
signal ext_mux_out : ext_mux_din_type;
begin
ext_mux_out(0) <= io_port_bus(0) when io_port_en_bus(0)='1' else (others => '0');
data_mux_for_read:for i in 1 to ext_mux_out'high generate
ext_mux_out(i) <= io_port_bus(i) when io_port_en_bus(i)='1' else ext_mux_out(i-1);
end generate;
dbus_out <= ram_data_out when ramre='1' else ext_mux_out(ext_mux_out'high);
interrupt_ack:for i in ind_irq_ack'range generate
ind_irq_ack(i) <= '1' when (irqackad=i+1 and irqack='1') else '0';
end generate;
end RTL;
|
--************************************************************************************************
-- External multeplexer for AVR core
-- Version 2.2
-- Designed by Ruslan Lepetenok 05.11.2001
-- Modified 29.08.2003
--************************************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use WORK.AVRuCPackage.all;
entity external_mux is port(
ramre : in std_logic;
dbus_out : out std_logic_vector(7 downto 0);
ram_data_out : in std_logic_vector(7 downto 0);
io_port_bus : in ext_mux_din_type;
io_port_en_bus : in ext_mux_en_type;
irqack : in std_logic;
irqackad : in std_logic_vector(4 downto 0);
ind_irq_ack : out std_logic_vector(22 downto 0)
);
end external_mux;
architecture RTL of external_mux is
signal ext_mux_out : ext_mux_din_type;
begin
ext_mux_out(0) <= io_port_bus(0) when io_port_en_bus(0)='1' else (others => '0');
data_mux_for_read:for i in 1 to ext_mux_out'high generate
ext_mux_out(i) <= io_port_bus(i) when io_port_en_bus(i)='1' else ext_mux_out(i-1);
end generate;
dbus_out <= ram_data_out when ramre='1' else ext_mux_out(ext_mux_out'high);
interrupt_ack:for i in ind_irq_ack'range generate
ind_irq_ack(i) <= '1' when (irqackad=i+1 and irqack='1') else '0';
end generate;
end RTL;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1_block1.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block1
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block1 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_11_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_11_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_5_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_5_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_6_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_5_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block1;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block1 IS
-- Signals
SIGNAL twdlXdin_3_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_3_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_11_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_11_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_5_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_5_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_6_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_3_re_signed <= signed(twdlXdin_3_re);
twdlXdin_3_im_signed <= signed(twdlXdin_3_im);
twdlXdin_11_re_signed <= signed(twdlXdin_11_re);
twdlXdin_11_im_signed <= signed(twdlXdin_11_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_3_re_signed,
twdlXdin_3_im_signed, twdlXdin_11_re_signed, twdlXdin_11_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_3_re_signed, 18) + resize(twdlXdin_11_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_3_re_signed, 18) - resize(twdlXdin_11_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_3_im_signed, 18) + resize(twdlXdin_11_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_3_im_signed, 18) - resize(twdlXdin_11_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_5_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_5_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_6_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_6_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_5_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_5_re <= std_logic_vector(dout_5_re_tmp);
dout_5_im <= std_logic_vector(dout_5_im_tmp);
dout_6_re <= std_logic_vector(dout_6_re_tmp);
dout_6_im <= std_logic_vector(dout_6_im_tmp);
END rtl;
|
entity driving is
port ( i : in integer;
o : out integer );
end entity;
architecture test of driving is
signal x : integer;
begin
p1: process is
variable v : integer;
begin
x <= 1;
assert x'driving; -- OK
assert v'driving; -- Error
assert o'driving; -- OK
assert i'driving; -- Error
wait;
end process;
end architecture;
|
-- $Id: pdp11_tmu_sb.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2018 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
-- Description: pdp11: trace and monitor unit; simbus wrapper
--
-- Dependencies: simbus
-- Test bench: -
-- Tool versions: xst 8.1-14.7; viv 2016.2-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-05 1053 1.0.2 use DM_STAT_CA instead of DM_STAT_SY
-- 2015-11-01 712 1.0.1 use sbcntl_sbf_tmu
-- 2009-05-10 214 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.pdp11.all;
entity pdp11_tmu_sb is -- trace and mon. unit; simbus wrapper
generic (
ENAPIN : integer := sbcntl_sbf_tmu); -- SB_CNTL for tmu
port (
CLK : in slbit; -- clock
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - dpath
DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
DM_STAT_CO : in dm_stat_co_type; -- debug and monitor status - core
DM_STAT_CA : in dm_stat_ca_type -- debug and monitor status - cache
);
end pdp11_tmu_sb;
architecture sim of pdp11_tmu_sb is
signal ENA : slbit := '0';
begin
assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
report "assert(ENAPIN in SB_CNTL'range)" severity failure;
ENA <= to_x01(SB_CNTL(ENAPIN));
CPMON : pdp11_tmu
port map (
CLK => CLK,
ENA => ENA,
DM_STAT_DP => DM_STAT_DP,
DM_STAT_VM => DM_STAT_VM,
DM_STAT_CO => DM_STAT_CO,
DM_STAT_CA => DM_STAT_CA
);
end sim;
|
-------------------------------------------------------------------------------
-- $Id: pselect.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
|
architecture RTL of FIFO is
begin
process
begin
end process;
-- Violations below
process
begin
END process;
end architecture RTL;
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version, wrapper wirh memory ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu (Behave) (Entity and architecture) ----
---- File name: zpu.vhd ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu is
generic(
g_addr_size : integer := 16;
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unused bits, can be '-' or '0'
port(
clock : in std_logic;
reset : in std_logic;
interrupt_i : in std_logic;
break_o : out std_logic;
mem_address : out std_logic_vector(g_addr_size-1 downto 0);
mem_size : out std_logic_vector(1 downto 0);
mem_instr : out std_logic;
mem_req : out std_logic;
mem_write : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_wdata : out std_logic_vector(7 downto 0);
mem_rdata : in std_logic_vector(7 downto 0) );
end zpu;
architecture gideon of zpu is
signal a_we : std_logic; -- BRAM A port Write Enable
signal a_en : std_logic; -- BRAM A port Enable
signal a_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
signal a_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata : unsigned(31 downto 0); -- Data from BRAM A port
signal a_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM A port
signal b_we : std_logic; -- BRAM B port Write Enable
signal b_en : std_logic; -- BRAM B port Enable
signal b_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
signal b_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata : unsigned(31 downto 0); -- Data from BRAM B port
signal b_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM B port
signal c_addr : unsigned(g_addr_size-1 downto 0);
begin
cpu: entity work.zpu_8bit_loadb
generic map (
g_addr_size => g_addr_size,
g_stack_size => g_stack_size,
g_prog_size => g_prog_size,
g_dont_care => g_dont_care )
port map (
clk_i => clock,
reset_i => reset,
interrupt_i => interrupt_i,
break_o => break_o,
-- synthesis translate_off
dbg_o => open,
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o => a_we,
a_en_o => a_en,
a_addr_o => a_addr,
a_o => a_wdata,
a_i => a_rdata,
b_we_o => b_we,
b_en_o => b_en,
b_addr_o => b_addr,
b_o => b_wdata,
b_i => b_rdata,
-- memory port for text, bss, data
c_addr_o => c_addr,
c_size_o => mem_size,
c_inst_o => mem_instr,
c_req_o => mem_req,
c_rack_i => mem_rack,
c_dack_i => mem_dack,
c_we_o => mem_write,
c_data_o => mem_wdata,
c_data_i => mem_rdata );
mem_address <= std_logic_vector(c_addr);
a_wdata_slv <= std_logic_vector(a_wdata);
b_wdata_slv <= std_logic_vector(b_wdata);
a_rdata <= unsigned(a_rdata_slv);
b_rdata <= unsigned(b_rdata_slv);
i_stack_ram: entity work.dpram
generic map (
g_width_bits => 32,
g_depth_bits => g_stack_size-2,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => a_addr,
a_rdata => a_rdata_slv,
a_wdata => a_wdata_slv,
a_en => a_en,
a_we => a_we,
b_clock => clock,
b_address => b_addr,
b_rdata => b_rdata_slv,
b_wdata => b_wdata_slv,
b_en => b_en,
b_we => b_we );
end gideon;
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version, wrapper wirh memory ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu (Behave) (Entity and architecture) ----
---- File name: zpu.vhd ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu is
generic(
g_addr_size : integer := 16;
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unused bits, can be '-' or '0'
port(
clock : in std_logic;
reset : in std_logic;
interrupt_i : in std_logic;
break_o : out std_logic;
mem_address : out std_logic_vector(g_addr_size-1 downto 0);
mem_size : out std_logic_vector(1 downto 0);
mem_instr : out std_logic;
mem_req : out std_logic;
mem_write : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_wdata : out std_logic_vector(7 downto 0);
mem_rdata : in std_logic_vector(7 downto 0) );
end zpu;
architecture gideon of zpu is
signal a_we : std_logic; -- BRAM A port Write Enable
signal a_en : std_logic; -- BRAM A port Enable
signal a_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
signal a_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata : unsigned(31 downto 0); -- Data from BRAM A port
signal a_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM A port
signal b_we : std_logic; -- BRAM B port Write Enable
signal b_en : std_logic; -- BRAM B port Enable
signal b_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
signal b_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata : unsigned(31 downto 0); -- Data from BRAM B port
signal b_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM B port
signal c_addr : unsigned(g_addr_size-1 downto 0);
begin
cpu: entity work.zpu_8bit_loadb
generic map (
g_addr_size => g_addr_size,
g_stack_size => g_stack_size,
g_prog_size => g_prog_size,
g_dont_care => g_dont_care )
port map (
clk_i => clock,
reset_i => reset,
interrupt_i => interrupt_i,
break_o => break_o,
-- synthesis translate_off
dbg_o => open,
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o => a_we,
a_en_o => a_en,
a_addr_o => a_addr,
a_o => a_wdata,
a_i => a_rdata,
b_we_o => b_we,
b_en_o => b_en,
b_addr_o => b_addr,
b_o => b_wdata,
b_i => b_rdata,
-- memory port for text, bss, data
c_addr_o => c_addr,
c_size_o => mem_size,
c_inst_o => mem_instr,
c_req_o => mem_req,
c_rack_i => mem_rack,
c_dack_i => mem_dack,
c_we_o => mem_write,
c_data_o => mem_wdata,
c_data_i => mem_rdata );
mem_address <= std_logic_vector(c_addr);
a_wdata_slv <= std_logic_vector(a_wdata);
b_wdata_slv <= std_logic_vector(b_wdata);
a_rdata <= unsigned(a_rdata_slv);
b_rdata <= unsigned(b_rdata_slv);
i_stack_ram: entity work.dpram
generic map (
g_width_bits => 32,
g_depth_bits => g_stack_size-2,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => a_addr,
a_rdata => a_rdata_slv,
a_wdata => a_wdata_slv,
a_en => a_en,
a_we => a_we,
b_clock => clock,
b_address => b_addr,
b_rdata => b_rdata_slv,
b_wdata => b_wdata_slv,
b_en => b_en,
b_we => b_we );
end gideon;
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version, wrapper wirh memory ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu (Behave) (Entity and architecture) ----
---- File name: zpu.vhd ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu is
generic(
g_addr_size : integer := 16;
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unused bits, can be '-' or '0'
port(
clock : in std_logic;
reset : in std_logic;
interrupt_i : in std_logic;
break_o : out std_logic;
mem_address : out std_logic_vector(g_addr_size-1 downto 0);
mem_size : out std_logic_vector(1 downto 0);
mem_instr : out std_logic;
mem_req : out std_logic;
mem_write : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_wdata : out std_logic_vector(7 downto 0);
mem_rdata : in std_logic_vector(7 downto 0) );
end zpu;
architecture gideon of zpu is
signal a_we : std_logic; -- BRAM A port Write Enable
signal a_en : std_logic; -- BRAM A port Enable
signal a_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
signal a_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata : unsigned(31 downto 0); -- Data from BRAM A port
signal a_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM A port
signal b_we : std_logic; -- BRAM B port Write Enable
signal b_en : std_logic; -- BRAM B port Enable
signal b_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
signal b_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata : unsigned(31 downto 0); -- Data from BRAM B port
signal b_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM B port
signal c_addr : unsigned(g_addr_size-1 downto 0);
begin
cpu: entity work.zpu_8bit_loadb
generic map (
g_addr_size => g_addr_size,
g_stack_size => g_stack_size,
g_prog_size => g_prog_size,
g_dont_care => g_dont_care )
port map (
clk_i => clock,
reset_i => reset,
interrupt_i => interrupt_i,
break_o => break_o,
-- synthesis translate_off
dbg_o => open,
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o => a_we,
a_en_o => a_en,
a_addr_o => a_addr,
a_o => a_wdata,
a_i => a_rdata,
b_we_o => b_we,
b_en_o => b_en,
b_addr_o => b_addr,
b_o => b_wdata,
b_i => b_rdata,
-- memory port for text, bss, data
c_addr_o => c_addr,
c_size_o => mem_size,
c_inst_o => mem_instr,
c_req_o => mem_req,
c_rack_i => mem_rack,
c_dack_i => mem_dack,
c_we_o => mem_write,
c_data_o => mem_wdata,
c_data_i => mem_rdata );
mem_address <= std_logic_vector(c_addr);
a_wdata_slv <= std_logic_vector(a_wdata);
b_wdata_slv <= std_logic_vector(b_wdata);
a_rdata <= unsigned(a_rdata_slv);
b_rdata <= unsigned(b_rdata_slv);
i_stack_ram: entity work.dpram
generic map (
g_width_bits => 32,
g_depth_bits => g_stack_size-2,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => a_addr,
a_rdata => a_rdata_slv,
a_wdata => a_wdata_slv,
a_en => a_en,
a_we => a_we,
b_clock => clock,
b_address => b_addr,
b_rdata => b_rdata_slv,
b_wdata => b_wdata_slv,
b_en => b_en,
b_we => b_we );
end gideon;
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version, wrapper wirh memory ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu (Behave) (Entity and architecture) ----
---- File name: zpu.vhd ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu is
generic(
g_addr_size : integer := 16;
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unused bits, can be '-' or '0'
port(
clock : in std_logic;
reset : in std_logic;
interrupt_i : in std_logic;
break_o : out std_logic;
mem_address : out std_logic_vector(g_addr_size-1 downto 0);
mem_size : out std_logic_vector(1 downto 0);
mem_instr : out std_logic;
mem_req : out std_logic;
mem_write : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_wdata : out std_logic_vector(7 downto 0);
mem_rdata : in std_logic_vector(7 downto 0) );
end zpu;
architecture gideon of zpu is
signal a_we : std_logic; -- BRAM A port Write Enable
signal a_en : std_logic; -- BRAM A port Enable
signal a_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
signal a_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata : unsigned(31 downto 0); -- Data from BRAM A port
signal a_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM A port
signal b_we : std_logic; -- BRAM B port Write Enable
signal b_en : std_logic; -- BRAM B port Enable
signal b_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
signal b_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata : unsigned(31 downto 0); -- Data from BRAM B port
signal b_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM B port
signal c_addr : unsigned(g_addr_size-1 downto 0);
begin
cpu: entity work.zpu_8bit_loadb
generic map (
g_addr_size => g_addr_size,
g_stack_size => g_stack_size,
g_prog_size => g_prog_size,
g_dont_care => g_dont_care )
port map (
clk_i => clock,
reset_i => reset,
interrupt_i => interrupt_i,
break_o => break_o,
-- synthesis translate_off
dbg_o => open,
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o => a_we,
a_en_o => a_en,
a_addr_o => a_addr,
a_o => a_wdata,
a_i => a_rdata,
b_we_o => b_we,
b_en_o => b_en,
b_addr_o => b_addr,
b_o => b_wdata,
b_i => b_rdata,
-- memory port for text, bss, data
c_addr_o => c_addr,
c_size_o => mem_size,
c_inst_o => mem_instr,
c_req_o => mem_req,
c_rack_i => mem_rack,
c_dack_i => mem_dack,
c_we_o => mem_write,
c_data_o => mem_wdata,
c_data_i => mem_rdata );
mem_address <= std_logic_vector(c_addr);
a_wdata_slv <= std_logic_vector(a_wdata);
b_wdata_slv <= std_logic_vector(b_wdata);
a_rdata <= unsigned(a_rdata_slv);
b_rdata <= unsigned(b_rdata_slv);
i_stack_ram: entity work.dpram
generic map (
g_width_bits => 32,
g_depth_bits => g_stack_size-2,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => a_addr,
a_rdata => a_rdata_slv,
a_wdata => a_wdata_slv,
a_en => a_en,
a_we => a_we,
b_clock => clock,
b_address => b_addr,
b_rdata => b_rdata_slv,
b_wdata => b_wdata_slv,
b_en => b_en,
b_we => b_we );
end gideon;
|
------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version, wrapper wirh memory ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu (Behave) (Entity and architecture) ----
---- File name: zpu.vhd ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu is
generic(
g_addr_size : integer := 16;
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unused bits, can be '-' or '0'
port(
clock : in std_logic;
reset : in std_logic;
interrupt_i : in std_logic;
break_o : out std_logic;
mem_address : out std_logic_vector(g_addr_size-1 downto 0);
mem_size : out std_logic_vector(1 downto 0);
mem_instr : out std_logic;
mem_req : out std_logic;
mem_write : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_wdata : out std_logic_vector(7 downto 0);
mem_rdata : in std_logic_vector(7 downto 0) );
end zpu;
architecture gideon of zpu is
signal a_we : std_logic; -- BRAM A port Write Enable
signal a_en : std_logic; -- BRAM A port Enable
signal a_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
signal a_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata : unsigned(31 downto 0); -- Data from BRAM A port
signal a_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM A port
signal a_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM A port
signal b_we : std_logic; -- BRAM B port Write Enable
signal b_en : std_logic; -- BRAM B port Enable
signal b_addr : unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
signal b_wdata : unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata : unsigned(31 downto 0); -- Data from BRAM B port
signal b_wdata_slv : std_logic_vector(31 downto 0):=(others => '0'); -- Data to BRAM B port
signal b_rdata_slv : std_logic_vector(31 downto 0); -- Data from BRAM B port
signal c_addr : unsigned(g_addr_size-1 downto 0);
begin
cpu: entity work.zpu_8bit_loadb
generic map (
g_addr_size => g_addr_size,
g_stack_size => g_stack_size,
g_prog_size => g_prog_size,
g_dont_care => g_dont_care )
port map (
clk_i => clock,
reset_i => reset,
interrupt_i => interrupt_i,
break_o => break_o,
-- synthesis translate_off
dbg_o => open,
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o => a_we,
a_en_o => a_en,
a_addr_o => a_addr,
a_o => a_wdata,
a_i => a_rdata,
b_we_o => b_we,
b_en_o => b_en,
b_addr_o => b_addr,
b_o => b_wdata,
b_i => b_rdata,
-- memory port for text, bss, data
c_addr_o => c_addr,
c_size_o => mem_size,
c_inst_o => mem_instr,
c_req_o => mem_req,
c_rack_i => mem_rack,
c_dack_i => mem_dack,
c_we_o => mem_write,
c_data_o => mem_wdata,
c_data_i => mem_rdata );
mem_address <= std_logic_vector(c_addr);
a_wdata_slv <= std_logic_vector(a_wdata);
b_wdata_slv <= std_logic_vector(b_wdata);
a_rdata <= unsigned(a_rdata_slv);
b_rdata <= unsigned(b_rdata_slv);
i_stack_ram: entity work.dpram
generic map (
g_width_bits => 32,
g_depth_bits => g_stack_size-2,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => a_addr,
a_rdata => a_rdata_slv,
a_wdata => a_wdata_slv,
a_en => a_en,
a_we => a_we,
b_clock => clock,
b_address => b_addr,
b_rdata => b_rdata_slv,
b_wdata => b_wdata_slv,
b_en => b_en,
b_we => b_we );
end gideon;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:54 12/01/2014
-- Design Name:
-- Module Name: befunge_pc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.STD_LOGIC_UNSIGNED;
--PC outputs x and y coordinates to read from grid
--dir input affects PC incrementing, it denotes the direction of execution in befunge_pc
--skip increments the pc twice to avoid a cell
--en, so that the operation of the pc can be clocked
entity befunge_pc is
generic(
grid_width : integer;
grid_height : integer
);
port(
clk : in std_logic;
reset : in std_logic;
pc_address : out integer range 0 to (grid_width*grid_height)-1;
dir : in std_logic_vector (1 downto 0);
skip : in std_logic;
en : in std_logic
);
end befunge_pc;
--dir:
--0 = right
--1 = down
--2 = left
--3 = up
architecture pc_v1 of befunge_pc is
signal pc_address_int : integer range 0 to (grid_width*grid_height)-1;
begin
pc_address <= pc_address_int;
process(reset,clk)
variable increment : integer range 1 to 2;
begin
if(reset = '1') then
pc_address_int <= 0;
increment := 1;
else
if rising_edge(clk) then
if ( en = '1' ) then
if ( skip = '1' ) then
increment := 2;
else
increment := 1;
end if;
if ( dir = "00" ) then --move right: add 1
pc_address_int <= pc_address_int + 1;
elsif ( dir = "01" ) then --move up: subtract grid_width
pc_address_int <= pc_address_int - 8;
elsif ( dir = "10" ) then --move left: subtract 1
pc_address_int <= pc_address_int - 1;
elsif (dir = "11") then --move down: add grid_width
pc_address_int <= pc_address_int + 8;
else --do nothing, laaaatchhh!!!!
pc_address_int <= pc_address_int;
end if;
end if;
end if;
end if;
end process;
end pc_v1;
architecture pc_v2 of befunge_pc is
signal pc_address_int : integer range 0 to (grid_width*grid_height)-1;
begin
pc_address <= pc_address_int;
process(reset,clk)
variable increment : integer range 1 to 2;
begin
if(reset = '1') then
pc_address_int <= 0;
increment := 1;
else
if rising_edge(clk) then
if ( en = '1' ) then
if ( skip = '1' ) then
increment := 2;
else
increment := 1;
end if;
if ( dir = "00" ) then --move right: add 1
pc_address_int <= pc_address_int + 1;
elsif ( dir = "01" ) then --move up: subtract grid_width
pc_address_int <= pc_address_int - 8;
elsif ( dir = "10" ) then --move left: subtract 1
pc_address_int <= pc_address_int - 1;
elsif (dir = "11") then --move down: add grid_width
pc_address_int <= pc_address_int + 8;
else --do nothing, laaaatchhh!!!!
pc_address_int <= pc_address_int;
end if;
end if;
end if;
end if;
end process;
end pc_v2;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc99.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n02i00099ent_a IS
END c04s03b02x00p29n02i00099ent_a;
ARCHITECTURE c04s03b02x00p29n02i00099arch_a OF c04s03b02x00p29n02i00099ent_a IS
PROCEDURE p1 ( prm_in : IN INTEGER ) IS
ATTRIBUTE attr1 : INTEGER;
ATTRIBUTE attr1 OF prm_in : constant IS 300;
BEGIN
ASSERT prm_in'attr1 = 300 REPORT "ERROR: Bad value for prm_in'attr1" SEVERITY FAILURE;
assert NOT(prm_in'attr1 = 300)
report "***PASSED TEST: c04s03b02x00p29n02i00099"
severity NOTE;
assert (prm_in'attr1 = 300)
report "***FAILED TEST: c04s03b02x00p29n02i00099 - Attribute reading in subprogram fail."
severity ERROR;
END;
BEGIN
PROCESS
BEGIN
--
p1 ( 0 );
--
wait;
END PROCESS;
END c04s03b02x00p29n02i00099arch_a;
ENTITY vests25 IS
END vests25;
ARCHITECTURE c04s03b02x00p29n02i00099arch OF vests25 IS
COMPONENT c04s03b02x00p29n02i00099ent_a
END COMPONENT;
FOR cmp1 : c04s03b02x00p29n02i00099ent_a USE ENTITY work.c04s03b02x00p29n02i00099ent_a(c04s03b02x00p29n02i00099arch_a);
SIGNAL s : INTEGER;
BEGIN
cmp1 : c04s03b02x00p29n02i00099ent_a;
END c04s03b02x00p29n02i00099arch;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package desilog is
subtype u8 is unsigned( 7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype u32 is unsigned(31 downto 0);
subtype u64 is unsigned(63 downto 0);
subtype u2 is unsigned( 1 downto 0);
subtype u4 is unsigned( 3 downto 0);
type string_ptr is access string;
--function str(a : unsigned) return string;
--function str(a : integer) return string;
function dg_boolToBit(bval : boolean) return std_ulogic;
end package;
package body desilog is
function dg_boolToBit(bval : boolean) return std_ulogic is begin
if bval then
return '1';
else
return '0';
end if;
end function;
end;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package desilog is
subtype u8 is unsigned( 7 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype u32 is unsigned(31 downto 0);
subtype u64 is unsigned(63 downto 0);
subtype u2 is unsigned( 1 downto 0);
subtype u4 is unsigned( 3 downto 0);
type string_ptr is access string;
--function str(a : unsigned) return string;
--function str(a : integer) return string;
function dg_boolToBit(bval : boolean) return std_ulogic;
end package;
package body desilog is
function dg_boolToBit(bval : boolean) return std_ulogic is begin
if bval then
return '1';
else
return '0';
end if;
end function;
end;
|
Subsets and Splits