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library IEEE;
use IEEE.std_logic_1164.all;
entity DrinksMachine is
port( CLOCK_50 : in std_logic;
SW : in std_logic_vector(2 downto 0);
KEY : in std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(0 downto 0));
end DrinksMachine;
architecture Shell of DrinksMachine is
signal clk50Mhz, s_clk : std_logic;
begin
clk50MHz <= CLOCK_50;
sw_debounce : entity WORK.DebounceUnit(Behavioral)
generic map(clkFrekHz => 50000,
blindmSec => 100,
inPol => '0',
outPol => '1')
port map(reset => SW(0),
refClk => clk50MHz,
dirtyIn => KEY(0),
pulsedOut => s_clk);
drink_core : entity work.DrinksFSM(Behavioral)
port map(C => SW(2),
V => SW(1),
reset => SW(0),
clk => s_clk,
drink => LEDG(0));
end Shell; |
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity bit_DIVV is
port
(in_Bus : in std_logic_vector(7 downto 0);
out_bus : out std_logic_vector(15 downto 0);
WindowEnable : in std_logic;
clk : in std_logic;
U_enable : std_logic;
TrainFlag: in std_logic;
aclr : in std_logic;
AccumulateSIGNAL: in std_logic;
CalculateSIGNAL: in std_logic;
last_row : in std_logic
);
end bit_DIVV;
architecture str_AddDiv1 of bit_DIVV is
signal data_total : std_logic_vector (15 downto 0);
signal add : integer range -16384 to 16383;
begin
TRAINcalculate: process(TrainFlag,CalculateSIGNAL) -- at end of training period do this, but only at start of a frame (and end of Vsync period)
variable Calc_total : std_logic_vector(15 downto 0);
begin
if (CalculateSIGNAL'event) and (CalculateSIGNAL='1') then
data_total <= data_total sll 2;
out_bus <= data_total;
if (TrainFlag = '1')then
-- HERE
end if;
end if;
end process TRAINcalculate;
end str_AddDiv1; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fmul_2_max_dsp_32;
ARCHITECTURE ANN_ap_fmul_2_max_dsp_32_arch OF ANN_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fmul_2_max_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fmul_2_max_dsp_32_arch;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:45:24)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_nsga2_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_nsga2_entity;
ARCHITECTURE mpegmv_nsga2_description OF mpegmv_nsga2_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
register3 := input3 * 5;
WHEN "00000011" =>
register3 := register3 + 7;
register2 := register2 + 9;
register4 := input4 * 10;
register5 := input5 * 11;
WHEN "00000100" =>
register4 := register4 + 13;
register6 := input6 * 14;
register1 := register5 + register1;
register5 := input7 * 15;
register7 := input8 * 16;
WHEN "00000101" =>
register1 := register7 + register1;
register7 := input9 * 17;
WHEN "00000110" =>
output1 <= register7 + register3;
register3 := input10 * 19;
register4 := register6 + register4;
register2 := register5 + register2;
register1 := ((NOT register1) + 1) XOR register1;
register5 := input11 * 22;
WHEN "00000111" =>
register4 := register5 + register4;
register5 := input12 * 23;
WHEN "00001000" =>
output2 <= register1(0 TO 15) & register4(0 TO 15);
register1 := input13 * 25;
register2 := register5 + register2;
WHEN "00001001" =>
register2 := ((NOT register2) + 1) XOR register2;
register4 := input14 * 28;
register1 := register1 + 30;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := register3 + register1;
WHEN "00001100" =>
output3 <= register2(0 TO 15) & register1(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_nsga2_description; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:31:50 06/04/2015
-- Design Name:
-- Module Name: F:/WorkSpace/workspace_ise/Exp/CPU/test_alu.vhd
-- Project Name: CPU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: module_ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_alu IS
END test_alu;
ARCHITECTURE behavior OF test_alu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT module_ALU
PORT(
clk_ALU : IN std_logic;
nreset : IN std_logic;
M_A : IN std_logic;
M_B : IN std_logic;
M_F : IN std_logic;
nALU_EN : IN std_logic;
nPSW_EN : IN std_logic;
C0 : IN std_logic;
S : IN std_logic_vector(4 downto 0);
F_in : IN std_logic_vector(1 downto 0);
datai : IN std_logic_vector(7 downto 0);
datao : OUT std_logic_vector(7 downto 0);
do : OUT std_logic;
AC : OUT std_logic;
CY : OUT std_logic;
ZN : OUT std_logic;
OV : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk_ALU : std_logic := '0';
signal nreset : std_logic := '0';
signal M_A : std_logic := '0';
signal M_B : std_logic := '0';
signal M_F : std_logic := '0';
signal nALU_EN : std_logic := '1';
signal nPSW_EN : std_logic := '1';
signal C0 : std_logic := '0';
signal S : std_logic_vector(4 downto 0) := (others => '0');
signal F_in : std_logic_vector(1 downto 0) := (others => '0');
signal datai : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal datao : std_logic_vector(7 downto 0);
signal do : std_logic;
signal AC : std_logic;
signal CY : std_logic;
signal ZN : std_logic;
signal OV : std_logic;
-- Clock period definitions
constant clk_ALU_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: module_ALU PORT MAP (
clk_ALU => clk_ALU,
nreset => nreset,
M_A => M_A,
M_B => M_B,
M_F => M_F,
nALU_EN => nALU_EN,
nPSW_EN => nPSW_EN,
C0 => C0,
S => S,
F_in => F_in,
datai => datai,
datao => datao,
do => do,
AC => AC,
CY => CY,
ZN => ZN,
OV => OV
);
-- Clock process definitions
clk_ALU_process :process
begin
clk_ALU <= '0';
wait for clk_ALU_period/2;
clk_ALU <= '1';
wait for clk_ALU_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
nreset <= '1';
-- insert stimulus here
M_A <= '1';
datai <= X"68";
wait for 100ns;
M_A <= '0';
M_B <= '1';
datai <= X"34";
wait for 100ns;
M_B <= '0';
nALU_EN <= '0';
S <= "00000";
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_byte_bus is
end test_byte_bus;
architecture behavioural of test_byte_bus is
component byte_bus is
generic (
bus_length : natural
);
port (
clock : in std_logic;
data : out std_logic_vector(7 downto 0)
);
end component byte_bus;
signal clock: std_logic;
signal data_bus : std_logic_vector(7 downto 0);
begin
BBUS: byte_bus generic map(4)
port map (clock, data_bus);
process
begin
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000000"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000001"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000010"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000011"
report "Data should match writer position" severity error;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert data_bus = "00000000"
report "Writer should cycle back to start" severity error;
wait;
end process;
end behavioural;
|
-- $Id: migui2bram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: migui2bram - sim
-- Description: MIG to BRAM adapter
--
-- Dependencies: xlib/s7_cmt_sfs
-- memlib/ram_1swsr_wfirst_gen
-- cdclib/cdc_signal_s1_as
-- Test bench: -
-- Target Devices: 7-Series
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-28 1096 1.0 Initial version
-- 2018-11-10 1067 0.1 First draft
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.cdclib.all;
use work.xlib.all;
entity migui2bram is -- MIG to BRAM adapter
generic (
BAWIDTH : positive := 4; -- byte address width
MAWIDTH : positive := 28; -- memory address width
RAWIDTH : positive := 19; -- BRAM memory address width
RDELAY : positive := 5; -- read response delay
CLKMUI_MUL : positive := 6; -- multiplier for MIGUI clock
CLKMUI_DIV : positive := 12; -- divider for MIGUI clock
CLKMSYS_PERIOD : real := 6.000); -- MIG SYS_CLK period
port (
SYS_CLK : in slbit; -- system clock
SYS_RST : in slbit; -- system reset
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_EN : in slbit; -- MIGUI command enable
APP_CMD : in slv3; -- MIGUI command
APP_ADDR : in slv(MAWIDTH-1 downto 0); -- MIGUI address
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_WDF_DATA : in slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
APP_WDF_MASK : in slv((2**BAWIDTH)-1 downto 0); -- MIGUI write mask
APP_WDF_END : in slbit; -- MIGUI write end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RD_DATA : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
APP_RD_DATA_END : out slbit -- MIGUI read end
);
end migui2bram;
architecture syn of migui2bram is
constant mwidth : positive := 2**BAWIDTH; -- mask width (8 or 16)
signal CLKFX : slbit := '0';
signal CLK : slbit := '0'; -- local copy of UI_CLK
signal R_RDVAL : slv(RDELAY downto 0) := (others=>'0');
signal LOCKED : slbit := '0'; -- raw from mmcm
signal LOCKED_UICLK : slbit := '0'; -- sync'ed to UI_CLK
begin
assert BAWIDTH = 3 or BAWIDTH = 4
report "assert( BAWIDTH = 3 or 4 )"
severity failure;
GEN_CLKMUI : s7_cmt_sfs -- ui clock ------------
generic map (
VCO_DIVIDE => 1,
VCO_MULTIPLY => CLKMUI_MUL,
OUT_DIVIDE => CLKMUI_DIV,
CLKIN_PERIOD => CLKMSYS_PERIOD,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => "MMCM")
port map (
CLKIN => SYS_CLK,
CLKFX => CLKFX,
LOCKED => LOCKED
);
CLK <= CLKFX; -- !! copy both local CLK and exported
UI_CLK <= CLKFX; -- !! UI_CLK to avoid delta cycle diff
CDC_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLK,
DI => LOCKED,
DO => LOCKED_UICLK
);
MARRAY: for col in mwidth-1 downto 0 generate
signal MEM_WE : slbit := '0';
begin
MEM_WE <= APP_WDF_WREN and not APP_WDF_MASK(col); -- WE = not MASK !
MCELL : ram_1swsr_wfirst_gen
generic map (
AWIDTH => RAWIDTH-BAWIDTH,
DWIDTH => 8) -- byte wide
port map (
CLK => CLK,
EN => APP_EN,
WE => MEM_WE,
ADDR => APP_ADDR(RAWIDTH-1 downto BAWIDTH),
DI => APP_WDF_DATA(8*col+7 downto 8*col),
DO => APP_RD_DATA(8*col+7 downto 8*col)
);
end generate MARRAY;
UI_CLK_SYNC_RST <= not LOCKED_UICLK;
INIT_CALIB_COMPLETE <= LOCKED_UICLK;
APP_RDY <= '1';
APP_WDF_RDY <= '1';
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '1' then
R_RDVAL <= (others=>'0');
else
R_RDVAL(0) <= APP_EN and not APP_WDF_WREN;
R_RDVAL(RDELAY downto 1) <= R_RDVAL(RDELAY-1 downto 0);
end if;
end if;
end process proc_regs;
APP_RD_DATA_VALID <= R_RDVAL(RDELAY);
APP_RD_DATA_END <= R_RDVAL(RDELAY);
-- synthesis translate_off
proc_moni: process (CLK)
begin
if rising_edge(CLK) then
if SYS_RST = '0' then
if APP_EN = '1' then
assert unsigned(APP_ADDR(MAWIDTH-1 downto RAWIDTH)) = 0
report "migui2bram: FAIL: out of memory size access"
severity error;
else
assert APP_WDF_WREN = '0'
report "migui2bram: FAIL: APP_WDF_WREN=1 when APP_EN=0"
severity error;
end if;
assert APP_WDF_WREN = APP_WDF_END
report "migui2bram: FAIL: APP_WDF_WREN /= APP_WDF_END"
severity error;
end if;
end if;
end process proc_moni;
-- synthesis translate_on
end syn;
|
-- VHDL do interface recepcao
library ieee;
use ieee.std_logic_1164.all;
entity interface_recepcao is
port(
clock: in std_logic;
reset: in std_logic;
pronto: in std_logic;
paridade_ok: in std_logic;
recebe_dado: in std_logic;
dado_entrada: in std_logic_vector(11 downto 0);
tem_dado_rec: out std_logic;
dado_rec: out std_logic_vector(11 downto 0)
);
end interface_recepcao;
architecture estrutural of interface_recepcao is
component unidade_controle_interface_recepcao is
port(
clock: in std_logic;
reset: in std_logic;
pronto: in std_logic;
recebe_dado: in std_logic;
tem_dado_rec: out std_logic;
habilita_registrador: out std_logic
);
end component;
component fluxo_dados_interface_recepcao is
port(
clock: in std_logic;
enable: in std_logic;
entrada: in std_logic_vector(11 downto 0);
saida: out std_logic_vector(11 downto 0)
);
end component;
signal sinal_habilita_registrador: std_logic;
begin
unidade_controle: unidade_controle_interface_recepcao port map (clock, reset, pronto, recebe_dado, tem_dado_rec, sinal_habilita_registrador);
fluxo_dados: fluxo_dados_interface_recepcao port map(clock, sinal_habilita_registrador, dado_entrada, dado_rec);
end estrutural;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad_ds
-- File: toutpad_ds.vhd
-- Author: Jonas Ekergarn - Aeroflex Gaisler
-- Description: tri-state differential output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of toutpad_ds is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or (is_unisim(tech) = 1) or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130
generate
padp <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
igl2 : if (tech = igloo2) generate
u0 : igloo2_toutpad_ds port map (padp, padn, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad_ds generic map (level)
port map (padp, padn, i, oen);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end;
architecture rtl of toutpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end;
architecture rtl of toutpad_dsvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/26/2016 11:44:06 PM
-- Design Name:
-- Module Name: sim_prf - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.sha1_pkg.all;
entity sim_prf is
end sim_prf;
architecture Behavioral of sim_prf is
component prf_main is
port(
clk_i : in std_ulogic;
rst_i : in std_ulogic;
load_i : in std_ulogic;
pmk_i : in w_input;
anonce_dat : in nonce_data;
cnonce_dat : in nonce_data;
amac_dat : in mac_data;
cmac_dat : in mac_data;
ptk_dat_o : out ptk_data;
ptk_valid_o : out std_ulogic
);
end component;
signal valid : std_ulogic;
signal load : std_ulogic := '0';
signal clk_i : std_ulogic := '0';
signal rst_i : std_ulogic := '0';
signal pmk : w_input;
signal anonce : nonce_data;
signal cnonce : nonce_data;
signal amac_dat : mac_data;
signal cmac_dat : mac_data;
signal ptk : ptk_data;
--pmk: 5df920b5481ed70538dd5fd02423d7e2522205feeebb974cad08a52b5613ede2
--a: 5061697277697365206b657920657870616e73696f6e
--b: 000b86c2a4850013ce5598efae12a150652e9bc22063720c5081e9eb74077fb19fffe871dc4ca1e6f448af85e8dfa16b8769957d8249a4ec68d2b7641d3782162ef0dc37b014cc48343e8dd2
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f8361
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345
--r: 5e9805e89cb0e84b45e5f9e4a1a80d9d9958c24e2b5ca71661334a890814f53e1d035e8beb4f83611dc93e2657cecf69a3651bc4fca5880ce9081345c5411d489313b29e4aaf287d5231a342b777a67a
--ptk: 5e9805e89cb0e84b45e5f9e4a1a80d9d
signal i: integer range 0 to 65535;
constant clock_period : time := 1 ns;
begin
prf: prf_main port map (clk_i,rst_i,load,pmk,anonce,cnonce,amac_dat,cmac_dat,ptk,valid);
stim_proc: process
begin
rst_i <= '0';
i <= 0;
load <= '0';
--Ordinally will come from PBKDF2
--5df920b5481ed70538dd5fd02423d7e2 522205feeebb974cad08a52b5613ede2
pmk <= (X"5df920b5",X"481ed705",X"38dd5fd0",X"2423d7e2",
X"522205fe",X"eebb974c",X"ad08a52b",X"5613ede2",
others=>(X"00000000"));
--b = min(apMac, cMac) + max(apMac, cMac) + min(apNonce, cNonce) + max(apNonce, cNonce)
--We're assuming that min/max will be calculated host-side
--Comes directly from handshake on host
--000b86c2a485
amac_dat <= (X"00",X"0b",X"86",X"c2",X"a4",X"85");
--0013ce5598ef
cmac_dat <= (X"00",X"13",X"ce",X"55",X"98",X"ef");
--ae12a150652e9bc22063720c5081e9eb 74077fb19fffe871dc4ca1e6f448af85
anonce <= (X"ae",X"12",X"a1",X"50",X"65",X"2e",X"9b",X"c2",X"20",X"63",X"72",X"0c",X"50",X"81",X"e9",X"eb",
X"74",X"07",X"7f",X"b1",X"9f",X"ff",X"e8",X"71",X"dc",X"4c",X"a1",X"e6",X"f4",X"48",X"af",X"85");
--e8dfa16b8769957d8249a4ec68d2b764 1d3782162ef0dc37b014cc48343e8dd2
cnonce <= (X"e8",X"df",X"a1",X"6b",X"87",X"69",X"95",X"7d",X"82",X"49",X"a4",X"ec",X"68",X"d2",X"b7",X"64",
X"1d",X"37",X"82",X"16",X"2e",X"f0",X"dc",X"37",X"b0",X"14",X"cc",X"48",X"34",X"3e",X"8d",X"d2");
wait until rising_edge(clk_i);
rst_i <= '1';
wait until rising_edge(clk_i);
rst_i <= '0';
wait until rising_edge(clk_i);
load <= '1';
wait until rising_edge(clk_i);
load <= '0';
wait until rising_edge(clk_i);
while valid = '0' loop
i <= i + 1;
wait until rising_edge(clk_i);
end loop;
wait;
end process;
clock_process: process
begin
clk_i <= '0';
wait for clock_period/2;
clk_i <= '1';
wait for clock_period/2;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc510.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n03i00510ent IS
END c03s02b02x00p06n03i00510ent;
ARCHITECTURE c03s02b02x00p06n03i00510arch OF c03s02b02x00p06n03i00510ent IS
type x is (one,two);
type rec_type is
record
x : bit;
y : integer;
z : x; -- Failure_here
-- ERROR: The use of a name that denotes a record element
-- is not allowed within the record type definition that declares the element.
end record;
BEGIN
TESTING: PROCESS
variable k : rec_type;
BEGIN
k.x = '0';
k.y = 123;
k.z = one;
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n03i00510 - The use of a name that denotes a record element is not allowed within the record type definition that declares the element."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n03i00510arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc510.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n03i00510ent IS
END c03s02b02x00p06n03i00510ent;
ARCHITECTURE c03s02b02x00p06n03i00510arch OF c03s02b02x00p06n03i00510ent IS
type x is (one,two);
type rec_type is
record
x : bit;
y : integer;
z : x; -- Failure_here
-- ERROR: The use of a name that denotes a record element
-- is not allowed within the record type definition that declares the element.
end record;
BEGIN
TESTING: PROCESS
variable k : rec_type;
BEGIN
k.x = '0';
k.y = 123;
k.z = one;
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n03i00510 - The use of a name that denotes a record element is not allowed within the record type definition that declares the element."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n03i00510arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc510.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n03i00510ent IS
END c03s02b02x00p06n03i00510ent;
ARCHITECTURE c03s02b02x00p06n03i00510arch OF c03s02b02x00p06n03i00510ent IS
type x is (one,two);
type rec_type is
record
x : bit;
y : integer;
z : x; -- Failure_here
-- ERROR: The use of a name that denotes a record element
-- is not allowed within the record type definition that declares the element.
end record;
BEGIN
TESTING: PROCESS
variable k : rec_type;
BEGIN
k.x = '0';
k.y = 123;
k.z = one;
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n03i00510 - The use of a name that denotes a record element is not allowed within the record type definition that declares the element."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n03i00510arch;
|
component qsys is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sdram_clock_areset_conduit_export : in std_logic := 'X'; -- export
sdram_clock_c0_clk : out std_logic; -- clk
sdram_read_control_fixed_location : in std_logic := 'X'; -- fixed_location
sdram_read_control_read_base : in std_logic_vector(31 downto 0) := (others => 'X'); -- read_base
sdram_read_control_read_length : in std_logic_vector(31 downto 0) := (others => 'X'); -- read_length
sdram_read_control_go : in std_logic := 'X'; -- go
sdram_read_control_done : out std_logic; -- done
sdram_read_control_early_done : out std_logic; -- early_done
sdram_read_user_read_buffer : in std_logic := 'X'; -- read_buffer
sdram_read_user_buffer_output_data : out std_logic_vector(63 downto 0); -- buffer_output_data
sdram_read_user_data_available : out std_logic; -- data_available
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
sdram_wire_cas_n : out std_logic; -- cas_n
sdram_wire_cke : out std_logic; -- cke
sdram_wire_cs_n : out std_logic; -- cs_n
sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
sdram_wire_ras_n : out std_logic; -- ras_n
sdram_wire_we_n : out std_logic; -- we_n
sdram_write_control_fixed_location : in std_logic := 'X'; -- fixed_location
sdram_write_control_write_base : in std_logic_vector(31 downto 0) := (others => 'X'); -- write_base
sdram_write_control_write_length : in std_logic_vector(31 downto 0) := (others => 'X'); -- write_length
sdram_write_control_go : in std_logic := 'X'; -- go
sdram_write_control_done : out std_logic; -- done
sdram_write_user_write_buffer : in std_logic := 'X'; -- write_buffer
sdram_write_user_buffer_input_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- buffer_input_data
sdram_write_user_buffer_full : out std_logic -- buffer_full
);
end component qsys;
u0 : component qsys
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sdram_clock_areset_conduit_export => CONNECTED_TO_sdram_clock_areset_conduit_export, -- sdram_clock_areset_conduit.export
sdram_clock_c0_clk => CONNECTED_TO_sdram_clock_c0_clk, -- sdram_clock_c0.clk
sdram_read_control_fixed_location => CONNECTED_TO_sdram_read_control_fixed_location, -- sdram_read_control.fixed_location
sdram_read_control_read_base => CONNECTED_TO_sdram_read_control_read_base, -- .read_base
sdram_read_control_read_length => CONNECTED_TO_sdram_read_control_read_length, -- .read_length
sdram_read_control_go => CONNECTED_TO_sdram_read_control_go, -- .go
sdram_read_control_done => CONNECTED_TO_sdram_read_control_done, -- .done
sdram_read_control_early_done => CONNECTED_TO_sdram_read_control_early_done, -- .early_done
sdram_read_user_read_buffer => CONNECTED_TO_sdram_read_user_read_buffer, -- sdram_read_user.read_buffer
sdram_read_user_buffer_output_data => CONNECTED_TO_sdram_read_user_buffer_output_data, -- .buffer_output_data
sdram_read_user_data_available => CONNECTED_TO_sdram_read_user_data_available, -- .data_available
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
sdram_write_control_fixed_location => CONNECTED_TO_sdram_write_control_fixed_location, -- sdram_write_control.fixed_location
sdram_write_control_write_base => CONNECTED_TO_sdram_write_control_write_base, -- .write_base
sdram_write_control_write_length => CONNECTED_TO_sdram_write_control_write_length, -- .write_length
sdram_write_control_go => CONNECTED_TO_sdram_write_control_go, -- .go
sdram_write_control_done => CONNECTED_TO_sdram_write_control_done, -- .done
sdram_write_user_write_buffer => CONNECTED_TO_sdram_write_user_write_buffer, -- sdram_write_user.write_buffer
sdram_write_user_buffer_input_data => CONNECTED_TO_sdram_write_user_buffer_input_data, -- .buffer_input_data
sdram_write_user_buffer_full => CONNECTED_TO_sdram_write_user_buffer_full -- .buffer_full
);
|
library verilog;
use verilog.vl_types.all;
entity adjustAdder4_vlg_vec_tst is
end adjustAdder4_vlg_vec_tst;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity led is
port
(
led_port_led: out std_logic_vector(0 to 15);
led_data: in std_logic_vector(15 downto 0)
);
end led;
architecture Behavioral of led is
begin
led_port_led <= led_data;
end Behavioral;
|
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_cdc is
generic (
C_CDC_TYPE : integer range 0 to 15 := 0 ;
-- Clock domain crossing type
-- 0 = pulse primary to secondary clk
-- 1 = level primary to secondary clk
-- 2 = pulse secondary to primary clk
-- 3 = level secondary to primary clk
-- 4 = vectr primary to secondary clk
-- 5 = vectr secondary to primary clk
-- 6 = pulse primary to secondary clk --No reset
-- 7 = level primary to secondary clk --No reset
-- 8 = pulse secondary to primary clk --No reset
-- 9 = level secondary to primary clk --No reset
-- 10 = pulse primary to secondary clk --Low latency
-- 11 = pulse secondary to primary clk --Low latency
-- 12 = pulse primary to secondary clk open ended
-- 13 = pulse secondary to primary clk open ended
-- 12 = pulse primary to secondary clk open ended -No reset
-- 13 = pulse secondary to primary clk open ended -No reset
C_RESET_STATE : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer := 32
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Secondary to Primary Clock Crossing --
scndry_in : in std_logic ; --
prmry_out : out std_logic ; --
--
-- Primary to Secondary Clock Crossing --
prmry_in : in std_logic ; --
scndry_out : out std_logic ; --
--
scndry_vect_s_h : in std_logic ; --
scndry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
--
prmry_vect_s_h : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end axi_vdma_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_in_d1_cdc_from <= '0';
--else
p_in_d1_cdc_from <= prmry_in_xored;
--end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_out_d1_cdc_to <= '0';
-- s_out_d2 <= '0';
-- s_out_d3 <= '0';
-- s_out_d4 <= '0';
--else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
--end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_in_d1_cdc_from <= '0';
else
s_in_d1_cdc_from <= scndry_in_xored;
end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_out_d1_cdc_to <= '0';
p_out_d2 <= '0';
p_out_d3 <= '0';
p_out_d4 <= '0';
else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_in_d1_cdc_from <= '0';
--else
s_in_d1_cdc_from <= scndry_in_xored;
--end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_out_d1_cdc_to <= '0';
-- p_out_d2 <= '0';
-- p_out_d3 <= '0';
-- p_out_d4 <= '0';
--else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
--end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC;
GENERATE_PULSE_P_S_CDC_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_LL generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
--s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
--s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_LL;
-- Generate PULSE clock domain crossing --No reset (resetn = 1)
GENERATE_PULSE_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_NO_RST generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P;
GENERATE_PULSE_CDC_S_P_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_LL generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
--p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
--p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_LL;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_NO_RST generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S and C_RESET_STATE = 0 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S_NO_RST generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_in_d1_cdc_from <= prmry_in;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 0 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '0';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P_NO_RST generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_in_d1_cdc_from <= scndry_in;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 1
GENERATE_LEVEL_S_P_CDC2 : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 1 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '1';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '1';
p_level_out_d2 <= '1';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC2;
GENERATE_VECT_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_P_S generate
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
P_REG_GREY_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_in_d1_cdc_from <= (others => '0');
elsif(prmry_vect_s_h = '1')then
p_vect_in_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process P_REG_GREY_IN;
-- Double register to secondary
S_REG_GREY_OUT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_out_d1_cdc_to <= (others => '0');
s_vect_out_d2 <= (others => '0');
else
s_vect_out_d1_cdc_to <= p_vect_in_d1_cdc_from;
s_vect_out_d2 <= s_vect_out_d1_cdc_to;
end if;
end if;
end process S_REG_GREY_OUT;
scndry_vect_out <= s_vect_out_d2;
prmry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_P_S_CDC;
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
GENERATE_VECT_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_S_P generate
signal s_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
S_REG_GREY_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_in_d1_cdc_from <= (others => '0');
elsif(scndry_vect_s_h = '1')then
s_vect_in_d1_cdc_from <= scndry_vect_in;
end if;
end if;
end process S_REG_GREY_IN;
-- Double register to primary
P_REG_GREY_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_out_d1_cdc_to <= (others => '0');
p_vect_out_d2 <= (others => '0');
else
p_vect_out_d1_cdc_to <= s_vect_in_d1_cdc_from;
p_vect_out_d2 <= p_vect_out_d1_cdc_to;
end if;
end if;
end process P_REG_GREY_OUT;
prmry_vect_out <= p_vect_out_d2;
scndry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_S_P_CDC;
--GENERATE_AFIFO_CDC :
--
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_cdc
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_cdc.vhd
-- Description: This entity encompases the Clock Domain Crossing Pulse
-- Generator
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_cdc is
generic (
C_CDC_TYPE : integer range 0 to 15 := 0 ;
-- Clock domain crossing type
-- 0 = pulse primary to secondary clk
-- 1 = level primary to secondary clk
-- 2 = pulse secondary to primary clk
-- 3 = level secondary to primary clk
-- 4 = vectr primary to secondary clk
-- 5 = vectr secondary to primary clk
-- 6 = pulse primary to secondary clk --No reset
-- 7 = level primary to secondary clk --No reset
-- 8 = pulse secondary to primary clk --No reset
-- 9 = level secondary to primary clk --No reset
-- 10 = pulse primary to secondary clk --Low latency
-- 11 = pulse secondary to primary clk --Low latency
-- 12 = pulse primary to secondary clk open ended
-- 13 = pulse secondary to primary clk open ended
-- 12 = pulse primary to secondary clk open ended -No reset
-- 13 = pulse secondary to primary clk open ended -No reset
C_RESET_STATE : integer range 0 to 1 := 0 ;
C_VECTOR_WIDTH : integer := 32
-- Vector Data witdth
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
scndry_aclk : in std_logic ; --
scndry_resetn : in std_logic ; --
--
-- Secondary to Primary Clock Crossing --
scndry_in : in std_logic ; --
prmry_out : out std_logic ; --
--
-- Primary to Secondary Clock Crossing --
prmry_in : in std_logic ; --
scndry_out : out std_logic ; --
--
scndry_vect_s_h : in std_logic ; --
scndry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
prmry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
--
prmry_vect_s_h : in std_logic ; --
prmry_vect_in : in std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) ; --
scndry_vect_out : out std_logic_vector --
(C_VECTOR_WIDTH - 1 downto 0) --
);
end axi_vdma_cdc;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_cdc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_in_d1_cdc_from <= '0';
else
p_in_d1_cdc_from <= prmry_in_xored;
end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_out_d1_cdc_to <= '0';
s_out_d2 <= '0';
s_out_d3 <= '0';
s_out_d4 <= '0';
else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal s_out_d1_cdc_to : std_logic := '0';
signal s_out_d2 : std_logic := '0';
signal s_out_d3 : std_logic := '0';
signal s_out_d4 : std_logic := '0';
signal s_out_re : std_logic := '0';
signal prmry_in_xored : std_logic := '0';
signal p_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
REG_P_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_in_d1_cdc_from <= '0';
--else
p_in_d1_cdc_from <= prmry_in_xored;
--end if;
end if;
end process REG_P_IN;
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_out_d1_cdc_to <= '0';
-- s_out_d2 <= '0';
-- s_out_d3 <= '0';
-- s_out_d4 <= '0';
--else
s_out_d1_cdc_to <= p_in_d1_cdc_from;
s_out_d2 <= s_out_d1_cdc_to;
s_out_d3 <= s_out_d2;
s_out_d4 <= s_out_d3;
--end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_out_re <= s_out_d3 xor s_out_d4;
-- Feed secondary pulse out
scndry_out <= s_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED_NO_RST;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_in_d1_cdc_from <= '0';
else
s_in_d1_cdc_from <= scndry_in_xored;
end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_out_d1_cdc_to <= '0';
p_out_d2 <= '0';
p_out_d3 <= '0';
p_out_d4 <= '0';
else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED;
GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_OPEN_ENDED_NO_RST generate
-- Primary to Secondary
signal p_out_d1_cdc_to : std_logic := '0';
signal p_out_d2 : std_logic := '0';
signal p_out_d3 : std_logic := '0';
signal p_out_d4 : std_logic := '0';
signal p_out_re : std_logic := '0';
signal scndry_in_xored : std_logic := '0';
signal s_in_d1_cdc_from : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_out_d4 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY OPEN-ENDED **
--*****************************************************************************
scndry_in_xored <= scndry_in xor s_in_d1_cdc_from;
REG_S_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
--if(scndry_resetn = '0')then
-- s_in_d1_cdc_from <= '0';
--else
s_in_d1_cdc_from <= scndry_in_xored;
--end if;
end if;
end process REG_S_IN;
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
--if(prmry_resetn = '0')then
-- p_out_d1_cdc_to <= '0';
-- p_out_d2 <= '0';
-- p_out_d3 <= '0';
-- p_out_d4 <= '0';
--else
p_out_d1_cdc_to <= s_in_d1_cdc_from;
p_out_d2 <= p_out_d1_cdc_to;
p_out_d3 <= p_out_d2;
p_out_d4 <= p_out_d3;
--end if;
end if;
end process S_IN_CROSS2PRMRY;
p_out_re <= p_out_d3 xor p_out_d4;
-- Feed secondary pulse out
prmry_out <= p_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_S_P_CDC_OPEN_ENDED_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC;
GENERATE_PULSE_P_S_CDC_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_LL generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_d1_cdc_to <= '0';
s_pulse_out_d2 <= '0';
s_pulse_out_d3 <= '0';
--s_pulse_out_re <= '0';
else
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
--s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end if;
end process P_IN_CROSS2SCNDRY;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_s_h_d1_cdc_to <= '0';
p_pulse_out_s_h_d2 <= '0';
p_pulse_out_s_h_d3 <= '0';
else
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_LL;
-- Generate PULSE clock domain crossing --No reset (resetn = 1)
GENERATE_PULSE_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_P_S_NO_RST generate
-- Primary to Secondary
signal p_pulse_in_s_h_cdc_from : std_logic := '0';
signal p_pulse_in_s_h_clr : std_logic := '0';
signal s_pulse_out_d1_cdc_to : std_logic := '0';
signal s_pulse_out_d2 : std_logic := '0';
signal s_pulse_out_d3 : std_logic := '0';
signal s_pulse_out_re : std_logic := '0';
signal s_pulse_out_s_h_cdc_from : std_logic := '0';
signal p_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal p_pulse_out_s_h_d2 : std_logic := '0';
signal p_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- Limitations:
-- For prmry_aclk faster than scndry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For prmry_aclk slower than scndry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold primary pulse
PRMRY_IN_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_in_s_h_clr='1')then
p_pulse_in_s_h_cdc_from <= '0';
elsif(prmry_in = '1')then
p_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_IN_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_IN_CROSS2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_d1_cdc_to <= p_pulse_in_s_h_cdc_from;
s_pulse_out_d2 <= s_pulse_out_d1_cdc_to;
s_pulse_out_d3 <= s_pulse_out_d2;
s_pulse_out_re <= s_pulse_out_d2 and not s_pulse_out_d3;
end if;
end process P_IN_CROSS2SCNDRY;
-- Sample and hold secondary pulse for clearing primary sampled
-- and held pulse
SCNDRY_OUT_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_out_d2='0')then
s_pulse_out_s_h_cdc_from <= '0';
elsif(s_pulse_out_re = '1')then
s_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_OUT_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_s_h_d1_cdc_to <= s_pulse_out_s_h_cdc_from;
p_pulse_out_s_h_d2 <= p_pulse_out_s_h_d1_cdc_to;
p_pulse_out_s_h_d3 <= p_pulse_out_s_h_d2;
end if;
end process S_OUT_CROSS2PRMRY;
-- Create sample and hold clear
p_pulse_in_s_h_clr <= p_pulse_out_s_h_d2 and not p_pulse_out_s_h_d3;
-- Feed secondary pulse out
scndry_out <= s_pulse_out_re;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_P_S_CDC_NO_RST;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P;
GENERATE_PULSE_CDC_S_P_LL : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_LL generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0' or s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_pulse_out_d1_cdc_to <= '0';
p_pulse_out_d2 <= '0';
p_pulse_out_d3 <= '0';
--p_pulse_out_re <= '0';
else
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
--p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end if;
end process S_IN_CROSS2PRMRY;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0' or p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_pulse_out_s_h_d1_cdc_to <= '0';
s_pulse_out_s_h_d2 <= '0';
s_pulse_out_s_h_d3 <= '0';
else
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_LL;
-- Generate PULSE clock domain crossing
GENERATE_PULSE_CDC_S_P_NO_RST : if C_CDC_TYPE = CDC_TYPE_PULSE_S_P_NO_RST generate
-- Secondary to Primary
signal s_pulse_in_s_h_cdc_from : std_logic := '0';
signal s_pulse_in_s_h_clr : std_logic := '0';
signal p_pulse_out_d1_cdc_to : std_logic := '0';
signal p_pulse_out_d2 : std_logic := '0';
signal p_pulse_out_d3 : std_logic := '0';
signal p_pulse_out_re : std_logic := '0';
signal p_pulse_out_s_h_cdc_from : std_logic := '0';
signal s_pulse_out_s_h_d1_cdc_to : std_logic := '0';
signal s_pulse_out_s_h_d2 : std_logic := '0';
signal s_pulse_out_s_h_d3 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_pulse_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_d3 : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_pulse_out_re : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d2 : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_pulse_out_s_h_d3 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Pulse Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- Limitations:
-- For scndry_aclk faster than prmry_aclk then limited to pulse period greater
-- than (prmry_clk_freq / scndry_clk_freq) * 5
-- For scndry_aclk slower than prmry_aclk then limited to pulse period greater
-- than (scndry_clk_freq / prmry_clk_freq) / 5
-- Sample and hold secondary pulse
SCNDRY_IN_S_H_PULSE : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(s_pulse_in_s_h_clr='1')then
s_pulse_in_s_h_cdc_from <= '0';
elsif(scndry_in = '1')then
s_pulse_in_s_h_cdc_from <= '1';
end if;
end if;
end process SCNDRY_IN_S_H_PULSE;
-- Cross sample and held pulse to primary domain
S_IN_CROSS2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_pulse_out_d1_cdc_to <= s_pulse_in_s_h_cdc_from;
p_pulse_out_d2 <= p_pulse_out_d1_cdc_to;
p_pulse_out_d3 <= p_pulse_out_d2;
p_pulse_out_re <= p_pulse_out_d2 and not p_pulse_out_d3;
end if;
end process S_IN_CROSS2PRMRY;
-- Sample and hold primary pulse for clearing secondary sampled
-- and held pulse
PRMRY_OUT_S_H_PULSE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(p_pulse_out_d2='0')then
p_pulse_out_s_h_cdc_from <= '0';
elsif(p_pulse_out_re = '1')then
p_pulse_out_s_h_cdc_from <= '1';
end if;
end if;
end process PRMRY_OUT_S_H_PULSE;
-- Cross sample and held pulse to secondary domain
P_OUT_CROSS2SCDNRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_pulse_out_s_h_d1_cdc_to <= p_pulse_out_s_h_cdc_from;
s_pulse_out_s_h_d2 <= s_pulse_out_s_h_d1_cdc_to;
s_pulse_out_s_h_d3 <= s_pulse_out_s_h_d2;
end if;
end process P_OUT_CROSS2SCDNRY;
-- Create sample and hold clear
s_pulse_in_s_h_clr <= s_pulse_out_s_h_d2 and not s_pulse_out_s_h_d3;
-- Feed primary pulse out
prmry_out <= p_pulse_out_re;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_PULSE_CDC_S_P_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S and C_RESET_STATE = 0 generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_in_d1_cdc_from <= '0';
else
p_level_in_d1_cdc_from <= prmry_in;
end if;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_out_d1_cdc_to <= '0';
s_level_out_d2 <= '0';
else
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_P_S_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_P_S_NO_RST generate
-- Primary to Secondary
signal p_level_in_d1_cdc_from : std_logic := '0';
signal s_level_out_d1_cdc_to : std_logic := '0';
signal s_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** PRIMARY TO SECONDARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_PLEVEL_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_in_d1_cdc_from <= prmry_in;
end if;
end process REG_PLEVEL_IN;
CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_out_d1_cdc_to <= p_level_in_d1_cdc_from;
s_level_out_d2 <= s_level_out_d1_cdc_to;
end if;
end process CROSS_PLEVEL_IN2SCNDRY;
scndry_out <= s_level_out_d2;
prmry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_P_S_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 0 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '0';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '0';
p_level_out_d2 <= '0';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC;
-- Generate LEVEL clock domain crossing with reset state = 0
GENERATE_LEVEL_S_P_CDC_NO_RST : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P_NO_RST generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
s_level_in_d1_cdc_from <= scndry_in;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC_NO_RST;
-- Generate LEVEL clock domain crossing with reset state = 1
GENERATE_LEVEL_S_P_CDC2 : if C_CDC_TYPE = CDC_TYPE_LEVEL_S_P and C_RESET_STATE = 1 generate
-- Secondray to Primary
signal s_level_in_d1_cdc_from : std_logic := '0';
signal p_level_out_d1_cdc_to : std_logic := '0';
signal p_level_out_d2 : std_logic := '0';
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_level_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_level_out_d2 : SIGNAL IS "true";
begin
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
-- register is scndry to provide clean ff output to clock crossing logic
REG_SLEVEL_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_level_in_d1_cdc_from <= '1';
else
s_level_in_d1_cdc_from <= scndry_in;
end if;
end if;
end process REG_SLEVEL_IN;
CROSS_SLEVEL_IN2PRMRY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_level_out_d1_cdc_to <= '1';
p_level_out_d2 <= '1';
else
p_level_out_d1_cdc_to <= s_level_in_d1_cdc_from;
p_level_out_d2 <= p_level_out_d1_cdc_to;
end if;
end if;
end process CROSS_SLEVEL_IN2PRMRY;
prmry_out <= p_level_out_d2;
scndry_out <= '0';
scndry_vect_out <= (others => '0');
prmry_vect_out <= (others => '0');
end generate GENERATE_LEVEL_S_P_CDC2;
GENERATE_VECT_P_S_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_P_S generate
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal p_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal s_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF s_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF s_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
P_REG_GREY_IN : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_in_d1_cdc_from <= (others => '0');
elsif(prmry_vect_s_h = '1')then
p_vect_in_d1_cdc_from <= prmry_vect_in;
end if;
end if;
end process P_REG_GREY_IN;
-- Double register to secondary
S_REG_GREY_OUT : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_out_d1_cdc_to <= (others => '0');
s_vect_out_d2 <= (others => '0');
else
s_vect_out_d1_cdc_to <= p_vect_in_d1_cdc_from;
s_vect_out_d2 <= s_vect_out_d1_cdc_to;
end if;
end if;
end process S_REG_GREY_OUT;
scndry_vect_out <= s_vect_out_d2;
prmry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_P_S_CDC;
--*****************************************************************************
--** Asynchronous Level Clock Crossing **
--** SECONDARY TO PRIMARY **
--*****************************************************************************
GENERATE_VECT_S_P_CDC : if C_CDC_TYPE = CDC_TYPE_VECTR_S_P generate
signal s_vect_in_d1_cdc_from : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d1_cdc_to : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
signal p_vect_out_d2 : std_logic_vector(C_VECTOR_WIDTH-1 downto 0) := (others => '0');
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF p_vect_out_d1_cdc_to : SIGNAL IS "true";
ATTRIBUTE async_reg OF p_vect_out_d2 : SIGNAL IS "true";
begin
-- Register signal in to give clear FF output to CDC
S_REG_GREY_IN : process(scndry_aclk)
begin
if(scndry_aclk'EVENT and scndry_aclk ='1')then
if(scndry_resetn = '0')then
s_vect_in_d1_cdc_from <= (others => '0');
elsif(scndry_vect_s_h = '1')then
s_vect_in_d1_cdc_from <= scndry_vect_in;
end if;
end if;
end process S_REG_GREY_IN;
-- Double register to primary
P_REG_GREY_OUT : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk ='1')then
if(prmry_resetn = '0')then
p_vect_out_d1_cdc_to <= (others => '0');
p_vect_out_d2 <= (others => '0');
else
p_vect_out_d1_cdc_to <= s_vect_in_d1_cdc_from;
p_vect_out_d2 <= p_vect_out_d1_cdc_to;
end if;
end if;
end process P_REG_GREY_OUT;
prmry_vect_out <= p_vect_out_d2;
scndry_vect_out <= (others => '0');
scndry_out <= '0';
prmry_out <= '0';
end generate GENERATE_VECT_S_P_CDC;
--GENERATE_AFIFO_CDC :
--
end implementation;
|
-- tracking_camera_system.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system is
port (
altpll_0_c0_clk : out std_logic; -- altpll_0_c0.clk
character_lcd_0_external_interface_DATA : inout std_logic_vector(7 downto 0) := (others => '0'); -- character_lcd_0_external_interface.DATA
character_lcd_0_external_interface_ON : out std_logic; -- .ON
character_lcd_0_external_interface_BLON : out std_logic; -- .BLON
character_lcd_0_external_interface_EN : out std_logic; -- .EN
character_lcd_0_external_interface_RS : out std_logic; -- .RS
character_lcd_0_external_interface_RW : out std_logic; -- .RW
switch_0_external_connection_export : in std_logic := '0'; -- switch_0_external_connection.export
servo_pwm_0_conduit_end_0_export : out std_logic; -- servo_pwm_0_conduit_end_0.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
switch_external_connection_export : in std_logic := '0'; -- switch_external_connection.export
clk_clk : in std_logic := '0'; -- clk.clk
sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- sdram_0_wire.addr
sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_0_wire_cas_n : out std_logic; -- .cas_n
sdram_0_wire_cke : out std_logic; -- .cke
sdram_0_wire_cs_n : out std_logic; -- .cs_n
sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_0_wire_ras_n : out std_logic; -- .ras_n
sdram_0_wire_we_n : out std_logic; -- .we_n
green_leds_external_connection_export : out std_logic_vector(7 downto 0); -- green_leds_external_connection.export
sram_0_external_interface_DQ : inout std_logic_vector(15 downto 0) := (others => '0'); -- sram_0_external_interface.DQ
sram_0_external_interface_ADDR : out std_logic_vector(17 downto 0); -- .ADDR
sram_0_external_interface_LB_N : out std_logic; -- .LB_N
sram_0_external_interface_UB_N : out std_logic; -- .UB_N
sram_0_external_interface_CE_N : out std_logic; -- .CE_N
sram_0_external_interface_OE_N : out std_logic; -- .OE_N
sram_0_external_interface_WE_N : out std_logic -- .WE_N
);
end entity tracking_camera_system;
architecture rtl of tracking_camera_system is
component tracking_camera_system_nios2_qsys_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
d_address : out std_logic_vector(24 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
d_readdatavalid : in std_logic := 'X'; -- readdatavalid
jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(24 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
i_readdatavalid : in std_logic := 'X'; -- readdatavalid
d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
jtag_debug_module_resetrequest : out std_logic; -- reset
jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
jtag_debug_module_begintransfer : in std_logic := 'X'; -- begintransfer
jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess
jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_debug_module_select : in std_logic := 'X'; -- chipselect
jtag_debug_module_write : in std_logic := 'X'; -- write
jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
no_ci_readra : out std_logic -- readra
);
end component tracking_camera_system_nios2_qsys_0;
component tracking_camera_system_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
clken : in std_logic := 'X'; -- clken
readdata : out std_logic_vector(31 downto 0); -- readdata
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X' -- reset
);
end component tracking_camera_system_onchip_memory2_0;
component tracking_camera_system_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X' -- address
);
end component tracking_camera_system_sysid_qsys_0;
component tracking_camera_system_timer_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component tracking_camera_system_timer_0;
component tracking_camera_system_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component tracking_camera_system_jtag_uart_0;
component tracking_camera_system_character_lcd_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
address : in std_logic := 'X'; -- address
chipselect : in std_logic := 'X'; -- chipselect
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(7 downto 0); -- readdata
waitrequest : out std_logic; -- waitrequest
LCD_DATA : inout std_logic_vector(7 downto 0) := (others => 'X'); -- export
LCD_ON : out std_logic; -- export
LCD_BLON : out std_logic; -- export
LCD_EN : out std_logic; -- export
LCD_RS : out std_logic; -- export
LCD_RW : out std_logic -- export
);
end component tracking_camera_system_character_lcd_0;
component tracking_camera_system_green_leds is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component tracking_camera_system_green_leds;
component tracking_camera_system_switch is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic := 'X' -- export
);
end component tracking_camera_system_switch;
component tracking_camera_system_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component tracking_camera_system_altpll_0;
component tracking_camera_system_sdram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(21 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(11 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component tracking_camera_system_sdram_0;
component tracking_camera_system_sram_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
SRAM_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
SRAM_ADDR : out std_logic_vector(17 downto 0); -- export
SRAM_LB_N : out std_logic; -- export
SRAM_UB_N : out std_logic; -- export
SRAM_CE_N : out std_logic; -- export
SRAM_OE_N : out std_logic; -- export
SRAM_WE_N : out std_logic; -- export
address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
readdatavalid : out std_logic -- readdatavalid
);
end component tracking_camera_system_sram_0;
component tracking_camera_system_servo_pwm_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
coe_servo : out std_logic; -- export
avs_s0_write_n : in std_logic := 'X'; -- write_n
avs_s0_writedata : in std_logic_vector(7 downto 0) := (others => 'X') -- writedata
);
end component tracking_camera_system_servo_pwm_0;
component tracking_camera_system_nios2_qsys_0_instruction_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_readdatavalid : out std_logic -- readdatavalid
);
end component tracking_camera_system_nios2_qsys_0_instruction_master_translator;
component tracking_camera_system_nios2_qsys_0_data_master_translator is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : out std_logic_vector(24 downto 0); -- address
uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount
uav_read : out std_logic; -- read
uav_write : out std_logic; -- write
uav_waitrequest : in std_logic := 'X'; -- waitrequest
uav_readdatavalid : in std_logic := 'X'; -- readdatavalid
uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable
uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
uav_writedata : out std_logic_vector(31 downto 0); -- writedata
uav_lock : out std_logic; -- lock
uav_debugaccess : out std_logic; -- debugaccess
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_waitrequest : out std_logic; -- waitrequest
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_read : in std_logic := 'X'; -- read
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_readdatavalid : out std_logic; -- readdatavalid
av_write : in std_logic := 'X'; -- write
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_debugaccess : in std_logic := 'X' -- debugaccess
);
end component tracking_camera_system_nios2_qsys_0_data_master_translator;
component tracking_camera_system_nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(99 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component tracking_camera_system_nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent;
component tracking_camera_system_nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
av_write : in std_logic := 'X'; -- write
av_read : in std_logic := 'X'; -- read
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_waitrequest : out std_logic; -- waitrequest
av_readdatavalid : out std_logic; -- readdatavalid
av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
av_debugaccess : in std_logic := 'X'; -- debugaccess
av_lock : in std_logic := 'X'; -- lock
cp_valid : out std_logic; -- valid
cp_data : out std_logic_vector(99 downto 0); -- data
cp_startofpacket : out std_logic; -- startofpacket
cp_endofpacket : out std_logic; -- endofpacket
cp_ready : in std_logic := 'X'; -- ready
rp_valid : in std_logic := 'X'; -- valid
rp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rp_startofpacket : in std_logic := 'X'; -- startofpacket
rp_endofpacket : in std_logic := 'X'; -- endofpacket
rp_ready : out std_logic -- ready
);
end component tracking_camera_system_nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(100 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(81 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(82 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(15 downto 0) -- data
);
end component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(82 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(15 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(81 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(82 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(15 downto 0) -- data
);
end component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(82 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(31 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X' -- ready
);
end component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo;
component tracking_camera_system_sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_timer_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_timer_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic; -- burstcount
m0_byteenable : out std_logic; -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(72 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(7 downto 0) -- data
);
end component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_data : out std_logic_vector(73 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo;
component tracking_camera_system_green_leds_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_green_leds_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_switch_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_switch_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_servo_pwm_0_s0_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic; -- burstcount
m0_byteenable : out std_logic; -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(7 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(72 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(73 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(7 downto 0) -- data
);
end component tracking_camera_system_servo_pwm_0_s0_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_switch_0_s1_translator_avalon_universal_slave_0_agent is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
m0_address : out std_logic_vector(24 downto 0); -- address
m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
m0_lock : out std_logic; -- lock
m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_read : out std_logic; -- read
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_writedata : out std_logic_vector(31 downto 0); -- writedata
m0_write : out std_logic; -- write
rp_endofpacket : out std_logic; -- endofpacket
rp_ready : in std_logic := 'X'; -- ready
rp_valid : out std_logic; -- valid
rp_data : out std_logic_vector(99 downto 0); -- data
rp_startofpacket : out std_logic; -- startofpacket
cp_ready : out std_logic; -- ready
cp_valid : in std_logic := 'X'; -- valid
cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cp_startofpacket : in std_logic := 'X'; -- startofpacket
cp_endofpacket : in std_logic := 'X'; -- endofpacket
cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rf_sink_ready : out std_logic; -- ready
rf_sink_valid : in std_logic := 'X'; -- valid
rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data
rf_source_ready : in std_logic := 'X'; -- ready
rf_source_valid : out std_logic; -- valid
rf_source_startofpacket : out std_logic; -- startofpacket
rf_source_endofpacket : out std_logic; -- endofpacket
rf_source_data : out std_logic_vector(100 downto 0); -- data
rdata_fifo_sink_ready : out std_logic; -- ready
rdata_fifo_sink_valid : in std_logic := 'X'; -- valid
rdata_fifo_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
rdata_fifo_src_ready : in std_logic := 'X'; -- ready
rdata_fifo_src_valid : out std_logic; -- valid
rdata_fifo_src_data : out std_logic_vector(31 downto 0) -- data
);
end component tracking_camera_system_switch_0_s1_translator_avalon_universal_slave_0_agent;
component tracking_camera_system_addr_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_addr_router;
component tracking_camera_system_addr_router_001 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_addr_router_001;
component tracking_camera_system_id_router is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router;
component tracking_camera_system_id_router_002 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(81 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router_002;
component tracking_camera_system_id_router_004 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router_004;
component tracking_camera_system_id_router_008 is
port (
sink_ready : out std_logic; -- ready
sink_valid : in std_logic := 'X'; -- valid
sink_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(72 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_id_router_008;
component tracking_camera_system_limiter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
cmd_sink_ready : out std_logic; -- ready
cmd_sink_valid : in std_logic := 'X'; -- valid
cmd_sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
cmd_sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
cmd_sink_startofpacket : in std_logic := 'X'; -- startofpacket
cmd_sink_endofpacket : in std_logic := 'X'; -- endofpacket
cmd_src_ready : in std_logic := 'X'; -- ready
cmd_src_data : out std_logic_vector(99 downto 0); -- data
cmd_src_channel : out std_logic_vector(12 downto 0); -- channel
cmd_src_startofpacket : out std_logic; -- startofpacket
cmd_src_endofpacket : out std_logic; -- endofpacket
rsp_sink_ready : out std_logic; -- ready
rsp_sink_valid : in std_logic := 'X'; -- valid
rsp_sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
rsp_sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
rsp_sink_startofpacket : in std_logic := 'X'; -- startofpacket
rsp_sink_endofpacket : in std_logic := 'X'; -- endofpacket
rsp_src_ready : in std_logic := 'X'; -- ready
rsp_src_valid : out std_logic; -- valid
rsp_src_data : out std_logic_vector(99 downto 0); -- data
rsp_src_channel : out std_logic_vector(12 downto 0); -- channel
rsp_src_startofpacket : out std_logic; -- startofpacket
rsp_src_endofpacket : out std_logic; -- endofpacket
cmd_src_valid : out std_logic_vector(12 downto 0) -- data
);
end component tracking_camera_system_limiter;
component tracking_camera_system_burst_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(81 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component tracking_camera_system_burst_adapter;
component tracking_camera_system_burst_adapter_002 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink0_valid : in std_logic := 'X'; -- valid
sink0_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink0_ready : out std_logic; -- ready
source0_valid : out std_logic; -- valid
source0_data : out std_logic_vector(72 downto 0); -- data
source0_channel : out std_logic_vector(12 downto 0); -- channel
source0_startofpacket : out std_logic; -- startofpacket
source0_endofpacket : out std_logic; -- endofpacket
source0_ready : in std_logic := 'X' -- ready
);
end component tracking_camera_system_burst_adapter_002;
component tracking_camera_system_rst_controller is
port (
reset_in0 : in std_logic := 'X'; -- reset
reset_in1 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic -- reset
);
end component tracking_camera_system_rst_controller;
component tracking_camera_system_cmd_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(12 downto 0) := (others => 'X'); -- data
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_cmd_xbar_demux;
component tracking_camera_system_cmd_xbar_demux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(12 downto 0) := (others => 'X'); -- data
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic; -- endofpacket
src2_ready : in std_logic := 'X'; -- ready
src2_valid : out std_logic; -- valid
src2_data : out std_logic_vector(99 downto 0); -- data
src2_channel : out std_logic_vector(12 downto 0); -- channel
src2_startofpacket : out std_logic; -- startofpacket
src2_endofpacket : out std_logic; -- endofpacket
src3_ready : in std_logic := 'X'; -- ready
src3_valid : out std_logic; -- valid
src3_data : out std_logic_vector(99 downto 0); -- data
src3_channel : out std_logic_vector(12 downto 0); -- channel
src3_startofpacket : out std_logic; -- startofpacket
src3_endofpacket : out std_logic; -- endofpacket
src4_ready : in std_logic := 'X'; -- ready
src4_valid : out std_logic; -- valid
src4_data : out std_logic_vector(99 downto 0); -- data
src4_channel : out std_logic_vector(12 downto 0); -- channel
src4_startofpacket : out std_logic; -- startofpacket
src4_endofpacket : out std_logic; -- endofpacket
src5_ready : in std_logic := 'X'; -- ready
src5_valid : out std_logic; -- valid
src5_data : out std_logic_vector(99 downto 0); -- data
src5_channel : out std_logic_vector(12 downto 0); -- channel
src5_startofpacket : out std_logic; -- startofpacket
src5_endofpacket : out std_logic; -- endofpacket
src6_ready : in std_logic := 'X'; -- ready
src6_valid : out std_logic; -- valid
src6_data : out std_logic_vector(99 downto 0); -- data
src6_channel : out std_logic_vector(12 downto 0); -- channel
src6_startofpacket : out std_logic; -- startofpacket
src6_endofpacket : out std_logic; -- endofpacket
src7_ready : in std_logic := 'X'; -- ready
src7_valid : out std_logic; -- valid
src7_data : out std_logic_vector(99 downto 0); -- data
src7_channel : out std_logic_vector(12 downto 0); -- channel
src7_startofpacket : out std_logic; -- startofpacket
src7_endofpacket : out std_logic; -- endofpacket
src8_ready : in std_logic := 'X'; -- ready
src8_valid : out std_logic; -- valid
src8_data : out std_logic_vector(99 downto 0); -- data
src8_channel : out std_logic_vector(12 downto 0); -- channel
src8_startofpacket : out std_logic; -- startofpacket
src8_endofpacket : out std_logic; -- endofpacket
src9_ready : in std_logic := 'X'; -- ready
src9_valid : out std_logic; -- valid
src9_data : out std_logic_vector(99 downto 0); -- data
src9_channel : out std_logic_vector(12 downto 0); -- channel
src9_startofpacket : out std_logic; -- startofpacket
src9_endofpacket : out std_logic; -- endofpacket
src10_ready : in std_logic := 'X'; -- ready
src10_valid : out std_logic; -- valid
src10_data : out std_logic_vector(99 downto 0); -- data
src10_channel : out std_logic_vector(12 downto 0); -- channel
src10_startofpacket : out std_logic; -- startofpacket
src10_endofpacket : out std_logic; -- endofpacket
src11_ready : in std_logic := 'X'; -- ready
src11_valid : out std_logic; -- valid
src11_data : out std_logic_vector(99 downto 0); -- data
src11_channel : out std_logic_vector(12 downto 0); -- channel
src11_startofpacket : out std_logic; -- startofpacket
src11_endofpacket : out std_logic; -- endofpacket
src12_ready : in std_logic := 'X'; -- ready
src12_valid : out std_logic; -- valid
src12_data : out std_logic_vector(99 downto 0); -- data
src12_channel : out std_logic_vector(12 downto 0); -- channel
src12_startofpacket : out std_logic; -- startofpacket
src12_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_cmd_xbar_demux_001;
component tracking_camera_system_cmd_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X' -- endofpacket
);
end component tracking_camera_system_cmd_xbar_mux;
component tracking_camera_system_rsp_xbar_demux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic; -- endofpacket
src1_ready : in std_logic := 'X'; -- ready
src1_valid : out std_logic; -- valid
src1_data : out std_logic_vector(99 downto 0); -- data
src1_channel : out std_logic_vector(12 downto 0); -- channel
src1_startofpacket : out std_logic; -- startofpacket
src1_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_rsp_xbar_demux;
component tracking_camera_system_rsp_xbar_demux_004 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
sink_ready : out std_logic; -- ready
sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink_startofpacket : in std_logic := 'X'; -- startofpacket
sink_endofpacket : in std_logic := 'X'; -- endofpacket
sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid
src0_ready : in std_logic := 'X'; -- ready
src0_valid : out std_logic; -- valid
src0_data : out std_logic_vector(99 downto 0); -- data
src0_channel : out std_logic_vector(12 downto 0); -- channel
src0_startofpacket : out std_logic; -- startofpacket
src0_endofpacket : out std_logic -- endofpacket
);
end component tracking_camera_system_rsp_xbar_demux_004;
component tracking_camera_system_rsp_xbar_mux is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X' -- endofpacket
);
end component tracking_camera_system_rsp_xbar_mux;
component tracking_camera_system_rsp_xbar_mux_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
src_ready : in std_logic := 'X'; -- ready
src_valid : out std_logic; -- valid
src_data : out std_logic_vector(99 downto 0); -- data
src_channel : out std_logic_vector(12 downto 0); -- channel
src_startofpacket : out std_logic; -- startofpacket
src_endofpacket : out std_logic; -- endofpacket
sink0_ready : out std_logic; -- ready
sink0_valid : in std_logic := 'X'; -- valid
sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink0_startofpacket : in std_logic := 'X'; -- startofpacket
sink0_endofpacket : in std_logic := 'X'; -- endofpacket
sink1_ready : out std_logic; -- ready
sink1_valid : in std_logic := 'X'; -- valid
sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink1_startofpacket : in std_logic := 'X'; -- startofpacket
sink1_endofpacket : in std_logic := 'X'; -- endofpacket
sink2_ready : out std_logic; -- ready
sink2_valid : in std_logic := 'X'; -- valid
sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink2_startofpacket : in std_logic := 'X'; -- startofpacket
sink2_endofpacket : in std_logic := 'X'; -- endofpacket
sink3_ready : out std_logic; -- ready
sink3_valid : in std_logic := 'X'; -- valid
sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink3_startofpacket : in std_logic := 'X'; -- startofpacket
sink3_endofpacket : in std_logic := 'X'; -- endofpacket
sink4_ready : out std_logic; -- ready
sink4_valid : in std_logic := 'X'; -- valid
sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink4_startofpacket : in std_logic := 'X'; -- startofpacket
sink4_endofpacket : in std_logic := 'X'; -- endofpacket
sink5_ready : out std_logic; -- ready
sink5_valid : in std_logic := 'X'; -- valid
sink5_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink5_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink5_startofpacket : in std_logic := 'X'; -- startofpacket
sink5_endofpacket : in std_logic := 'X'; -- endofpacket
sink6_ready : out std_logic; -- ready
sink6_valid : in std_logic := 'X'; -- valid
sink6_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink6_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink6_startofpacket : in std_logic := 'X'; -- startofpacket
sink6_endofpacket : in std_logic := 'X'; -- endofpacket
sink7_ready : out std_logic; -- ready
sink7_valid : in std_logic := 'X'; -- valid
sink7_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink7_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink7_startofpacket : in std_logic := 'X'; -- startofpacket
sink7_endofpacket : in std_logic := 'X'; -- endofpacket
sink8_ready : out std_logic; -- ready
sink8_valid : in std_logic := 'X'; -- valid
sink8_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink8_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink8_startofpacket : in std_logic := 'X'; -- startofpacket
sink8_endofpacket : in std_logic := 'X'; -- endofpacket
sink9_ready : out std_logic; -- ready
sink9_valid : in std_logic := 'X'; -- valid
sink9_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink9_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink9_startofpacket : in std_logic := 'X'; -- startofpacket
sink9_endofpacket : in std_logic := 'X'; -- endofpacket
sink10_ready : out std_logic; -- ready
sink10_valid : in std_logic := 'X'; -- valid
sink10_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink10_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink10_startofpacket : in std_logic := 'X'; -- startofpacket
sink10_endofpacket : in std_logic := 'X'; -- endofpacket
sink11_ready : out std_logic; -- ready
sink11_valid : in std_logic := 'X'; -- valid
sink11_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink11_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink11_startofpacket : in std_logic := 'X'; -- startofpacket
sink11_endofpacket : in std_logic := 'X'; -- endofpacket
sink12_ready : out std_logic; -- ready
sink12_valid : in std_logic := 'X'; -- valid
sink12_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
sink12_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
sink12_startofpacket : in std_logic := 'X'; -- startofpacket
sink12_endofpacket : in std_logic := 'X' -- endofpacket
);
end component tracking_camera_system_rsp_xbar_mux_001;
component tracking_camera_system_width_adapter is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(81 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter;
component tracking_camera_system_width_adapter_001 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter_001;
component tracking_camera_system_width_adapter_004 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(72 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter_004;
component tracking_camera_system_width_adapter_005 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(99 downto 0); -- data
out_channel : out std_logic_vector(12 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic -- startofpacket
);
end component tracking_camera_system_width_adapter_005;
component tracking_camera_system_crosser is
port (
in_clk : in std_logic := 'X'; -- clk
in_reset : in std_logic := 'X'; -- reset
out_clk : in std_logic := 'X'; -- clk
out_reset : in std_logic := 'X'; -- reset
in_ready : out std_logic; -- ready
in_valid : in std_logic := 'X'; -- valid
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel
in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data
out_ready : in std_logic := 'X'; -- ready
out_valid : out std_logic; -- valid
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
out_channel : out std_logic_vector(12 downto 0); -- channel
out_data : out std_logic_vector(99 downto 0) -- data
);
end component tracking_camera_system_crosser;
component tracking_camera_system_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component tracking_camera_system_irq_mapper;
component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(8 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_debugaccess : out std_logic; -- debugaccess
av_read : out std_logic; -- read
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator;
component tracking_camera_system_onchip_memory2_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(11 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_onchip_memory2_0_s1_translator;
component tracking_camera_system_sdram_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(21 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_sdram_0_s1_translator;
component tracking_camera_system_sram_0_avalon_sram_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(15 downto 0); -- readdata
uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(17 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_byteenable : out std_logic_vector(1 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_sram_0_avalon_sram_slave_translator;
component tracking_camera_system_altpll_0_pll_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_altpll_0_pll_slave_translator;
component tracking_camera_system_sysid_qsys_0_control_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_sysid_qsys_0_control_slave_translator;
component tracking_camera_system_timer_0_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(2 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(15 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_timer_0_s1_translator;
component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator;
component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(7 downto 0); -- readdata
uav_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(7 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator;
component tracking_camera_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component tracking_camera_system_green_leds_s1_translator;
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [addr_router:clk, addr_router_001:clk, burst_adapter:clk, burst_adapter_001:clk, burst_adapter_002:clk, burst_adapter_003:clk, character_lcd_0:clk, character_lcd_0_avalon_lcd_slave_translator:clk, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:clk, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, crosser:in_clk, crosser_001:out_clk, green_leds:clk, green_leds_s1_translator:clk, green_leds_s1_translator_avalon_universal_slave_0_agent:clk, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_008:clk, id_router_009:clk, id_router_010:clk, id_router_011:clk, id_router_012:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, limiter:clk, limiter_001:clk, nios2_qsys_0:clk, nios2_qsys_0_data_master_translator:clk, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_instruction_master_translator:clk, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_008:clk, rsp_xbar_demux_009:clk, rsp_xbar_demux_010:clk, rsp_xbar_demux_011:clk, rsp_xbar_demux_012:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, servo_pwm_0:clk, servo_pwm_0_s0_translator:clk, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:clk, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sram_0:clk, sram_0_avalon_sram_slave_translator:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switch:clk, switch_0:clk, switch_0_s1_translator:clk, switch_0_s1_translator_avalon_universal_slave_0_agent:clk, switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switch_s1_translator:clk, switch_s1_translator_avalon_universal_slave_0_agent:clk, switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk, width_adapter_006:clk, width_adapter_007:clk]
signal nios2_qsys_0_instruction_master_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest
signal nios2_qsys_0_instruction_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address
signal nios2_qsys_0_instruction_master_read : std_logic; -- nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read
signal nios2_qsys_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata
signal nios2_qsys_0_instruction_master_readdatavalid : std_logic; -- nios2_qsys_0_instruction_master_translator:av_readdatavalid -> nios2_qsys_0:i_readdatavalid
signal nios2_qsys_0_data_master_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest
signal nios2_qsys_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata
signal nios2_qsys_0_data_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address
signal nios2_qsys_0_data_master_write : std_logic; -- nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write
signal nios2_qsys_0_data_master_read : std_logic; -- nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read
signal nios2_qsys_0_data_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata
signal nios2_qsys_0_data_master_debugaccess : std_logic; -- nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess
signal nios2_qsys_0_data_master_readdatavalid : std_logic; -- nios2_qsys_0_data_master_translator:av_readdatavalid -> nios2_qsys_0:d_readdatavalid
signal nios2_qsys_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address : std_logic_vector(8 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_chipselect -> nios2_qsys_0:jtag_debug_module_select
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_begintransfer -> nios2_qsys_0:jtag_debug_module_begintransfer
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(11 downto 0); -- onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken : std_logic; -- onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata
signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable
signal sdram_0_s1_translator_avalon_anti_slave_0_waitrequest : std_logic; -- sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
signal sdram_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:av_writedata -> sdram_0:az_data
signal sdram_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- sdram_0_s1_translator:av_address -> sdram_0:az_addr
signal sdram_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
signal sdram_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- sdram_0_s1_translator:av_write -> sdram_0_s1_translator_avalon_anti_slave_0_write:in
signal sdram_0_s1_translator_avalon_anti_slave_0_read : std_logic; -- sdram_0_s1_translator:av_read -> sdram_0_s1_translator_avalon_anti_slave_0_read:in
signal sdram_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sdram_0:za_data -> sdram_0_s1_translator:av_readdata
signal sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator:av_byteenable -> sdram_0_s1_translator_avalon_anti_slave_0_byteenable:in
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator:av_address -> sram_0:address
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write : std_logic; -- sram_0_avalon_sram_slave_translator:av_write -> sram_0:write
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read : std_logic; -- sram_0_avalon_sram_slave_translator:av_read -> sram_0:read
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sram_0:readdatavalid -> sram_0_avalon_sram_slave_translator:av_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:av_writedata -> altpll_0:writedata
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- altpll_0_pll_slave_translator:av_address -> altpll_0:address
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_write : std_logic; -- altpll_0_pll_slave_translator:av_write -> altpll_0:write
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_read : std_logic; -- altpll_0_pll_slave_translator:av_read -> altpll_0:read
signal altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> altpll_0_pll_slave_translator:av_readdata
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
signal timer_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- timer_0_s1_translator:av_writedata -> timer_0:writedata
signal timer_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(2 downto 0); -- timer_0_s1_translator:av_address -> timer_0:address
signal timer_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- timer_0_s1_translator:av_chipselect -> timer_0:chipselect
signal timer_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- timer_0_s1_translator:av_write -> timer_0_s1_translator_avalon_anti_slave_0_write:in
signal timer_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- timer_0:readdata -> timer_0_s1_translator:av_readdata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:in
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- character_lcd_0:waitrequest -> character_lcd_0_avalon_lcd_slave_translator:av_waitrequest
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator:av_writedata -> character_lcd_0:writedata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- character_lcd_0_avalon_lcd_slave_translator:av_address -> character_lcd_0:address
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:av_chipselect -> character_lcd_0:chipselect
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:av_write -> character_lcd_0:write
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:av_read -> character_lcd_0:read
signal character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(7 downto 0); -- character_lcd_0:readdata -> character_lcd_0_avalon_lcd_slave_translator:av_readdata
signal green_leds_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:av_writedata -> green_leds:writedata
signal green_leds_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- green_leds_s1_translator:av_address -> green_leds:address
signal green_leds_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- green_leds_s1_translator:av_chipselect -> green_leds:chipselect
signal green_leds_s1_translator_avalon_anti_slave_0_write : std_logic; -- green_leds_s1_translator:av_write -> green_leds_s1_translator_avalon_anti_slave_0_write:in
signal green_leds_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- green_leds:readdata -> green_leds_s1_translator:av_readdata
signal switch_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- switch_s1_translator:av_address -> switch:address
signal switch_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- switch:readdata -> switch_s1_translator:av_readdata
signal servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator:av_writedata -> servo_pwm_0:avs_s0_writedata
signal servo_pwm_0_s0_translator_avalon_anti_slave_0_write : std_logic; -- servo_pwm_0_s0_translator:av_write -> servo_pwm_0_s0_translator_avalon_anti_slave_0_write:in
signal switch_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- switch_0_s1_translator:av_address -> switch_0:address
signal switch_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- switch_0:readdata -> switch_0_s1_translator:av_readdata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(15 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:uav_waitrequest -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> character_lcd_0_avalon_lcd_slave_translator:uav_burstcount
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> character_lcd_0_avalon_lcd_slave_translator:uav_writedata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_address -> character_lcd_0_avalon_lcd_slave_translator:uav_address
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_write -> character_lcd_0_avalon_lcd_slave_translator:uav_write
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_lock -> character_lcd_0_avalon_lcd_slave_translator:uav_lock
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_read -> character_lcd_0_avalon_lcd_slave_translator:uav_read
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator:uav_readdata -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_readdata
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator:uav_readdatavalid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> character_lcd_0_avalon_lcd_slave_translator:uav_debugaccess
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> character_lcd_0_avalon_lcd_slave_translator:uav_byteenable
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(73 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(73 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(7 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- green_leds_s1_translator:uav_waitrequest -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> green_leds_s1_translator:uav_burstcount
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> green_leds_s1_translator:uav_writedata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_address -> green_leds_s1_translator:uav_address
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_write -> green_leds_s1_translator:uav_write
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_lock -> green_leds_s1_translator:uav_lock
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_read -> green_leds_s1_translator:uav_read
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:uav_readdata -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- green_leds_s1_translator:uav_readdatavalid -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> green_leds_s1_translator:uav_debugaccess
signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> green_leds_s1_translator:uav_byteenable
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- switch_s1_translator:uav_waitrequest -> switch_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switch_s1_translator:uav_burstcount
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switch_s1_translator:uav_writedata
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_address -> switch_s1_translator:uav_address
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_write -> switch_s1_translator:uav_write
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switch_s1_translator:uav_lock
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_read -> switch_s1_translator:uav_read
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- switch_s1_translator:uav_readdata -> switch_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- switch_s1_translator:uav_readdatavalid -> switch_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switch_s1_translator:uav_debugaccess
signal switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switch_s1_translator:uav_byteenable
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- servo_pwm_0_s0_translator:uav_waitrequest -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_burstcount -> servo_pwm_0_s0_translator:uav_burstcount
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_writedata -> servo_pwm_0_s0_translator:uav_writedata
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_address -> servo_pwm_0_s0_translator:uav_address
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_write -> servo_pwm_0_s0_translator:uav_write
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_lock -> servo_pwm_0_s0_translator:uav_lock
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_read -> servo_pwm_0_s0_translator:uav_read
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator:uav_readdata -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_readdata
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- servo_pwm_0_s0_translator:uav_readdatavalid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_debugaccess -> servo_pwm_0_s0_translator:uav_debugaccess
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:m0_byteenable -> servo_pwm_0_s0_translator:uav_byteenable
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(73 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_source_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(73 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rf_sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(7 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- switch_0_s1_translator:uav_waitrequest -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switch_0_s1_translator:uav_burstcount
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switch_0_s1_translator:uav_writedata
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> switch_0_s1_translator:uav_address
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> switch_0_s1_translator:uav_write
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switch_0_s1_translator:uav_lock
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> switch_0_s1_translator:uav_read
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- switch_0_s1_translator:uav_readdata -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- switch_0_s1_translator:uav_readdatavalid -> switch_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switch_0_s1_translator:uav_debugaccess
signal switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switch_0_s1_translator:uav_byteenable
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(31 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_007:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(72 downto 0); -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
signal character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_008:sink_ready -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:rp_ready
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_009:sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- switch_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
signal switch_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_010:sink_ready -> switch_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(72 downto 0); -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data
signal servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_011:sink_ready -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:rp_ready
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- switch_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data
signal switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_012:sink_ready -> switch_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> limiter:cmd_sink_valid
signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
signal addr_router_src_data : std_logic_vector(99 downto 0); -- addr_router:src_data -> limiter:cmd_sink_data
signal addr_router_src_channel : std_logic_vector(12 downto 0); -- addr_router:src_channel -> limiter:cmd_sink_channel
signal addr_router_src_ready : std_logic; -- limiter:cmd_sink_ready -> addr_router:src_ready
signal limiter_rsp_src_endofpacket : std_logic; -- limiter:rsp_src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal limiter_rsp_src_valid : std_logic; -- limiter:rsp_src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
signal limiter_rsp_src_startofpacket : std_logic; -- limiter:rsp_src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal limiter_rsp_src_data : std_logic_vector(99 downto 0); -- limiter:rsp_src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data
signal limiter_rsp_src_channel : std_logic_vector(12 downto 0); -- limiter:rsp_src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
signal limiter_rsp_src_ready : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready
signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> limiter_001:cmd_sink_valid
signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
signal addr_router_001_src_data : std_logic_vector(99 downto 0); -- addr_router_001:src_data -> limiter_001:cmd_sink_data
signal addr_router_001_src_channel : std_logic_vector(12 downto 0); -- addr_router_001:src_channel -> limiter_001:cmd_sink_channel
signal addr_router_001_src_ready : std_logic; -- limiter_001:cmd_sink_ready -> addr_router_001:src_ready
signal limiter_001_rsp_src_endofpacket : std_logic; -- limiter_001:rsp_src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
signal limiter_001_rsp_src_valid : std_logic; -- limiter_001:rsp_src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid
signal limiter_001_rsp_src_startofpacket : std_logic; -- limiter_001:rsp_src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
signal limiter_001_rsp_src_data : std_logic_vector(99 downto 0); -- limiter_001:rsp_src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data
signal limiter_001_rsp_src_channel : std_logic_vector(12 downto 0); -- limiter_001:rsp_src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel
signal limiter_001_rsp_src_ready : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready
signal burst_adapter_source0_endofpacket : std_logic; -- burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_source0_valid : std_logic; -- burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_source0_startofpacket : std_logic; -- burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_source0_data : std_logic_vector(81 downto 0); -- burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_source0_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
signal burst_adapter_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_001_source0_endofpacket : std_logic; -- burst_adapter_001:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_001_source0_valid : std_logic; -- burst_adapter_001:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_001_source0_startofpacket : std_logic; -- burst_adapter_001:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_001_source0_data : std_logic_vector(81 downto 0); -- burst_adapter_001:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_001_source0_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
signal burst_adapter_001_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_001:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_002_source0_endofpacket : std_logic; -- burst_adapter_002:source0_endofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_002_source0_valid : std_logic; -- burst_adapter_002:source0_valid -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_002_source0_startofpacket : std_logic; -- burst_adapter_002:source0_startofpacket -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_002_source0_data : std_logic_vector(72 downto 0); -- burst_adapter_002:source0_data -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_002_source0_ready : std_logic; -- character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_002:source0_ready
signal burst_adapter_002_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_002:source0_channel -> character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal burst_adapter_003_source0_endofpacket : std_logic; -- burst_adapter_003:source0_endofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal burst_adapter_003_source0_valid : std_logic; -- burst_adapter_003:source0_valid -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_valid
signal burst_adapter_003_source0_startofpacket : std_logic; -- burst_adapter_003:source0_startofpacket -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal burst_adapter_003_source0_data : std_logic_vector(72 downto 0); -- burst_adapter_003:source0_data -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_data
signal burst_adapter_003_source0_ready : std_logic; -- servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_003:source0_ready
signal burst_adapter_003_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_003:source0_channel -> servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:cp_channel
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, burst_adapter_001:reset, burst_adapter_002:reset, burst_adapter_003:reset, character_lcd_0:reset, character_lcd_0_avalon_lcd_slave_translator:reset, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent:reset, character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, crosser:in_reset, crosser_001:out_reset, green_leds_s1_translator:reset, green_leds_s1_translator_avalon_universal_slave_0_agent:reset, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, irq_mapper:reset, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, rst_controller_reset_out_reset:in, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, servo_pwm_0_s0_translator:reset, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent:reset, servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switch_0_s1_translator:reset, switch_0_s1_translator_avalon_universal_slave_0_agent:reset, switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switch_s1_translator:reset, switch_s1_translator_avalon_universal_slave_0_agent:reset, switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset, width_adapter_006:reset, width_adapter_007:reset]
signal nios2_qsys_0_jtag_debug_module_reset_reset : std_logic; -- nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, altpll_0_pll_slave_translator:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:out_reset, crosser_001:in_reset, id_router_004:reset, rsp_xbar_demux_004:reset]
signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
signal cmd_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
signal cmd_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
signal cmd_xbar_demux_src0_ready : std_logic; -- cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
signal cmd_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
signal cmd_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
signal cmd_xbar_demux_src1_ready : std_logic; -- cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
signal cmd_xbar_demux_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
signal cmd_xbar_demux_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
signal cmd_xbar_demux_src2_ready : std_logic; -- cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
signal cmd_xbar_demux_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
signal cmd_xbar_demux_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
signal cmd_xbar_demux_src3_ready : std_logic; -- cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
signal cmd_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
signal cmd_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
signal cmd_xbar_demux_001_src0_ready : std_logic; -- cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
signal cmd_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
signal cmd_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
signal cmd_xbar_demux_001_src1_ready : std_logic; -- cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid
signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
signal cmd_xbar_demux_001_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data
signal cmd_xbar_demux_001_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel
signal cmd_xbar_demux_001_src2_ready : std_logic; -- cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready
signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid
signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
signal cmd_xbar_demux_001_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data
signal cmd_xbar_demux_001_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel
signal cmd_xbar_demux_001_src3_ready : std_logic; -- cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready
signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src5_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src5_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src5_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src5_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src6_endofpacket : std_logic; -- cmd_xbar_demux_001:src6_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src6_valid : std_logic; -- cmd_xbar_demux_001:src6_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src6_startofpacket : std_logic; -- cmd_xbar_demux_001:src6_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src6_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src6_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src6_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src6_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src7_endofpacket : std_logic; -- cmd_xbar_demux_001:src7_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src7_valid : std_logic; -- cmd_xbar_demux_001:src7_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src7_startofpacket : std_logic; -- cmd_xbar_demux_001:src7_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src7_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src7_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src7_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src7_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src8_endofpacket : std_logic; -- cmd_xbar_demux_001:src8_endofpacket -> width_adapter_004:in_endofpacket
signal cmd_xbar_demux_001_src8_valid : std_logic; -- cmd_xbar_demux_001:src8_valid -> width_adapter_004:in_valid
signal cmd_xbar_demux_001_src8_startofpacket : std_logic; -- cmd_xbar_demux_001:src8_startofpacket -> width_adapter_004:in_startofpacket
signal cmd_xbar_demux_001_src8_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src8_data -> width_adapter_004:in_data
signal cmd_xbar_demux_001_src8_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src8_channel -> width_adapter_004:in_channel
signal cmd_xbar_demux_001_src9_endofpacket : std_logic; -- cmd_xbar_demux_001:src9_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src9_valid : std_logic; -- cmd_xbar_demux_001:src9_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src9_startofpacket : std_logic; -- cmd_xbar_demux_001:src9_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src9_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src9_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src9_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src9_channel -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src10_endofpacket : std_logic; -- cmd_xbar_demux_001:src10_endofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src10_valid : std_logic; -- cmd_xbar_demux_001:src10_valid -> switch_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src10_startofpacket : std_logic; -- cmd_xbar_demux_001:src10_startofpacket -> switch_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src10_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src10_data -> switch_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src10_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src10_channel -> switch_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src11_endofpacket : std_logic; -- cmd_xbar_demux_001:src11_endofpacket -> width_adapter_006:in_endofpacket
signal cmd_xbar_demux_001_src11_valid : std_logic; -- cmd_xbar_demux_001:src11_valid -> width_adapter_006:in_valid
signal cmd_xbar_demux_001_src11_startofpacket : std_logic; -- cmd_xbar_demux_001:src11_startofpacket -> width_adapter_006:in_startofpacket
signal cmd_xbar_demux_001_src11_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src11_data -> width_adapter_006:in_data
signal cmd_xbar_demux_001_src11_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src11_channel -> width_adapter_006:in_channel
signal cmd_xbar_demux_001_src12_endofpacket : std_logic; -- cmd_xbar_demux_001:src12_endofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_demux_001_src12_valid : std_logic; -- cmd_xbar_demux_001:src12_valid -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_demux_001_src12_startofpacket : std_logic; -- cmd_xbar_demux_001:src12_startofpacket -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_demux_001_src12_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src12_data -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_demux_001_src12_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src12_channel -> switch_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
signal rsp_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
signal rsp_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
signal rsp_xbar_demux_src1_endofpacket : std_logic; -- rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
signal rsp_xbar_demux_src1_valid : std_logic; -- rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
signal rsp_xbar_demux_src1_startofpacket : std_logic; -- rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
signal rsp_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
signal rsp_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
signal rsp_xbar_demux_src1_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
signal rsp_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
signal rsp_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
signal rsp_xbar_demux_001_src1_endofpacket : std_logic; -- rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
signal rsp_xbar_demux_001_src1_valid : std_logic; -- rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
signal rsp_xbar_demux_001_src1_startofpacket : std_logic; -- rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
signal rsp_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
signal rsp_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
signal rsp_xbar_demux_001_src1_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
signal rsp_xbar_demux_002_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
signal rsp_xbar_demux_002_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
signal rsp_xbar_demux_002_src1_endofpacket : std_logic; -- rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
signal rsp_xbar_demux_002_src1_valid : std_logic; -- rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid
signal rsp_xbar_demux_002_src1_startofpacket : std_logic; -- rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
signal rsp_xbar_demux_002_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data
signal rsp_xbar_demux_002_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel
signal rsp_xbar_demux_002_src1_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready
signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
signal rsp_xbar_demux_003_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
signal rsp_xbar_demux_003_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
signal rsp_xbar_demux_003_src1_endofpacket : std_logic; -- rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
signal rsp_xbar_demux_003_src1_valid : std_logic; -- rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid
signal rsp_xbar_demux_003_src1_startofpacket : std_logic; -- rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
signal rsp_xbar_demux_003_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data
signal rsp_xbar_demux_003_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel
signal rsp_xbar_demux_003_src1_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready
signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
signal rsp_xbar_demux_005_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
signal rsp_xbar_demux_005_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
signal rsp_xbar_demux_006_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
signal rsp_xbar_demux_006_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
signal rsp_xbar_demux_007_src0_endofpacket : std_logic; -- rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
signal rsp_xbar_demux_007_src0_valid : std_logic; -- rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
signal rsp_xbar_demux_007_src0_startofpacket : std_logic; -- rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
signal rsp_xbar_demux_007_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
signal rsp_xbar_demux_007_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
signal rsp_xbar_demux_007_src0_ready : std_logic; -- rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
signal rsp_xbar_demux_008_src0_endofpacket : std_logic; -- rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket
signal rsp_xbar_demux_008_src0_valid : std_logic; -- rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid
signal rsp_xbar_demux_008_src0_startofpacket : std_logic; -- rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket
signal rsp_xbar_demux_008_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data
signal rsp_xbar_demux_008_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel
signal rsp_xbar_demux_008_src0_ready : std_logic; -- rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready
signal rsp_xbar_demux_009_src0_endofpacket : std_logic; -- rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket
signal rsp_xbar_demux_009_src0_valid : std_logic; -- rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid
signal rsp_xbar_demux_009_src0_startofpacket : std_logic; -- rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket
signal rsp_xbar_demux_009_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data
signal rsp_xbar_demux_009_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel
signal rsp_xbar_demux_009_src0_ready : std_logic; -- rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready
signal rsp_xbar_demux_010_src0_endofpacket : std_logic; -- rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket
signal rsp_xbar_demux_010_src0_valid : std_logic; -- rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid
signal rsp_xbar_demux_010_src0_startofpacket : std_logic; -- rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket
signal rsp_xbar_demux_010_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data
signal rsp_xbar_demux_010_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel
signal rsp_xbar_demux_010_src0_ready : std_logic; -- rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready
signal rsp_xbar_demux_011_src0_endofpacket : std_logic; -- rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket
signal rsp_xbar_demux_011_src0_valid : std_logic; -- rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid
signal rsp_xbar_demux_011_src0_startofpacket : std_logic; -- rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket
signal rsp_xbar_demux_011_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data
signal rsp_xbar_demux_011_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel
signal rsp_xbar_demux_011_src0_ready : std_logic; -- rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready
signal rsp_xbar_demux_012_src0_endofpacket : std_logic; -- rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket
signal rsp_xbar_demux_012_src0_valid : std_logic; -- rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid
signal rsp_xbar_demux_012_src0_startofpacket : std_logic; -- rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket
signal rsp_xbar_demux_012_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data
signal rsp_xbar_demux_012_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel
signal rsp_xbar_demux_012_src0_ready : std_logic; -- rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready
signal limiter_cmd_src_endofpacket : std_logic; -- limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
signal limiter_cmd_src_startofpacket : std_logic; -- limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
signal limiter_cmd_src_data : std_logic_vector(99 downto 0); -- limiter:cmd_src_data -> cmd_xbar_demux:sink_data
signal limiter_cmd_src_channel : std_logic_vector(12 downto 0); -- limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
signal limiter_cmd_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
signal rsp_xbar_mux_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux:src_data -> limiter:rsp_sink_data
signal rsp_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
signal rsp_xbar_mux_src_ready : std_logic; -- limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
signal limiter_001_cmd_src_endofpacket : std_logic; -- limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
signal limiter_001_cmd_src_startofpacket : std_logic; -- limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
signal limiter_001_cmd_src_data : std_logic_vector(99 downto 0); -- limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
signal limiter_001_cmd_src_channel : std_logic_vector(12 downto 0); -- limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
signal limiter_001_cmd_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
signal rsp_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
signal rsp_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
signal rsp_xbar_mux_001_src_ready : std_logic; -- limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
signal cmd_xbar_mux_src_endofpacket : std_logic; -- cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_src_valid : std_logic; -- cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_src_startofpacket : std_logic; -- cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid
signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
signal id_router_src_data : std_logic_vector(99 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data
signal id_router_src_channel : std_logic_vector(12 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel
signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready
signal cmd_xbar_mux_001_src_endofpacket : std_logic; -- cmd_xbar_mux_001:src_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal cmd_xbar_mux_001_src_valid : std_logic; -- cmd_xbar_mux_001:src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
signal cmd_xbar_mux_001_src_startofpacket : std_logic; -- cmd_xbar_mux_001:src_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal cmd_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_001:src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data
signal cmd_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_001:src_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_mux_001_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_001:src_ready
signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
signal id_router_001_src_data : std_logic_vector(99 downto 0); -- id_router_001:src_data -> rsp_xbar_demux_001:sink_data
signal id_router_001_src_channel : std_logic_vector(12 downto 0); -- id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
signal id_router_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
signal crosser_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
signal id_router_004_src_data : std_logic_vector(99 downto 0); -- id_router_004:src_data -> rsp_xbar_demux_004:sink_data
signal id_router_004_src_channel : std_logic_vector(12 downto 0); -- id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
signal id_router_004_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
signal cmd_xbar_demux_001_src5_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
signal id_router_005_src_data : std_logic_vector(99 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data
signal id_router_005_src_channel : std_logic_vector(12 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
signal cmd_xbar_demux_001_src6_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
signal id_router_006_src_data : std_logic_vector(99 downto 0); -- id_router_006:src_data -> rsp_xbar_demux_006:sink_data
signal id_router_006_src_channel : std_logic_vector(12 downto 0); -- id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
signal id_router_006_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
signal cmd_xbar_demux_001_src7_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
signal id_router_007_src_endofpacket : std_logic; -- id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
signal id_router_007_src_valid : std_logic; -- id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
signal id_router_007_src_startofpacket : std_logic; -- id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
signal id_router_007_src_data : std_logic_vector(99 downto 0); -- id_router_007:src_data -> rsp_xbar_demux_007:sink_data
signal id_router_007_src_channel : std_logic_vector(12 downto 0); -- id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
signal id_router_007_src_ready : std_logic; -- rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
signal cmd_xbar_demux_001_src9_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready
signal id_router_009_src_endofpacket : std_logic; -- id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
signal id_router_009_src_valid : std_logic; -- id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
signal id_router_009_src_startofpacket : std_logic; -- id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
signal id_router_009_src_data : std_logic_vector(99 downto 0); -- id_router_009:src_data -> rsp_xbar_demux_009:sink_data
signal id_router_009_src_channel : std_logic_vector(12 downto 0); -- id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
signal id_router_009_src_ready : std_logic; -- rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
signal cmd_xbar_demux_001_src10_ready : std_logic; -- switch_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready
signal id_router_010_src_endofpacket : std_logic; -- id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
signal id_router_010_src_valid : std_logic; -- id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
signal id_router_010_src_startofpacket : std_logic; -- id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
signal id_router_010_src_data : std_logic_vector(99 downto 0); -- id_router_010:src_data -> rsp_xbar_demux_010:sink_data
signal id_router_010_src_channel : std_logic_vector(12 downto 0); -- id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
signal id_router_010_src_ready : std_logic; -- rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
signal cmd_xbar_demux_001_src12_ready : std_logic; -- switch_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready
signal id_router_012_src_endofpacket : std_logic; -- id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket
signal id_router_012_src_valid : std_logic; -- id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid
signal id_router_012_src_startofpacket : std_logic; -- id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket
signal id_router_012_src_data : std_logic_vector(99 downto 0); -- id_router_012:src_data -> rsp_xbar_demux_012:sink_data
signal id_router_012_src_channel : std_logic_vector(12 downto 0); -- id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel
signal id_router_012_src_ready : std_logic; -- rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready
signal cmd_xbar_mux_002_src_endofpacket : std_logic; -- cmd_xbar_mux_002:src_endofpacket -> width_adapter:in_endofpacket
signal cmd_xbar_mux_002_src_valid : std_logic; -- cmd_xbar_mux_002:src_valid -> width_adapter:in_valid
signal cmd_xbar_mux_002_src_startofpacket : std_logic; -- cmd_xbar_mux_002:src_startofpacket -> width_adapter:in_startofpacket
signal cmd_xbar_mux_002_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_002:src_data -> width_adapter:in_data
signal cmd_xbar_mux_002_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_002:src_channel -> width_adapter:in_channel
signal cmd_xbar_mux_002_src_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_mux_002:src_ready
signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> burst_adapter:sink0_valid
signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
signal width_adapter_src_data : std_logic_vector(81 downto 0); -- width_adapter:out_data -> burst_adapter:sink0_data
signal width_adapter_src_ready : std_logic; -- burst_adapter:sink0_ready -> width_adapter:out_ready
signal width_adapter_src_channel : std_logic_vector(12 downto 0); -- width_adapter:out_channel -> burst_adapter:sink0_channel
signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> width_adapter_001:in_endofpacket
signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> width_adapter_001:in_valid
signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> width_adapter_001:in_startofpacket
signal id_router_002_src_data : std_logic_vector(81 downto 0); -- id_router_002:src_data -> width_adapter_001:in_data
signal id_router_002_src_channel : std_logic_vector(12 downto 0); -- id_router_002:src_channel -> width_adapter_001:in_channel
signal id_router_002_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router_002:src_ready
signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux_002:sink_valid
signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
signal width_adapter_001_src_data : std_logic_vector(99 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux_002:sink_data
signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> width_adapter_001:out_ready
signal width_adapter_001_src_channel : std_logic_vector(12 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux_002:sink_channel
signal cmd_xbar_mux_003_src_endofpacket : std_logic; -- cmd_xbar_mux_003:src_endofpacket -> width_adapter_002:in_endofpacket
signal cmd_xbar_mux_003_src_valid : std_logic; -- cmd_xbar_mux_003:src_valid -> width_adapter_002:in_valid
signal cmd_xbar_mux_003_src_startofpacket : std_logic; -- cmd_xbar_mux_003:src_startofpacket -> width_adapter_002:in_startofpacket
signal cmd_xbar_mux_003_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_003:src_data -> width_adapter_002:in_data
signal cmd_xbar_mux_003_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_003:src_channel -> width_adapter_002:in_channel
signal cmd_xbar_mux_003_src_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_mux_003:src_ready
signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> burst_adapter_001:sink0_endofpacket
signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> burst_adapter_001:sink0_valid
signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> burst_adapter_001:sink0_startofpacket
signal width_adapter_002_src_data : std_logic_vector(81 downto 0); -- width_adapter_002:out_data -> burst_adapter_001:sink0_data
signal width_adapter_002_src_ready : std_logic; -- burst_adapter_001:sink0_ready -> width_adapter_002:out_ready
signal width_adapter_002_src_channel : std_logic_vector(12 downto 0); -- width_adapter_002:out_channel -> burst_adapter_001:sink0_channel
signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket
signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_003:in_valid
signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket
signal id_router_003_src_data : std_logic_vector(81 downto 0); -- id_router_003:src_data -> width_adapter_003:in_data
signal id_router_003_src_channel : std_logic_vector(12 downto 0); -- id_router_003:src_channel -> width_adapter_003:in_channel
signal id_router_003_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_003:src_ready
signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid
signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
signal width_adapter_003_src_data : std_logic_vector(99 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data
signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready
signal width_adapter_003_src_channel : std_logic_vector(12 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel
signal cmd_xbar_demux_001_src8_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_demux_001:src8_ready
signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> burst_adapter_002:sink0_endofpacket
signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> burst_adapter_002:sink0_valid
signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> burst_adapter_002:sink0_startofpacket
signal width_adapter_004_src_data : std_logic_vector(72 downto 0); -- width_adapter_004:out_data -> burst_adapter_002:sink0_data
signal width_adapter_004_src_ready : std_logic; -- burst_adapter_002:sink0_ready -> width_adapter_004:out_ready
signal width_adapter_004_src_channel : std_logic_vector(12 downto 0); -- width_adapter_004:out_channel -> burst_adapter_002:sink0_channel
signal id_router_008_src_endofpacket : std_logic; -- id_router_008:src_endofpacket -> width_adapter_005:in_endofpacket
signal id_router_008_src_valid : std_logic; -- id_router_008:src_valid -> width_adapter_005:in_valid
signal id_router_008_src_startofpacket : std_logic; -- id_router_008:src_startofpacket -> width_adapter_005:in_startofpacket
signal id_router_008_src_data : std_logic_vector(72 downto 0); -- id_router_008:src_data -> width_adapter_005:in_data
signal id_router_008_src_channel : std_logic_vector(12 downto 0); -- id_router_008:src_channel -> width_adapter_005:in_channel
signal id_router_008_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_008:src_ready
signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_008:sink_valid
signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
signal width_adapter_005_src_data : std_logic_vector(99 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_008:sink_data
signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_008:sink_ready -> width_adapter_005:out_ready
signal width_adapter_005_src_channel : std_logic_vector(12 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_008:sink_channel
signal cmd_xbar_demux_001_src11_ready : std_logic; -- width_adapter_006:in_ready -> cmd_xbar_demux_001:src11_ready
signal width_adapter_006_src_endofpacket : std_logic; -- width_adapter_006:out_endofpacket -> burst_adapter_003:sink0_endofpacket
signal width_adapter_006_src_valid : std_logic; -- width_adapter_006:out_valid -> burst_adapter_003:sink0_valid
signal width_adapter_006_src_startofpacket : std_logic; -- width_adapter_006:out_startofpacket -> burst_adapter_003:sink0_startofpacket
signal width_adapter_006_src_data : std_logic_vector(72 downto 0); -- width_adapter_006:out_data -> burst_adapter_003:sink0_data
signal width_adapter_006_src_ready : std_logic; -- burst_adapter_003:sink0_ready -> width_adapter_006:out_ready
signal width_adapter_006_src_channel : std_logic_vector(12 downto 0); -- width_adapter_006:out_channel -> burst_adapter_003:sink0_channel
signal id_router_011_src_endofpacket : std_logic; -- id_router_011:src_endofpacket -> width_adapter_007:in_endofpacket
signal id_router_011_src_valid : std_logic; -- id_router_011:src_valid -> width_adapter_007:in_valid
signal id_router_011_src_startofpacket : std_logic; -- id_router_011:src_startofpacket -> width_adapter_007:in_startofpacket
signal id_router_011_src_data : std_logic_vector(72 downto 0); -- id_router_011:src_data -> width_adapter_007:in_data
signal id_router_011_src_channel : std_logic_vector(12 downto 0); -- id_router_011:src_channel -> width_adapter_007:in_channel
signal id_router_011_src_ready : std_logic; -- width_adapter_007:in_ready -> id_router_011:src_ready
signal width_adapter_007_src_endofpacket : std_logic; -- width_adapter_007:out_endofpacket -> rsp_xbar_demux_011:sink_endofpacket
signal width_adapter_007_src_valid : std_logic; -- width_adapter_007:out_valid -> rsp_xbar_demux_011:sink_valid
signal width_adapter_007_src_startofpacket : std_logic; -- width_adapter_007:out_startofpacket -> rsp_xbar_demux_011:sink_startofpacket
signal width_adapter_007_src_data : std_logic_vector(99 downto 0); -- width_adapter_007:out_data -> rsp_xbar_demux_011:sink_data
signal width_adapter_007_src_ready : std_logic; -- rsp_xbar_demux_011:sink_ready -> width_adapter_007:out_ready
signal width_adapter_007_src_channel : std_logic_vector(12 downto 0); -- width_adapter_007:out_channel -> rsp_xbar_demux_011:sink_channel
signal crosser_out_endofpacket : std_logic; -- crosser:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
signal crosser_out_valid : std_logic; -- crosser:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid
signal crosser_out_startofpacket : std_logic; -- crosser:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
signal crosser_out_data : std_logic_vector(99 downto 0); -- crosser:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_data
signal crosser_out_channel : std_logic_vector(12 downto 0); -- crosser:out_channel -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel
signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> crosser:in_endofpacket
signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> crosser:in_valid
signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> crosser:in_startofpacket
signal cmd_xbar_demux_001_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src4_data -> crosser:in_data
signal cmd_xbar_demux_001_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src4_channel -> crosser:in_channel
signal cmd_xbar_demux_001_src4_ready : std_logic; -- crosser:in_ready -> cmd_xbar_demux_001:src4_ready
signal crosser_001_out_endofpacket : std_logic; -- crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
signal crosser_001_out_valid : std_logic; -- crosser_001:out_valid -> rsp_xbar_mux_001:sink4_valid
signal crosser_001_out_startofpacket : std_logic; -- crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
signal crosser_001_out_data : std_logic_vector(99 downto 0); -- crosser_001:out_data -> rsp_xbar_mux_001:sink4_data
signal crosser_001_out_channel : std_logic_vector(12 downto 0); -- crosser_001:out_channel -> rsp_xbar_mux_001:sink4_channel
signal crosser_001_out_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> crosser_001:out_ready
signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> crosser_001:in_endofpacket
signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> crosser_001:in_valid
signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> crosser_001:in_startofpacket
signal rsp_xbar_demux_004_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src0_data -> crosser_001:in_data
signal rsp_xbar_demux_004_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src0_channel -> crosser_001:in_channel
signal rsp_xbar_demux_004_src0_ready : std_logic; -- crosser_001:in_ready -> rsp_xbar_demux_004:src0_ready
signal limiter_cmd_valid_data : std_logic_vector(12 downto 0); -- limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
signal limiter_001_cmd_valid_data : std_logic_vector(12 downto 0); -- limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
signal irq_mapper_receiver0_irq : std_logic; -- timer_0:irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver1_irq
signal nios2_qsys_0_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_qsys_0:d_irq
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_write:inv -> sdram_0:az_wr_n
signal sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_read:inv -> sdram_0:az_rd_n
signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_anti_slave_0_byteenable:inv -> sdram_0:az_be_n
signal timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- timer_0_s1_translator_avalon_anti_slave_0_write:inv -> timer_0:write_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:inv -> jtag_uart_0:av_write_n
signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:inv -> jtag_uart_0:av_read_n
signal green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- green_leds_s1_translator_avalon_anti_slave_0_write:inv -> green_leds:write_n
signal servo_pwm_0_s0_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- servo_pwm_0_s0_translator_avalon_anti_slave_0_write:inv -> servo_pwm_0:avs_s0_write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [green_leds:reset_n, jtag_uart_0:rst_n, nios2_qsys_0:reset_n, sdram_0:reset_n, servo_pwm_0:reset_n, switch:reset_n, switch_0:reset_n, sysid_qsys_0:reset_n, timer_0:reset_n]
begin
nios2_qsys_0 : component tracking_camera_system_nios2_qsys_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
d_address => nios2_qsys_0_data_master_address, -- data_master.address
d_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
d_read => nios2_qsys_0_data_master_read, -- .read
d_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_qsys_0_data_master_write, -- .write
d_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
d_readdatavalid => nios2_qsys_0_data_master_readdatavalid, -- .readdatavalid
jtag_debug_module_debugaccess_to_roms => nios2_qsys_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_qsys_0_instruction_master_address, -- instruction_master.address
i_read => nios2_qsys_0_instruction_master_read, -- .read
i_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
i_readdatavalid => nios2_qsys_0_instruction_master_readdatavalid, -- .readdatavalid
d_irq => nios2_qsys_0_d_irq_irq, -- d_irq.irq
jtag_debug_module_resetrequest => nios2_qsys_0_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset
jtag_debug_module_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- jtag_debug_module.address
jtag_debug_module_begintransfer => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
jtag_debug_module_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
jtag_debug_module_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
jtag_debug_module_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
jtag_debug_module_select => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
jtag_debug_module_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
jtag_debug_module_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
no_ci_readra => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component tracking_camera_system_onchip_memory2_0
port map (
clk => altpll_0_c1_clk, -- clk1.clk
address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset -- reset1.reset
);
sysid_qsys_0 : component tracking_camera_system_sysid_qsys_0
port map (
clock => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- control_slave.readdata
address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address(0) -- .address
);
timer_0 : component tracking_camera_system_timer_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => timer_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
write_n => timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
irq => irq_mapper_receiver0_irq -- irq.irq
);
jtag_uart_0 : component tracking_camera_system_jtag_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- avalon_jtag_slave.chipselect
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address(0), -- .address
av_read_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver1_irq -- irq.irq
);
character_lcd_0 : component tracking_camera_system_character_lcd_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
address => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address(0), -- avalon_lcd_slave.address
chipselect => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
read => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read, -- .read
write => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
LCD_DATA => character_lcd_0_external_interface_DATA, -- external_interface.export
LCD_ON => character_lcd_0_external_interface_ON, -- .export
LCD_BLON => character_lcd_0_external_interface_BLON, -- .export
LCD_EN => character_lcd_0_external_interface_EN, -- .export
LCD_RS => character_lcd_0_external_interface_RS, -- .export
LCD_RW => character_lcd_0_external_interface_RW -- .export
);
green_leds : component tracking_camera_system_green_leds
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => green_leds_s1_translator_avalon_anti_slave_0_address, -- s1.address
write_n => green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
out_port => green_leds_external_connection_export -- external_connection.export
);
switch : component tracking_camera_system_switch
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => switch_s1_translator_avalon_anti_slave_0_address, -- s1.address
readdata => switch_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
in_port => switch_external_connection_export -- external_connection.export
);
altpll_0 : component tracking_camera_system_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset
read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- pll_slave.read
write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- .address
readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
sdram_0 : component tracking_camera_system_sdram_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => sdram_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
az_be_n => sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv, -- .byteenable_n
az_cs => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
az_data => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
az_rd_n => sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n
az_wr_n => sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n
za_data => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
za_valid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
za_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
zs_addr => sdram_0_wire_addr, -- wire.export
zs_ba => sdram_0_wire_ba, -- .export
zs_cas_n => sdram_0_wire_cas_n, -- .export
zs_cke => sdram_0_wire_cke, -- .export
zs_cs_n => sdram_0_wire_cs_n, -- .export
zs_dq => sdram_0_wire_dq, -- .export
zs_dqm => sdram_0_wire_dqm, -- .export
zs_ras_n => sdram_0_wire_ras_n, -- .export
zs_we_n => sdram_0_wire_we_n -- .export
);
sram_0 : component tracking_camera_system_sram_0
port map (
clk => altpll_0_c1_clk, -- clock_reset.clk
reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset
SRAM_DQ => sram_0_external_interface_DQ, -- external_interface.export
SRAM_ADDR => sram_0_external_interface_ADDR, -- .export
SRAM_LB_N => sram_0_external_interface_LB_N, -- .export
SRAM_UB_N => sram_0_external_interface_UB_N, -- .export
SRAM_CE_N => sram_0_external_interface_CE_N, -- .export
SRAM_OE_N => sram_0_external_interface_OE_N, -- .export
SRAM_WE_N => sram_0_external_interface_WE_N, -- .export
address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_sram_slave.address
byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid -- .readdatavalid
);
servo_pwm_0 : component tracking_camera_system_servo_pwm_0
port map (
clk => altpll_0_c1_clk, -- clock.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
coe_servo => servo_pwm_0_conduit_end_0_export, -- conduit_end_0.export
avs_s0_write_n => servo_pwm_0_s0_translator_avalon_anti_slave_0_write_ports_inv, -- s0.write_n
avs_s0_writedata => servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata -- .writedata
);
switch_0 : component tracking_camera_system_switch
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => switch_0_s1_translator_avalon_anti_slave_0_address, -- s1.address
readdata => switch_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
in_port => switch_0_external_connection_export -- external_connection.export
);
nios2_qsys_0_instruction_master_translator : component tracking_camera_system_nios2_qsys_0_instruction_master_translator
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_instruction_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest
av_read => nios2_qsys_0_instruction_master_read, -- .read
av_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata
av_readdatavalid => nios2_qsys_0_instruction_master_readdatavalid -- .readdatavalid
);
nios2_qsys_0_data_master_translator : component tracking_camera_system_nios2_qsys_0_data_master_translator
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address
uav_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
uav_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
uav_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
uav_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_data_master_address, -- avalon_anti_master_0.address
av_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest
av_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable
av_read => nios2_qsys_0_data_master_read, -- .read
av_readdata => nios2_qsys_0_data_master_readdata, -- .readdata
av_readdatavalid => nios2_qsys_0_data_master_readdatavalid, -- .readdatavalid
av_write => nios2_qsys_0_data_master_write, -- .write
av_writedata => nios2_qsys_0_data_master_writedata, -- .writedata
av_debugaccess => nios2_qsys_0_data_master_debugaccess -- .debugaccess
);
nios2_qsys_0_jtag_debug_module_translator : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator
generic map (
AV_ADDRESS_W => 9,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write
av_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer, -- .begintransfer
av_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess
av_read => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_outputenable => open -- (terminated)
);
onchip_memory2_0_s1_translator : component tracking_camera_system_onchip_memory2_0_s1_translator
generic map (
AV_ADDRESS_W => 12,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 1,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
sdram_0_s1_translator : component tracking_camera_system_sdram_0_s1_translator
generic map (
AV_ADDRESS_W => 22,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sdram_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sdram_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_read => sdram_0_s1_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sdram_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
sram_0_avalon_sram_slave_translator : component tracking_camera_system_sram_0_avalon_sram_slave_translator
generic map (
AV_ADDRESS_W => 18,
AV_DATA_W => 16,
UAV_DATA_W => 16,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 2,
UAV_BYTEENABLE_W => 2,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 2,
AV_READLATENCY => 0,
USE_READDATAVALID => 1,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 2,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable
av_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
altpll_0_pll_slave_translator : component tracking_camera_system_altpll_0_pll_slave_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 0,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- reset.reset
uav_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
sysid_qsys_0_control_slave_translator : component tracking_camera_system_sysid_qsys_0_control_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 4,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
timer_0_s1_translator : component tracking_camera_system_timer_0_s1_translator
generic map (
AV_ADDRESS_W => 3,
AV_DATA_W => 16,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => timer_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => timer_0_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
jtag_uart_0_avalon_jtag_slave_translator : component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
character_lcd_0_avalon_lcd_slave_translator : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 8,
UAV_DATA_W => 8,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 1,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 1,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 1,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 1,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount(0) => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable(0) => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_write, -- .write
av_read => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_read, -- .read
av_readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_writedata, -- .writedata
av_waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest
av_chipselect => character_lcd_0_avalon_lcd_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
green_leds_s1_translator : component tracking_camera_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => green_leds_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_write => green_leds_s1_translator_avalon_anti_slave_0_write, -- .write
av_readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata
av_chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
switch_s1_translator : component tracking_camera_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => switch_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => switch_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => switch_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => switch_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => switch_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => switch_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
servo_pwm_0_s0_translator : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator
generic map (
AV_ADDRESS_W => 1,
AV_DATA_W => 8,
UAV_DATA_W => 8,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 1,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 1,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 1,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount(0) => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable(0) => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_write => servo_pwm_0_s0_translator_avalon_anti_slave_0_write, -- avalon_anti_slave_0.write
av_writedata => servo_pwm_0_s0_translator_avalon_anti_slave_0_writedata, -- .writedata
av_address => open, -- (terminated)
av_read => open, -- (terminated)
av_readdata => "10101101", -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
switch_0_s1_translator : component tracking_camera_system_green_leds_s1_translator
generic map (
AV_ADDRESS_W => 2,
AV_DATA_W => 32,
UAV_DATA_W => 32,
AV_BURSTCOUNT_W => 1,
AV_BYTEENABLE_W => 1,
UAV_BYTEENABLE_W => 4,
UAV_ADDRESS_W => 25,
UAV_BURSTCOUNT_W => 3,
AV_READLATENCY => 0,
USE_READDATAVALID => 0,
USE_WAITREQUEST => 0,
USE_UAV_CLKEN => 0,
AV_SYMBOLS_PER_WORD => 4,
AV_ADDRESS_SYMBOLS => 0,
AV_BURSTCOUNT_SYMBOLS => 0,
AV_CONSTANT_BURST_BEHAVIOR => 0,
UAV_CONSTANT_BURST_BEHAVIOR => 0,
AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
CHIPSELECT_THROUGH_READLATENCY => 0,
AV_READ_WAIT_CYCLES => 1,
AV_WRITE_WAIT_CYCLES => 0,
AV_SETUP_WAIT_CYCLES => 0,
AV_DATA_HOLD_CYCLES => 0
)
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
uav_address => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address
uav_burstcount => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
uav_read => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
uav_write => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
uav_waitrequest => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
uav_readdatavalid => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
uav_byteenable => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
uav_readdata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
uav_writedata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
uav_lock => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
uav_debugaccess => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
av_address => switch_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address
av_readdata => switch_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata
av_write => open, -- (terminated)
av_read => open, -- (terminated)
av_writedata => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent : component tracking_camera_system_nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => limiter_rsp_src_valid, -- rp.valid
rp_data => limiter_rsp_src_data, -- .data
rp_channel => limiter_rsp_src_channel, -- .channel
rp_startofpacket => limiter_rsp_src_startofpacket, -- .startofpacket
rp_endofpacket => limiter_rsp_src_endofpacket, -- .endofpacket
rp_ready => limiter_rsp_src_ready -- .ready
);
nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent : component tracking_camera_system_nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
av_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- av.address
av_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write
av_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read
av_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata
av_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata
av_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest
av_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid
av_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable
av_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount
av_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess
av_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock
cp_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid
cp_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
cp_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
cp_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
cp_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready
rp_valid => limiter_001_rsp_src_valid, -- rp.valid
rp_data => limiter_001_rsp_src_data, -- .data
rp_channel => limiter_001_rsp_src_channel, -- .channel
rp_startofpacket => limiter_001_rsp_src_startofpacket, -- .startofpacket
rp_endofpacket => limiter_001_rsp_src_endofpacket, -- .endofpacket
rp_ready => limiter_001_rsp_src_ready -- .ready
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_src_valid, -- .valid
cp_data => cmd_xbar_mux_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_src_channel, -- .channel
rf_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_mux_001_src_ready, -- cp.ready
cp_valid => cmd_xbar_mux_001_src_valid, -- .valid
cp_data => cmd_xbar_mux_001_src_data, -- .data
cp_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_mux_001_src_channel, -- .channel
rf_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
sdram_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_source0_ready, -- cp.ready
cp_valid => burst_adapter_source0_valid, -- .valid
cp_data => burst_adapter_source0_data, -- .data
cp_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_source0_channel, -- .channel
rf_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_001_source0_ready, -- cp.ready
cp_valid => burst_adapter_001_source0_valid, -- .valid
cp_data => burst_adapter_001_source0_data, -- .data
cp_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_001_source0_channel, -- .channel
rf_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
m0_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => crosser_out_ready, -- cp.ready
cp_valid => crosser_out_valid, -- .valid
cp_data => crosser_out_data, -- .data
cp_startofpacket => crosser_out_startofpacket, -- .startofpacket
cp_endofpacket => crosser_out_endofpacket, -- .endofpacket
cp_channel => crosser_out_channel, -- .channel
rf_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
rdata_fifo_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data
rdata_fifo_src_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component tracking_camera_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data
in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready
out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data
out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid
out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready -- .ready
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid
cp_data => cmd_xbar_demux_001_src5_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel
rf_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
timer_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_timer_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src6_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src6_valid, -- .valid
cp_data => cmd_xbar_demux_001_src6_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src6_channel, -- .channel
rf_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src7_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src7_valid, -- .valid
cp_data => cmd_xbar_demux_001_src7_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src7_channel, -- .channel
rf_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_002_source0_ready, -- cp.ready
cp_valid => burst_adapter_002_source0_valid, -- .valid
cp_data => burst_adapter_002_source0_data, -- .data
cp_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_002_source0_channel, -- .channel
rf_sink_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
green_leds_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_green_leds_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src9_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src9_valid, -- .valid
cp_data => cmd_xbar_demux_001_src9_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src9_channel, -- .channel
rf_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
switch_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_switch_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => switch_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => switch_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => switch_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => switch_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => switch_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => switch_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => switch_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => switch_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => switch_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => switch_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => switch_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => switch_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => switch_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src10_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src10_valid, -- .valid
cp_data => cmd_xbar_demux_001_src10_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src10_channel, -- .channel
rf_sink_ready => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => switch_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
servo_pwm_0_s0_translator_avalon_universal_slave_0_agent : component tracking_camera_system_servo_pwm_0_s0_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => burst_adapter_003_source0_ready, -- cp.ready
cp_valid => burst_adapter_003_source0_valid, -- .valid
cp_data => burst_adapter_003_source0_data, -- .data
cp_startofpacket => burst_adapter_003_source0_startofpacket, -- .startofpacket
cp_endofpacket => burst_adapter_003_source0_endofpacket, -- .endofpacket
cp_channel => burst_adapter_003_source0_channel, -- .channel
rf_sink_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
switch_0_s1_translator_avalon_universal_slave_0_agent : component tracking_camera_system_switch_0_s1_translator_avalon_universal_slave_0_agent
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
m0_address => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address
m0_burstcount => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount
m0_byteenable => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable
m0_debugaccess => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess
m0_lock => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock
m0_readdata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata
m0_readdatavalid => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid
m0_read => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read
m0_waitrequest => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest
m0_writedata => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata
m0_write => switch_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write
rp_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket
rp_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready
rp_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
rp_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
rp_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
cp_ready => cmd_xbar_demux_001_src12_ready, -- cp.ready
cp_valid => cmd_xbar_demux_001_src12_valid, -- .valid
cp_data => cmd_xbar_demux_001_src12_data, -- .data
cp_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
cp_endofpacket => cmd_xbar_demux_001_src12_endofpacket, -- .endofpacket
cp_channel => cmd_xbar_demux_001_src12_channel, -- .channel
rf_sink_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready
rf_sink_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
rf_sink_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
rf_sink_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket
rf_sink_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data
rf_source_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready
rf_source_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
rf_source_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
rf_source_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
rf_source_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data
rdata_fifo_sink_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready
rdata_fifo_sink_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_sink_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data
rdata_fifo_src_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready
rdata_fifo_src_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid
rdata_fifo_src_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data -- .data
);
switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component tracking_camera_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data
in_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid
in_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready
in_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket
in_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket
out_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data
out_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid
out_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready
out_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket
out_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket -- .endofpacket
);
addr_router : component tracking_camera_system_addr_router
port map (
sink_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_src_ready, -- src.ready
src_valid => addr_router_src_valid, -- .valid
src_data => addr_router_src_data, -- .data
src_channel => addr_router_src_channel, -- .channel
src_startofpacket => addr_router_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_src_endofpacket -- .endofpacket
);
addr_router_001 : component tracking_camera_system_addr_router_001
port map (
sink_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready
sink_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid
sink_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data
sink_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => addr_router_001_src_ready, -- src.ready
src_valid => addr_router_001_src_valid, -- .valid
src_data => addr_router_001_src_data, -- .data
src_channel => addr_router_001_src_channel, -- .channel
src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket
);
id_router : component tracking_camera_system_id_router
port map (
sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_src_ready, -- src.ready
src_valid => id_router_src_valid, -- .valid
src_data => id_router_src_data, -- .data
src_channel => id_router_src_channel, -- .channel
src_startofpacket => id_router_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_src_endofpacket -- .endofpacket
);
id_router_001 : component tracking_camera_system_id_router
port map (
sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_001_src_ready, -- src.ready
src_valid => id_router_001_src_valid, -- .valid
src_data => id_router_001_src_data, -- .data
src_channel => id_router_001_src_channel, -- .channel
src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_001_src_endofpacket -- .endofpacket
);
id_router_002 : component tracking_camera_system_id_router_002
port map (
sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_002_src_ready, -- src.ready
src_valid => id_router_002_src_valid, -- .valid
src_data => id_router_002_src_data, -- .data
src_channel => id_router_002_src_channel, -- .channel
src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_002_src_endofpacket -- .endofpacket
);
id_router_003 : component tracking_camera_system_id_router_002
port map (
sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_003_src_ready, -- src.ready
src_valid => id_router_003_src_valid, -- .valid
src_data => id_router_003_src_data, -- .data
src_channel => id_router_003_src_channel, -- .channel
src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_003_src_endofpacket -- .endofpacket
);
id_router_004 : component tracking_camera_system_id_router_004
port map (
sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
src_ready => id_router_004_src_ready, -- src.ready
src_valid => id_router_004_src_valid, -- .valid
src_data => id_router_004_src_data, -- .data
src_channel => id_router_004_src_channel, -- .channel
src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_004_src_endofpacket -- .endofpacket
);
id_router_005 : component tracking_camera_system_id_router_004
port map (
sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_005_src_ready, -- src.ready
src_valid => id_router_005_src_valid, -- .valid
src_data => id_router_005_src_data, -- .data
src_channel => id_router_005_src_channel, -- .channel
src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_005_src_endofpacket -- .endofpacket
);
id_router_006 : component tracking_camera_system_id_router_004
port map (
sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_006_src_ready, -- src.ready
src_valid => id_router_006_src_valid, -- .valid
src_data => id_router_006_src_data, -- .data
src_channel => id_router_006_src_channel, -- .channel
src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_006_src_endofpacket -- .endofpacket
);
id_router_007 : component tracking_camera_system_id_router_004
port map (
sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_007_src_ready, -- src.ready
src_valid => id_router_007_src_valid, -- .valid
src_data => id_router_007_src_data, -- .data
src_channel => id_router_007_src_channel, -- .channel
src_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_007_src_endofpacket -- .endofpacket
);
id_router_008 : component tracking_camera_system_id_router_008
port map (
sink_ready => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => character_lcd_0_avalon_lcd_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_008_src_ready, -- src.ready
src_valid => id_router_008_src_valid, -- .valid
src_data => id_router_008_src_data, -- .data
src_channel => id_router_008_src_channel, -- .channel
src_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_008_src_endofpacket -- .endofpacket
);
id_router_009 : component tracking_camera_system_id_router_004
port map (
sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_009_src_ready, -- src.ready
src_valid => id_router_009_src_valid, -- .valid
src_data => id_router_009_src_data, -- .data
src_channel => id_router_009_src_channel, -- .channel
src_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_009_src_endofpacket -- .endofpacket
);
id_router_010 : component tracking_camera_system_id_router_004
port map (
sink_ready => switch_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => switch_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => switch_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => switch_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_010_src_ready, -- src.ready
src_valid => id_router_010_src_valid, -- .valid
src_data => id_router_010_src_data, -- .data
src_channel => id_router_010_src_channel, -- .channel
src_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_010_src_endofpacket -- .endofpacket
);
id_router_011 : component tracking_camera_system_id_router_008
port map (
sink_ready => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => servo_pwm_0_s0_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_011_src_ready, -- src.ready
src_valid => id_router_011_src_valid, -- .valid
src_data => id_router_011_src_data, -- .data
src_channel => id_router_011_src_channel, -- .channel
src_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_011_src_endofpacket -- .endofpacket
);
id_router_012 : component tracking_camera_system_id_router_004
port map (
sink_ready => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready
sink_valid => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid
sink_data => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data
sink_startofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket
sink_endofpacket => switch_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => id_router_012_src_ready, -- src.ready
src_valid => id_router_012_src_valid, -- .valid
src_data => id_router_012_src_data, -- .data
src_channel => id_router_012_src_channel, -- .channel
src_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
src_endofpacket => id_router_012_src_endofpacket -- .endofpacket
);
limiter : component tracking_camera_system_limiter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
cmd_sink_ready => addr_router_src_ready, -- cmd_sink.ready
cmd_sink_valid => addr_router_src_valid, -- .valid
cmd_sink_data => addr_router_src_data, -- .data
cmd_sink_channel => addr_router_src_channel, -- .channel
cmd_sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket
cmd_sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket
cmd_src_ready => limiter_cmd_src_ready, -- cmd_src.ready
cmd_src_data => limiter_cmd_src_data, -- .data
cmd_src_channel => limiter_cmd_src_channel, -- .channel
cmd_src_startofpacket => limiter_cmd_src_startofpacket, -- .startofpacket
cmd_src_endofpacket => limiter_cmd_src_endofpacket, -- .endofpacket
rsp_sink_ready => rsp_xbar_mux_src_ready, -- rsp_sink.ready
rsp_sink_valid => rsp_xbar_mux_src_valid, -- .valid
rsp_sink_channel => rsp_xbar_mux_src_channel, -- .channel
rsp_sink_data => rsp_xbar_mux_src_data, -- .data
rsp_sink_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
rsp_sink_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
rsp_src_ready => limiter_rsp_src_ready, -- rsp_src.ready
rsp_src_valid => limiter_rsp_src_valid, -- .valid
rsp_src_data => limiter_rsp_src_data, -- .data
rsp_src_channel => limiter_rsp_src_channel, -- .channel
rsp_src_startofpacket => limiter_rsp_src_startofpacket, -- .startofpacket
rsp_src_endofpacket => limiter_rsp_src_endofpacket, -- .endofpacket
cmd_src_valid => limiter_cmd_valid_data -- cmd_valid.data
);
limiter_001 : component tracking_camera_system_limiter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
cmd_sink_ready => addr_router_001_src_ready, -- cmd_sink.ready
cmd_sink_valid => addr_router_001_src_valid, -- .valid
cmd_sink_data => addr_router_001_src_data, -- .data
cmd_sink_channel => addr_router_001_src_channel, -- .channel
cmd_sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket
cmd_sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket
cmd_src_ready => limiter_001_cmd_src_ready, -- cmd_src.ready
cmd_src_data => limiter_001_cmd_src_data, -- .data
cmd_src_channel => limiter_001_cmd_src_channel, -- .channel
cmd_src_startofpacket => limiter_001_cmd_src_startofpacket, -- .startofpacket
cmd_src_endofpacket => limiter_001_cmd_src_endofpacket, -- .endofpacket
rsp_sink_ready => rsp_xbar_mux_001_src_ready, -- rsp_sink.ready
rsp_sink_valid => rsp_xbar_mux_001_src_valid, -- .valid
rsp_sink_channel => rsp_xbar_mux_001_src_channel, -- .channel
rsp_sink_data => rsp_xbar_mux_001_src_data, -- .data
rsp_sink_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
rsp_sink_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
rsp_src_ready => limiter_001_rsp_src_ready, -- rsp_src.ready
rsp_src_valid => limiter_001_rsp_src_valid, -- .valid
rsp_src_data => limiter_001_rsp_src_data, -- .data
rsp_src_channel => limiter_001_rsp_src_channel, -- .channel
rsp_src_startofpacket => limiter_001_rsp_src_startofpacket, -- .startofpacket
rsp_src_endofpacket => limiter_001_rsp_src_endofpacket, -- .endofpacket
cmd_src_valid => limiter_001_cmd_valid_data -- cmd_valid.data
);
burst_adapter : component tracking_camera_system_burst_adapter
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_src_valid, -- sink0.valid
sink0_data => width_adapter_src_data, -- .data
sink0_channel => width_adapter_src_channel, -- .channel
sink0_startofpacket => width_adapter_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_src_ready, -- .ready
source0_valid => burst_adapter_source0_valid, -- source0.valid
source0_data => burst_adapter_source0_data, -- .data
source0_channel => burst_adapter_source0_channel, -- .channel
source0_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_source0_ready -- .ready
);
burst_adapter_001 : component tracking_camera_system_burst_adapter
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_002_src_valid, -- sink0.valid
sink0_data => width_adapter_002_src_data, -- .data
sink0_channel => width_adapter_002_src_channel, -- .channel
sink0_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_002_src_ready, -- .ready
source0_valid => burst_adapter_001_source0_valid, -- source0.valid
source0_data => burst_adapter_001_source0_data, -- .data
source0_channel => burst_adapter_001_source0_channel, -- .channel
source0_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_001_source0_ready -- .ready
);
burst_adapter_002 : component tracking_camera_system_burst_adapter_002
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_004_src_valid, -- sink0.valid
sink0_data => width_adapter_004_src_data, -- .data
sink0_channel => width_adapter_004_src_channel, -- .channel
sink0_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_004_src_ready, -- .ready
source0_valid => burst_adapter_002_source0_valid, -- source0.valid
source0_data => burst_adapter_002_source0_data, -- .data
source0_channel => burst_adapter_002_source0_channel, -- .channel
source0_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_002_source0_ready -- .ready
);
burst_adapter_003 : component tracking_camera_system_burst_adapter_002
port map (
clk => altpll_0_c1_clk, -- cr0.clk
reset => rst_controller_reset_out_reset, -- cr0_reset.reset
sink0_valid => width_adapter_006_src_valid, -- sink0.valid
sink0_data => width_adapter_006_src_data, -- .data
sink0_channel => width_adapter_006_src_channel, -- .channel
sink0_startofpacket => width_adapter_006_src_startofpacket, -- .startofpacket
sink0_endofpacket => width_adapter_006_src_endofpacket, -- .endofpacket
sink0_ready => width_adapter_006_src_ready, -- .ready
source0_valid => burst_adapter_003_source0_valid, -- source0.valid
source0_data => burst_adapter_003_source0_data, -- .data
source0_channel => burst_adapter_003_source0_channel, -- .channel
source0_startofpacket => burst_adapter_003_source0_startofpacket, -- .startofpacket
source0_endofpacket => burst_adapter_003_source0_endofpacket, -- .endofpacket
source0_ready => burst_adapter_003_source0_ready -- .ready
);
rst_controller : component tracking_camera_system_rst_controller
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset -- reset_out.reset
);
rst_controller_001 : component tracking_camera_system_rst_controller
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset -- reset_out.reset
);
cmd_xbar_demux : component tracking_camera_system_cmd_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => limiter_cmd_src_ready, -- sink.ready
sink_channel => limiter_cmd_src_channel, -- .channel
sink_data => limiter_cmd_src_data, -- .data
sink_startofpacket => limiter_cmd_src_startofpacket, -- .startofpacket
sink_endofpacket => limiter_cmd_src_endofpacket, -- .endofpacket
sink_valid => limiter_cmd_valid_data, -- sink_valid.data
src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_src0_valid, -- .valid
src0_data => cmd_xbar_demux_src0_data, -- .data
src0_channel => cmd_xbar_demux_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_src1_valid, -- .valid
src1_data => cmd_xbar_demux_src1_data, -- .data
src1_channel => cmd_xbar_demux_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_src2_valid, -- .valid
src2_data => cmd_xbar_demux_src2_data, -- .data
src2_channel => cmd_xbar_demux_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_src3_valid, -- .valid
src3_data => cmd_xbar_demux_src3_data, -- .data
src3_channel => cmd_xbar_demux_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_src3_endofpacket -- .endofpacket
);
cmd_xbar_demux_001 : component tracking_camera_system_cmd_xbar_demux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => limiter_001_cmd_src_ready, -- sink.ready
sink_channel => limiter_001_cmd_src_channel, -- .channel
sink_data => limiter_001_cmd_src_data, -- .data
sink_startofpacket => limiter_001_cmd_src_startofpacket, -- .startofpacket
sink_endofpacket => limiter_001_cmd_src_endofpacket, -- .endofpacket
sink_valid => limiter_001_cmd_valid_data, -- sink_valid.data
src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid
src0_data => cmd_xbar_demux_001_src0_data, -- .data
src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
src1_data => cmd_xbar_demux_001_src1_data, -- .data
src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket
src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready
src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid
src2_data => cmd_xbar_demux_001_src2_data, -- .data
src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel
src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket
src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready
src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid
src3_data => cmd_xbar_demux_001_src3_data, -- .data
src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel
src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket
src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready
src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid
src4_data => cmd_xbar_demux_001_src4_data, -- .data
src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel
src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready
src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid
src5_data => cmd_xbar_demux_001_src5_data, -- .data
src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel
src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket
src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket
src6_ready => cmd_xbar_demux_001_src6_ready, -- src6.ready
src6_valid => cmd_xbar_demux_001_src6_valid, -- .valid
src6_data => cmd_xbar_demux_001_src6_data, -- .data
src6_channel => cmd_xbar_demux_001_src6_channel, -- .channel
src6_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket
src6_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket
src7_ready => cmd_xbar_demux_001_src7_ready, -- src7.ready
src7_valid => cmd_xbar_demux_001_src7_valid, -- .valid
src7_data => cmd_xbar_demux_001_src7_data, -- .data
src7_channel => cmd_xbar_demux_001_src7_channel, -- .channel
src7_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket
src7_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket
src8_ready => cmd_xbar_demux_001_src8_ready, -- src8.ready
src8_valid => cmd_xbar_demux_001_src8_valid, -- .valid
src8_data => cmd_xbar_demux_001_src8_data, -- .data
src8_channel => cmd_xbar_demux_001_src8_channel, -- .channel
src8_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
src8_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
src9_ready => cmd_xbar_demux_001_src9_ready, -- src9.ready
src9_valid => cmd_xbar_demux_001_src9_valid, -- .valid
src9_data => cmd_xbar_demux_001_src9_data, -- .data
src9_channel => cmd_xbar_demux_001_src9_channel, -- .channel
src9_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket
src9_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket
src10_ready => cmd_xbar_demux_001_src10_ready, -- src10.ready
src10_valid => cmd_xbar_demux_001_src10_valid, -- .valid
src10_data => cmd_xbar_demux_001_src10_data, -- .data
src10_channel => cmd_xbar_demux_001_src10_channel, -- .channel
src10_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket
src10_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket
src11_ready => cmd_xbar_demux_001_src11_ready, -- src11.ready
src11_valid => cmd_xbar_demux_001_src11_valid, -- .valid
src11_data => cmd_xbar_demux_001_src11_data, -- .data
src11_channel => cmd_xbar_demux_001_src11_channel, -- .channel
src11_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
src11_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
src12_ready => cmd_xbar_demux_001_src12_ready, -- src12.ready
src12_valid => cmd_xbar_demux_001_src12_valid, -- .valid
src12_data => cmd_xbar_demux_001_src12_data, -- .data
src12_channel => cmd_xbar_demux_001_src12_channel, -- .channel
src12_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket
src12_endofpacket => cmd_xbar_demux_001_src12_endofpacket -- .endofpacket
);
cmd_xbar_mux : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_src_ready, -- src.ready
src_valid => cmd_xbar_mux_src_valid, -- .valid
src_data => cmd_xbar_mux_src_data, -- .data
src_channel => cmd_xbar_mux_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src0_valid, -- .valid
sink0_channel => cmd_xbar_demux_src0_channel, -- .channel
sink0_data => cmd_xbar_demux_src0_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src0_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src0_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src0_endofpacket -- .endofpacket
);
cmd_xbar_mux_001 : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_001_src_ready, -- src.ready
src_valid => cmd_xbar_mux_001_src_valid, -- .valid
src_data => cmd_xbar_mux_001_src_data, -- .data
src_channel => cmd_xbar_mux_001_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src1_valid, -- .valid
sink0_channel => cmd_xbar_demux_src1_channel, -- .channel
sink0_data => cmd_xbar_demux_src1_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src1_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src1_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src1_endofpacket -- .endofpacket
);
cmd_xbar_mux_002 : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_002_src_ready, -- src.ready
src_valid => cmd_xbar_mux_002_src_valid, -- .valid
src_data => cmd_xbar_mux_002_src_data, -- .data
src_channel => cmd_xbar_mux_002_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src2_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src2_valid, -- .valid
sink0_channel => cmd_xbar_demux_src2_channel, -- .channel
sink0_data => cmd_xbar_demux_src2_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src2_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src2_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src2_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src2_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src2_endofpacket -- .endofpacket
);
cmd_xbar_mux_003 : component tracking_camera_system_cmd_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => cmd_xbar_mux_003_src_ready, -- src.ready
src_valid => cmd_xbar_mux_003_src_valid, -- .valid
src_data => cmd_xbar_mux_003_src_data, -- .data
src_channel => cmd_xbar_mux_003_src_channel, -- .channel
src_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
src_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
sink0_ready => cmd_xbar_demux_src3_ready, -- sink0.ready
sink0_valid => cmd_xbar_demux_src3_valid, -- .valid
sink0_channel => cmd_xbar_demux_src3_channel, -- .channel
sink0_data => cmd_xbar_demux_src3_data, -- .data
sink0_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket
sink0_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket
sink1_ready => cmd_xbar_demux_001_src3_ready, -- sink1.ready
sink1_valid => cmd_xbar_demux_001_src3_valid, -- .valid
sink1_channel => cmd_xbar_demux_001_src3_channel, -- .channel
sink1_data => cmd_xbar_demux_001_src3_data, -- .data
sink1_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket
sink1_endofpacket => cmd_xbar_demux_001_src3_endofpacket -- .endofpacket
);
rsp_xbar_demux : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_src_ready, -- sink.ready
sink_channel => id_router_src_channel, -- .channel
sink_data => id_router_src_data, -- .data
sink_startofpacket => id_router_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_src_valid, -- .valid
src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_src0_valid, -- .valid
src0_data => rsp_xbar_demux_src0_data, -- .data
src0_channel => rsp_xbar_demux_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_src1_valid, -- .valid
src1_data => rsp_xbar_demux_src1_data, -- .data
src1_channel => rsp_xbar_demux_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_001 : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_001_src_ready, -- sink.ready
sink_channel => id_router_001_src_channel, -- .channel
sink_data => id_router_001_src_data, -- .data
sink_startofpacket => id_router_001_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_001_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid
src0_data => rsp_xbar_demux_001_src0_data, -- .data
src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_001_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
src1_data => rsp_xbar_demux_001_src1_data, -- .data
src1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_001_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_002 : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_001_src_ready, -- sink.ready
sink_channel => width_adapter_001_src_channel, -- .channel
sink_data => width_adapter_001_src_data, -- .data
sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_001_src_valid, -- .valid
src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid
src0_data => rsp_xbar_demux_002_src0_data, -- .data
src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_002_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_002_src1_valid, -- .valid
src1_data => rsp_xbar_demux_002_src1_data, -- .data
src1_channel => rsp_xbar_demux_002_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_002_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_003 : component tracking_camera_system_rsp_xbar_demux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_003_src_ready, -- sink.ready
sink_channel => width_adapter_003_src_channel, -- .channel
sink_data => width_adapter_003_src_data, -- .data
sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_003_src_valid, -- .valid
src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid
src0_data => rsp_xbar_demux_003_src0_data, -- .data
src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket
src1_ready => rsp_xbar_demux_003_src1_ready, -- src1.ready
src1_valid => rsp_xbar_demux_003_src1_valid, -- .valid
src1_data => rsp_xbar_demux_003_src1_data, -- .data
src1_channel => rsp_xbar_demux_003_src1_channel, -- .channel
src1_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
src1_endofpacket => rsp_xbar_demux_003_src1_endofpacket -- .endofpacket
);
rsp_xbar_demux_004 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_004_src_ready, -- sink.ready
sink_channel => id_router_004_src_channel, -- .channel
sink_data => id_router_004_src_data, -- .data
sink_startofpacket => id_router_004_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_004_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_004_src_valid, -- .valid
src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid
src0_data => rsp_xbar_demux_004_src0_data, -- .data
src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_005 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_005_src_ready, -- sink.ready
sink_channel => id_router_005_src_channel, -- .channel
sink_data => id_router_005_src_data, -- .data
sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid
src0_data => rsp_xbar_demux_005_src0_data, -- .data
src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_006 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_006_src_ready, -- sink.ready
sink_channel => id_router_006_src_channel, -- .channel
sink_data => id_router_006_src_data, -- .data
sink_startofpacket => id_router_006_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_006_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_006_src_valid, -- .valid
src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid
src0_data => rsp_xbar_demux_006_src0_data, -- .data
src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_007 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_007_src_ready, -- sink.ready
sink_channel => id_router_007_src_channel, -- .channel
sink_data => id_router_007_src_data, -- .data
sink_startofpacket => id_router_007_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_007_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_007_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_007_src0_valid, -- .valid
src0_data => rsp_xbar_demux_007_src0_data, -- .data
src0_channel => rsp_xbar_demux_007_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_008 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_005_src_ready, -- sink.ready
sink_channel => width_adapter_005_src_channel, -- .channel
sink_data => width_adapter_005_src_data, -- .data
sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_005_src_valid, -- .valid
src0_ready => rsp_xbar_demux_008_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_008_src0_valid, -- .valid
src0_data => rsp_xbar_demux_008_src0_data, -- .data
src0_channel => rsp_xbar_demux_008_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_008_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_009 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_009_src_ready, -- sink.ready
sink_channel => id_router_009_src_channel, -- .channel
sink_data => id_router_009_src_data, -- .data
sink_startofpacket => id_router_009_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_009_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_009_src_valid, -- .valid
src0_ready => rsp_xbar_demux_009_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_009_src0_valid, -- .valid
src0_data => rsp_xbar_demux_009_src0_data, -- .data
src0_channel => rsp_xbar_demux_009_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_009_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_010 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_010_src_ready, -- sink.ready
sink_channel => id_router_010_src_channel, -- .channel
sink_data => id_router_010_src_data, -- .data
sink_startofpacket => id_router_010_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_010_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_010_src_valid, -- .valid
src0_ready => rsp_xbar_demux_010_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_010_src0_valid, -- .valid
src0_data => rsp_xbar_demux_010_src0_data, -- .data
src0_channel => rsp_xbar_demux_010_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_010_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_011 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => width_adapter_007_src_ready, -- sink.ready
sink_channel => width_adapter_007_src_channel, -- .channel
sink_data => width_adapter_007_src_data, -- .data
sink_startofpacket => width_adapter_007_src_startofpacket, -- .startofpacket
sink_endofpacket => width_adapter_007_src_endofpacket, -- .endofpacket
sink_valid(0) => width_adapter_007_src_valid, -- .valid
src0_ready => rsp_xbar_demux_011_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_011_src0_valid, -- .valid
src0_data => rsp_xbar_demux_011_src0_data, -- .data
src0_channel => rsp_xbar_demux_011_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_011_src0_endofpacket -- .endofpacket
);
rsp_xbar_demux_012 : component tracking_camera_system_rsp_xbar_demux_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
sink_ready => id_router_012_src_ready, -- sink.ready
sink_channel => id_router_012_src_channel, -- .channel
sink_data => id_router_012_src_data, -- .data
sink_startofpacket => id_router_012_src_startofpacket, -- .startofpacket
sink_endofpacket => id_router_012_src_endofpacket, -- .endofpacket
sink_valid(0) => id_router_012_src_valid, -- .valid
src0_ready => rsp_xbar_demux_012_src0_ready, -- src0.ready
src0_valid => rsp_xbar_demux_012_src0_valid, -- .valid
src0_data => rsp_xbar_demux_012_src0_data, -- .data
src0_channel => rsp_xbar_demux_012_src0_channel, -- .channel
src0_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
src0_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux : component tracking_camera_system_rsp_xbar_mux
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_src_ready, -- src.ready
src_valid => rsp_xbar_mux_src_valid, -- .valid
src_data => rsp_xbar_mux_src_data, -- .data
src_channel => rsp_xbar_mux_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src0_valid, -- .valid
sink0_channel => rsp_xbar_demux_src0_channel, -- .channel
sink0_data => rsp_xbar_demux_src0_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src0_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src0_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src0_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket -- .endofpacket
);
rsp_xbar_mux_001 : component tracking_camera_system_rsp_xbar_mux_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
src_ready => rsp_xbar_mux_001_src_ready, -- src.ready
src_valid => rsp_xbar_mux_001_src_valid, -- .valid
src_data => rsp_xbar_mux_001_src_data, -- .data
src_channel => rsp_xbar_mux_001_src_channel, -- .channel
src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket
src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket
sink0_ready => rsp_xbar_demux_src1_ready, -- sink0.ready
sink0_valid => rsp_xbar_demux_src1_valid, -- .valid
sink0_channel => rsp_xbar_demux_src1_channel, -- .channel
sink0_data => rsp_xbar_demux_src1_data, -- .data
sink0_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket
sink0_endofpacket => rsp_xbar_demux_src1_endofpacket, -- .endofpacket
sink1_ready => rsp_xbar_demux_001_src1_ready, -- sink1.ready
sink1_valid => rsp_xbar_demux_001_src1_valid, -- .valid
sink1_channel => rsp_xbar_demux_001_src1_channel, -- .channel
sink1_data => rsp_xbar_demux_001_src1_data, -- .data
sink1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket
sink1_endofpacket => rsp_xbar_demux_001_src1_endofpacket, -- .endofpacket
sink2_ready => rsp_xbar_demux_002_src1_ready, -- sink2.ready
sink2_valid => rsp_xbar_demux_002_src1_valid, -- .valid
sink2_channel => rsp_xbar_demux_002_src1_channel, -- .channel
sink2_data => rsp_xbar_demux_002_src1_data, -- .data
sink2_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket
sink2_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket
sink3_ready => rsp_xbar_demux_003_src1_ready, -- sink3.ready
sink3_valid => rsp_xbar_demux_003_src1_valid, -- .valid
sink3_channel => rsp_xbar_demux_003_src1_channel, -- .channel
sink3_data => rsp_xbar_demux_003_src1_data, -- .data
sink3_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket
sink3_endofpacket => rsp_xbar_demux_003_src1_endofpacket, -- .endofpacket
sink4_ready => crosser_001_out_ready, -- sink4.ready
sink4_valid => crosser_001_out_valid, -- .valid
sink4_channel => crosser_001_out_channel, -- .channel
sink4_data => crosser_001_out_data, -- .data
sink4_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
sink4_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready
sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid
sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel
sink5_data => rsp_xbar_demux_005_src0_data, -- .data
sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket
sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket
sink6_ready => rsp_xbar_demux_006_src0_ready, -- sink6.ready
sink6_valid => rsp_xbar_demux_006_src0_valid, -- .valid
sink6_channel => rsp_xbar_demux_006_src0_channel, -- .channel
sink6_data => rsp_xbar_demux_006_src0_data, -- .data
sink6_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket
sink6_endofpacket => rsp_xbar_demux_006_src0_endofpacket, -- .endofpacket
sink7_ready => rsp_xbar_demux_007_src0_ready, -- sink7.ready
sink7_valid => rsp_xbar_demux_007_src0_valid, -- .valid
sink7_channel => rsp_xbar_demux_007_src0_channel, -- .channel
sink7_data => rsp_xbar_demux_007_src0_data, -- .data
sink7_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket
sink7_endofpacket => rsp_xbar_demux_007_src0_endofpacket, -- .endofpacket
sink8_ready => rsp_xbar_demux_008_src0_ready, -- sink8.ready
sink8_valid => rsp_xbar_demux_008_src0_valid, -- .valid
sink8_channel => rsp_xbar_demux_008_src0_channel, -- .channel
sink8_data => rsp_xbar_demux_008_src0_data, -- .data
sink8_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket
sink8_endofpacket => rsp_xbar_demux_008_src0_endofpacket, -- .endofpacket
sink9_ready => rsp_xbar_demux_009_src0_ready, -- sink9.ready
sink9_valid => rsp_xbar_demux_009_src0_valid, -- .valid
sink9_channel => rsp_xbar_demux_009_src0_channel, -- .channel
sink9_data => rsp_xbar_demux_009_src0_data, -- .data
sink9_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket
sink9_endofpacket => rsp_xbar_demux_009_src0_endofpacket, -- .endofpacket
sink10_ready => rsp_xbar_demux_010_src0_ready, -- sink10.ready
sink10_valid => rsp_xbar_demux_010_src0_valid, -- .valid
sink10_channel => rsp_xbar_demux_010_src0_channel, -- .channel
sink10_data => rsp_xbar_demux_010_src0_data, -- .data
sink10_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket
sink10_endofpacket => rsp_xbar_demux_010_src0_endofpacket, -- .endofpacket
sink11_ready => rsp_xbar_demux_011_src0_ready, -- sink11.ready
sink11_valid => rsp_xbar_demux_011_src0_valid, -- .valid
sink11_channel => rsp_xbar_demux_011_src0_channel, -- .channel
sink11_data => rsp_xbar_demux_011_src0_data, -- .data
sink11_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket
sink11_endofpacket => rsp_xbar_demux_011_src0_endofpacket, -- .endofpacket
sink12_ready => rsp_xbar_demux_012_src0_ready, -- sink12.ready
sink12_valid => rsp_xbar_demux_012_src0_valid, -- .valid
sink12_channel => rsp_xbar_demux_012_src0_channel, -- .channel
sink12_data => rsp_xbar_demux_012_src0_data, -- .data
sink12_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket
sink12_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket
);
width_adapter : component tracking_camera_system_width_adapter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_002_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_002_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_002_src_ready, -- .ready
in_data => cmd_xbar_mux_002_src_data, -- .data
out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket
out_data => width_adapter_src_data, -- .data
out_channel => width_adapter_src_channel, -- .channel
out_valid => width_adapter_src_valid, -- .valid
out_ready => width_adapter_src_ready, -- .ready
out_startofpacket => width_adapter_src_startofpacket -- .startofpacket
);
width_adapter_001 : component tracking_camera_system_width_adapter_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_002_src_valid, -- sink.valid
in_channel => id_router_002_src_channel, -- .channel
in_startofpacket => id_router_002_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_002_src_endofpacket, -- .endofpacket
in_ready => id_router_002_src_ready, -- .ready
in_data => id_router_002_src_data, -- .data
out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket
out_data => width_adapter_001_src_data, -- .data
out_channel => width_adapter_001_src_channel, -- .channel
out_valid => width_adapter_001_src_valid, -- .valid
out_ready => width_adapter_001_src_ready, -- .ready
out_startofpacket => width_adapter_001_src_startofpacket -- .startofpacket
);
width_adapter_002 : component tracking_camera_system_width_adapter
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_mux_003_src_valid, -- sink.valid
in_channel => cmd_xbar_mux_003_src_channel, -- .channel
in_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket
in_ready => cmd_xbar_mux_003_src_ready, -- .ready
in_data => cmd_xbar_mux_003_src_data, -- .data
out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket
out_data => width_adapter_002_src_data, -- .data
out_channel => width_adapter_002_src_channel, -- .channel
out_valid => width_adapter_002_src_valid, -- .valid
out_ready => width_adapter_002_src_ready, -- .ready
out_startofpacket => width_adapter_002_src_startofpacket -- .startofpacket
);
width_adapter_003 : component tracking_camera_system_width_adapter_001
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_003_src_valid, -- sink.valid
in_channel => id_router_003_src_channel, -- .channel
in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket
in_ready => id_router_003_src_ready, -- .ready
in_data => id_router_003_src_data, -- .data
out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket
out_data => width_adapter_003_src_data, -- .data
out_channel => width_adapter_003_src_channel, -- .channel
out_valid => width_adapter_003_src_valid, -- .valid
out_ready => width_adapter_003_src_ready, -- .ready
out_startofpacket => width_adapter_003_src_startofpacket -- .startofpacket
);
width_adapter_004 : component tracking_camera_system_width_adapter_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_001_src8_valid, -- sink.valid
in_channel => cmd_xbar_demux_001_src8_channel, -- .channel
in_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_001_src8_ready, -- .ready
in_data => cmd_xbar_demux_001_src8_data, -- .data
out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket
out_data => width_adapter_004_src_data, -- .data
out_channel => width_adapter_004_src_channel, -- .channel
out_valid => width_adapter_004_src_valid, -- .valid
out_ready => width_adapter_004_src_ready, -- .ready
out_startofpacket => width_adapter_004_src_startofpacket -- .startofpacket
);
width_adapter_005 : component tracking_camera_system_width_adapter_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_008_src_valid, -- sink.valid
in_channel => id_router_008_src_channel, -- .channel
in_startofpacket => id_router_008_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_008_src_endofpacket, -- .endofpacket
in_ready => id_router_008_src_ready, -- .ready
in_data => id_router_008_src_data, -- .data
out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket
out_data => width_adapter_005_src_data, -- .data
out_channel => width_adapter_005_src_channel, -- .channel
out_valid => width_adapter_005_src_valid, -- .valid
out_ready => width_adapter_005_src_ready, -- .ready
out_startofpacket => width_adapter_005_src_startofpacket -- .startofpacket
);
width_adapter_006 : component tracking_camera_system_width_adapter_004
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => cmd_xbar_demux_001_src11_valid, -- sink.valid
in_channel => cmd_xbar_demux_001_src11_channel, -- .channel
in_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket
in_ready => cmd_xbar_demux_001_src11_ready, -- .ready
in_data => cmd_xbar_demux_001_src11_data, -- .data
out_endofpacket => width_adapter_006_src_endofpacket, -- src.endofpacket
out_data => width_adapter_006_src_data, -- .data
out_channel => width_adapter_006_src_channel, -- .channel
out_valid => width_adapter_006_src_valid, -- .valid
out_ready => width_adapter_006_src_ready, -- .ready
out_startofpacket => width_adapter_006_src_startofpacket -- .startofpacket
);
width_adapter_007 : component tracking_camera_system_width_adapter_005
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
in_valid => id_router_011_src_valid, -- sink.valid
in_channel => id_router_011_src_channel, -- .channel
in_startofpacket => id_router_011_src_startofpacket, -- .startofpacket
in_endofpacket => id_router_011_src_endofpacket, -- .endofpacket
in_ready => id_router_011_src_ready, -- .ready
in_data => id_router_011_src_data, -- .data
out_endofpacket => width_adapter_007_src_endofpacket, -- src.endofpacket
out_data => width_adapter_007_src_data, -- .data
out_channel => width_adapter_007_src_channel, -- .channel
out_valid => width_adapter_007_src_valid, -- .valid
out_ready => width_adapter_007_src_ready, -- .ready
out_startofpacket => width_adapter_007_src_startofpacket -- .startofpacket
);
crosser : component tracking_camera_system_crosser
port map (
in_clk => altpll_0_c1_clk, -- in_clk.clk
in_reset => rst_controller_reset_out_reset, -- in_clk_reset.reset
out_clk => clk_clk, -- out_clk.clk
out_reset => rst_controller_001_reset_out_reset, -- out_clk_reset.reset
in_ready => cmd_xbar_demux_001_src4_ready, -- in.ready
in_valid => cmd_xbar_demux_001_src4_valid, -- .valid
in_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket
in_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket
in_channel => cmd_xbar_demux_001_src4_channel, -- .channel
in_data => cmd_xbar_demux_001_src4_data, -- .data
out_ready => crosser_out_ready, -- out.ready
out_valid => crosser_out_valid, -- .valid
out_startofpacket => crosser_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_out_endofpacket, -- .endofpacket
out_channel => crosser_out_channel, -- .channel
out_data => crosser_out_data -- .data
);
crosser_001 : component tracking_camera_system_crosser
port map (
in_clk => clk_clk, -- in_clk.clk
in_reset => rst_controller_001_reset_out_reset, -- in_clk_reset.reset
out_clk => altpll_0_c1_clk, -- out_clk.clk
out_reset => rst_controller_reset_out_reset, -- out_clk_reset.reset
in_ready => rsp_xbar_demux_004_src0_ready, -- in.ready
in_valid => rsp_xbar_demux_004_src0_valid, -- .valid
in_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket
in_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket
in_channel => rsp_xbar_demux_004_src0_channel, -- .channel
in_data => rsp_xbar_demux_004_src0_data, -- .data
out_ready => crosser_001_out_ready, -- out.ready
out_valid => crosser_001_out_valid, -- .valid
out_startofpacket => crosser_001_out_startofpacket, -- .startofpacket
out_endofpacket => crosser_001_out_endofpacket, -- .endofpacket
out_channel => crosser_001_out_channel, -- .channel
out_data => crosser_001_out_data -- .data
);
irq_mapper : component tracking_camera_system_irq_mapper
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
sender_irq => nios2_qsys_0_d_irq_irq -- sender.irq
);
reset_reset_n_ports_inv <= not reset_reset_n;
sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_write;
sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_read;
sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_byteenable;
timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not timer_0_s1_translator_avalon_anti_slave_0_write;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write;
jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read;
green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv <= not green_leds_s1_translator_avalon_anti_slave_0_write;
servo_pwm_0_s0_translator_avalon_anti_slave_0_write_ports_inv <= not servo_pwm_0_s0_translator_avalon_anti_slave_0_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of tracking_camera_system
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_bpb_pkg.all;
entity cpu_bpb is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_bpb_ctrl_in : in cpu_bpb_ctrl_in_type;
cpu_bpb_dp_in : in cpu_bpb_dp_in_type;
cpu_bpb_ctrl_out : out cpu_bpb_ctrl_out_type;
cpu_bpb_dp_out : out cpu_bpb_dp_out_type
);
end;
|
architecture RTL of FIFO is
begin
process
begin
loop
a <= b;
end loop;
loop -- Comment
a <= b;
end loop;
-- Violations below
loop
a <= b;
end loop;
loop
a <= b; -- Comment
end loop;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc674.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00674ent IS
END c03s04b01x00p23n01i00674ent;
ARCHITECTURE c03s04b01x00p23n01i00674arch OF c03s04b01x00p23n01i00674ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ( '0', '1', 'Z' );
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT is file of LOGIC_SWITCH;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.49";
-- Declare a variable.
constant CON : LOGIC_SWITCH := '1';
variable VAR : LOGIC_SWITCH := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00674 - The output file will tested by test file s010406.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00674arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc674.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00674ent IS
END c03s04b01x00p23n01i00674ent;
ARCHITECTURE c03s04b01x00p23n01i00674arch OF c03s04b01x00p23n01i00674ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ( '0', '1', 'Z' );
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT is file of LOGIC_SWITCH;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.49";
-- Declare a variable.
constant CON : LOGIC_SWITCH := '1';
variable VAR : LOGIC_SWITCH := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00674 - The output file will tested by test file s010406.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00674arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc674.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:59 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00674ent IS
END c03s04b01x00p23n01i00674ent;
ARCHITECTURE c03s04b01x00p23n01i00674arch OF c03s04b01x00p23n01i00674ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type SWITCH_LEVEL is ( '0', '1', 'Z' );
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
type FT is file of LOGIC_SWITCH;
-- Declare the actual file to write.
file FILEV : FT open write_mode is "iofile.49";
-- Declare a variable.
constant CON : LOGIC_SWITCH := '1';
variable VAR : LOGIC_SWITCH := CON;
BEGIN
-- Write out the file.
for I in 1 to 100 loop
WRITE( FILEV,VAR );
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00674 - The output file will tested by test file s010406.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00674arch;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Vendor and devices id's for amba plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices_ocp is
-- Vendor code
constant VENDOR_OPENCHIP : amba_vendor_type := 16#06#;
-- OpenChip ID's
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- pragma translate_off
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Vendor and devices id's for amba plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices_ocp is
-- Vendor code
constant VENDOR_OPENCHIP : amba_vendor_type := 16#06#;
-- OpenChip ID's
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- pragma translate_off
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
-- pragma translate_on
end;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_manchester_encode IS END tb_manchester_encode;
ARCHITECTURE test OF tb_manchester_encode IS
COMPONENT manchester_encode IS
PORT(input, clk: IN STD_LOGIC;
man_out: OUT STD_LOGIC);
END COMPONENT;
SIGNAL input, clk: STD_LOGIC:='0';
SIGNAL man_out: STD_LOGIC;
BEGIN
T1: manchester_encode PORT MAP(input, clk, man_out);
input<='0',
'1' AFTER 15 ns,
'0' AFTER 25 ns,
'1' AFTER 35 ns,
'0' AFTER 45 ns,
'1' AFTER 55 ns,
'0' AFTER 65 ns,
'1' AFTER 75 ns,
'0' AFTER 85 ns;
clk<=NOT(clk) AFTER 2.5 ns;
END test; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
entity zpuino_debug_core is
port (
clk: in std_logic;
rst: in std_logic;
dbg_in: in zpu_dbg_out_type;
dbg_out: out zpu_dbg_in_type;
dbg_reset: out std_logic;
jtag_data_chain_out: out std_logic_vector(98 downto 0);
jtag_ctrl_chain_in: in std_logic_vector(11 downto 0)
);
end entity;
architecture behave of zpuino_debug_core is
signal enter_ss: std_logic :='0';
signal step: std_logic := '0';
signal status_injection_ready: std_logic;
signal status_injectmode: std_logic;
type state_type is (
state_idle,
state_debug,
state_enter_inject,
state_flush,
state_inject,
state_leave_inject,
state_step
);
type dbgregs_type is record
state: state_type;
step: std_logic;
inject: std_logic;
freeze: std_logic;
injectmode: std_logic;
reset: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
signal dbgr: dbgregs_type;
signal injected: std_logic;
signal inject_q_in: std_logic := '0';
signal inject_q: std_logic := '0';
alias jtag_debug: std_logic is jtag_ctrl_chain_in(0);
alias jtag_inject: std_logic is jtag_ctrl_chain_in(1);
alias jtag_step: std_logic is jtag_ctrl_chain_in(2);
alias jtag_reset: std_logic is jtag_ctrl_chain_in(3);
alias jtag_opcode: std_logic_vector(7 downto 0) is jtag_ctrl_chain_in(11 downto 4);
signal pc_i: std_logic_vector(wordSize-1 downto 0);
signal sp_i: std_logic_vector(wordSize-1 downto 0);
begin
pc_i(wordSize-1 downto dbg_in.pc'high+1) <= (others => '0');
pc_i(dbg_in.pc'high downto dbg_in.pc'low) <= dbg_in.pc;
sp_i(wordSize-1 downto dbg_in.sp'high+1) <= (others => '0');
sp_i(dbg_in.sp'high downto dbg_in.sp'low) <= dbg_in.sp;
sp_i(dbg_in.sp'low-1 downto 0) <= (others => '0');
-- jtag chain output
jtag_data_chain_out <=
dbg_in.idim &
sp_i &
dbg_in.stacka &
pc_i &
dbg_in.brk &
status_injection_ready
;
status_injection_ready <= '1' when dbgr.state = state_debug else '0';
process(clk, rst, dbgr, dbg_in.valid, jtag_debug, jtag_opcode,
inject_q, dbg_in.ready, dbg_in.pc, dbg_in.idim, jtag_ctrl_chain_in)
variable w: dbgregs_type;
begin
w := dbgr;
if rst='1' then
w.state := state_idle;
w.reset := '0';
w.flush := '0';
w.injectmode := '0';
w.inject := '0';
w.step := '0';
w.freeze := '0';
injected <= '0';
else
injected <= '0';
case dbgr.state is
when state_idle =>
w.freeze := '0';
--if jtag_debug='1' then
-- w.freeze := '1';
-- w.state := state_debug;
--end if;
if jtag_debug='1' then
--if dbg_ready='1' then
w.injectmode := '1';
--w.opcode := jtag_opcode;
-- end if;
-- Wait for pipeline to finish
if dbg_in.valid='0' and dbg_in.ready='1' then
--report "Enter PC " & hstr(dbg_pc) & " IDIM flag " & chr(dbg_idim) severity note;
w.state:=state_debug;
end if;
--end if;
end if;
when state_debug =>
w.step := '0';
if inject_q='1' then
w.state := state_enter_inject;
w.injectmode := '1';
w.opcode := jtag_opcode;
elsif jtag_debug='0' then
w.flush:='1';
w.state := state_leave_inject;
end if;
when state_leave_inject =>
w.flush := '0';
w.injectmode:='0';
w.state := state_idle;
when state_enter_inject =>
-- w.state := state_flush;
w.state := state_inject;
when state_flush =>
w.flush := '1';
w.state := state_inject;
when state_inject =>
w.inject := '1';
w.flush := '0';
-- Here ?
injected <= '1';
w.state := state_step;
when state_step =>
injected <= '0';
w.inject := '0';
if dbg_in.valid='1' then
-- w.step := '1';
w.state := state_debug;
end if;
when others =>
end case;
end if;
if rising_edge(clk) then
dbgr <= w;
end if;
end process;
dbg_out.freeze <= dbgr.freeze;
--dbg_reset <= dbgr.reset;
dbg_out.inject <= dbgr.inject;
dbg_out.injectmode <= dbgr.injectmode;-- and dbg_ready;
dbg_out.step <= dbgr.step;
dbg_out.flush <= dbgr.flush;
dbg_out.opcode <= dbgr.opcode;
process(clk)
begin
if rising_edge(clk) then
dbg_reset <= jtag_ctrl_chain_in(3);
end if;
end process;
-- Synchronization stuff
process(jtag_inject, clk, injected, inject_q_in)
begin
if injected='1' then
inject_q <= '0';
inject_q_in <= '0';
else
if rising_edge(jtag_inject) then
inject_q_in <= '1';
--else
-- inject_q_in <= inject_q_in;
end if;
if rising_edge(clk) then
inject_q <= inject_q_in;
end if;
end if;
end process;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_in_tb is
end entity;
architecture structure of struct_in_tb is
component router_struct is
generic (
ADDR_X : natural range 0 to 3 := 0;
ADDR_Y : natural range 0 to 3 := 0;
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(31 downto 0);
L_VIN : in std_logic;
L_RIN : out std_logic;
L_DOUT : out std_logic_vector(31 downto 0);
L_VOUT : out std_logic;
L_ROUT : in std_logic;
L_SZ : out std_logic_vector(15 downto 0);
L_DIR : out std_logic_vector(4 downto 0); --LNSEW
-- north
N_DIN : in std_logic_vector(31 downto 0);
N_VIN : in std_logic;
N_RIN : out std_logic;
N_DOUT : out std_logic_vector(31 downto 0);
N_VOUT : out std_logic;
N_ROUT : in std_logic;
N_SZ : out std_logic_vector(15 downto 0);
N_DIR : out std_logic_vector(4 downto 0);
-- south
S_DIN : in std_logic_vector(31 downto 0);
S_VIN : in std_logic;
S_RIN : out std_logic;
S_DOUT : out std_logic_vector(31 downto 0);
S_VOUT : out std_logic;
S_ROUT : in std_logic;
S_SZ : out std_logic_vector(15 downto 0);
S_DIR : out std_logic_vector(4 downto 0);
-- east
E_DIN : in std_logic_vector(31 downto 0);
E_VIN : in std_logic;
E_RIN : out std_logic;
E_DOUT : out std_logic_vector(31 downto 0);
E_VOUT : out std_logic;
E_ROUT : in std_logic;
E_SZ : out std_logic_vector(15 downto 0);
E_DIR : out std_logic_vector(4 downto 0);
-- west
W_DIN : in std_logic_vector(31 downto 0);
W_VIN : in std_logic;
W_RIN : out std_logic;
W_DOUT : out std_logic_vector(31 downto 0);
W_VOUT : out std_logic;
W_ROUT : in std_logic;
W_SZ : out std_logic_vector(15 downto 0);
W_DIR : out std_logic_vector(4 downto 0)
);
end component;
constant ADDR_X : natural range 0 to 3 := 1;
constant ADDR_Y : natural range 0 to 3 := 1;
constant N_INST : boolean := true;
constant S_INST : boolean := true;
constant E_INST : boolean := true;
constant W_INST : boolean := true;
signal CLOCK : std_logic := '0';
signal RESET : std_logic := '0';
-- local
signal L_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal L_VIN : std_logic := '0';
signal L_RIN : std_logic;
signal L_DOUT : std_logic_vector(31 downto 0);
signal L_VOUT : std_logic;
signal L_ROUT : std_logic := '0';
signal L_SZ : std_logic_vector(15 downto 0);
signal L_DIR : std_logic_vector(4 downto 0); --LNSEW
-- north
signal N_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal N_VIN : std_logic := '0';
signal N_RIN : std_logic;
signal N_DOUT : std_logic_vector(31 downto 0);
signal N_VOUT : std_logic;
signal N_ROUT : std_logic := '0';
signal N_SZ : std_logic_vector(15 downto 0);
signal N_DIR : std_logic_vector(4 downto 0);
-- south
signal S_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal S_VIN : std_logic := '0';
signal S_RIN : std_logic;
signal S_DOUT : std_logic_vector(31 downto 0);
signal S_VOUT : std_logic;
signal S_ROUT : std_logic := '0';
signal S_SZ : std_logic_vector(15 downto 0);
signal S_DIR : std_logic_vector(4 downto 0);
-- east
signal E_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal E_VIN : std_logic := '0';
signal E_RIN : std_logic;
signal E_DOUT : std_logic_vector(31 downto 0);
signal E_VOUT : std_logic;
signal E_ROUT : std_logic := '0';
signal E_SZ : std_logic_vector(15 downto 0);
signal E_DIR : std_logic_vector(4 downto 0);
-- west
signal W_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal W_VIN : std_logic := '0';
signal W_RIN : std_logic;
signal W_DOUT : std_logic_vector(31 downto 0);
signal W_VOUT : std_logic;
signal W_ROUT : std_logic := '0';
signal W_SZ : std_logic_vector(15 downto 0);
signal W_DIR : std_logic_vector(4 downto 0);
constant PKT_SIZE : positive := 8;
begin
UUT: struct_in
generic map (
ADDR_X => ADDR_X,
ADDR_Y => ADDR_Y,
N_INST => N_INST,
S_INST => S_INST,
E_INST => E_INST,
W_INST => W_INST
)
port map (
CLOCK => CLOCK,
RESET => RESET,
-- local
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
L_SZ => L_SZ,
L_DIR => L_DIR,
-- north
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
N_SZ => N_SZ,
N_DIR => N_DIR,
-- south
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
S_SZ => S_SZ,
S_DIR => S_DIR,
-- east
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
E_SZ => E_SZ,
E_DIR => E_DIR,
-- west
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT,
W_SZ => W_SZ,
W_DIR => W_DIR
);
CLOCK <= not CLOCK after 5 ns;
RESET <= '1', '0' after 20 ns;
-- local
L_PROC: process
begin
wait for 20 ns;
L_DIN <= X"00000000"; --west
L_VIN <= '1';
wait until rising_edge(CLOCK);
L_DIN <= X"10000000";
L_VIN <= '1';
wait until rising_edge(CLOCK);
L_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
L_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
L_DIN <= std_logic_vector(to_unsigned(i, 32));
L_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
L_DIN <= (others => 'X');
L_VIN <= '0';
wait for 50 ns;
for i in 1 to 16 loop
L_ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
L_ROUT <= '0';
wait for 100 ns;
wait;
end process;
-- north
N_PROC: process
begin
wait for 20 ns;
N_DIN <= X"F0000000"; --east
N_VIN <= '1';
wait until rising_edge(CLOCK);
N_DIN <= X"10000000";
N_VIN <= '1';
wait until rising_edge(CLOCK);
N_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
N_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
N_DIN <= std_logic_vector(to_unsigned(i, 32));
N_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
N_DIN <= (others => 'X');
N_VIN <= '0';
wait for 50 ns;
for i in 1 to 16 loop
N_ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
N_ROUT <= '0';
wait for 100 ns;
wait;
end process;
-- south
S_PROC: process
begin
wait for 20 ns;
S_DIN <= X"70000000"; --north
S_VIN <= '1';
wait until rising_edge(CLOCK);
S_DIN <= X"10000000";
S_VIN <= '1';
wait until rising_edge(CLOCK);
S_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
S_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
S_DIN <= std_logic_vector(to_unsigned(i, 32));
S_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
S_DIN <= (others => 'X');
S_VIN <= '0';
wait for 50 ns;
for i in 1 to 16 loop
S_ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
S_ROUT <= '0';
wait for 100 ns;
wait;
end process;
-- east
E_PROC: process
begin
wait for 20 ns;
E_DIN <= X"40000000"; --south
E_VIN <= '1';
wait until rising_edge(CLOCK);
E_DIN <= X"10000000";
E_VIN <= '1';
wait until rising_edge(CLOCK);
E_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
E_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
E_DIN <= std_logic_vector(to_unsigned(i, 32));
E_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
E_DIN <= (others => 'X');
E_VIN <= '0';
wait for 50 ns;
for i in 1 to 16 loop
E_ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
E_ROUT <= '0';
wait for 100 ns;
wait;
end process;
-- west
W_PROC: process
begin
wait for 20 ns;
W_DIN <= X"50000000"; --local
W_VIN <= '1';
wait until rising_edge(CLOCK);
W_DIN <= X"10000000";
W_VIN <= '1';
wait until rising_edge(CLOCK);
W_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
W_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
W_DIN <= std_logic_vector(to_unsigned(i, 32));
W_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
W_DIN <= (others => 'X');
W_VIN <= '0';
wait for 50 ns;
for i in 1 to 16 loop
W_ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
W_ROUT <= '0';
wait for 100 ns;
wait;
end process;
end architecture;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 29-02-2016
-- Module Name: moore.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity moore is
port (d, clk, reset : in std_logic;
z : out std_logic);
end entity moore;
architecture arch_moore of moore is
type state is (S0, S1, S2, S3, S4);
signal current : state := S0;
begin
process (clk, reset)
begin
if reset = '1' then
current <= S0;
end if;
if clk = '1' and clk'event then
case current is
when S0 =>
if d = '0' then
current <= S0;
else
current <= S1;
end if;
when S1 =>
if d = '0' then
current <= S2;
else
current <= S0;
end if;
when S2 =>
if d = '1' then
current <= S3;
else
current <= S0;
end if;
when S3 =>
if d = '0' then
current <= S2;
else
current <= S4;
end if;
when S4 =>
if d = '0' then
current <= S1;
else
current <= S2;
end if;
end case;
end if;
end process;
z <= '1' when current = S4 else '0';
end architecture arch_moore;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(13 downto 0);
b: in std_logic_vector(13 downto 0);
s: out std_logic_vector(13 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
port (
faa : IN STD_LOGIC_VECTOR (4-1 downto 0);
fab : IN STD_LOGIC_VECTOR (4-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (4-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (2-1 downto 0);
fab : IN STD_LOGIC_VECTOR (2-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (2-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(13 downto 0);
signal b_reg : std_logic_vector(13 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(3 downto 0);
signal b0_cb : std_logic_vector(3 downto 0);
signal a1_cb : std_logic_vector(7 downto 4);
signal b1_cb : std_logic_vector(7 downto 4);
signal a2_cb : std_logic_vector(11 downto 8);
signal b2_cb : std_logic_vector(11 downto 8);
signal a3_cb : std_logic_vector(13 downto 12);
signal b3_cb : std_logic_vector(13 downto 12);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
type ramtypei2 is array (2 downto 0) of std_logic_vector(1 downto 0);
signal a3_cb_regi3 : ramtypei2;
signal b3_cb_regi3 : ramtypei2;
-- wires for each full adder sum
signal fas : std_logic_vector(13 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout3_co3 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
signal faccout2_co2_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo2 is array (2 downto 0) of std_logic_vector(3 downto 0);
signal s0_ca_rego0 : ramtypeo2;
type ramtypeo1 is array (1 downto 0) of std_logic_vector(3 downto 0);
signal s1_ca_rego1 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(3 downto 0);
signal s2_ca_rego2 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(13 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(3 downto 0);
b0_cb <= b_reg(3 downto 0);
a1_cb <= a_reg(7 downto 4);
b1_cb <= b_reg(7 downto 4);
a2_cb <= a_reg(11 downto 8);
b2_cb <= b_reg(11 downto 8);
a3_cb <= a_reg(13 downto 12);
b3_cb <= b_reg(13 downto 12);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a3_cb_regi3 (0) <= a3_cb;
b3_cb_regi3 (0) <= b3_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
a3_cb_regi3 (1) <= a3_cb_regi3 (0);
b3_cb_regi3 (1) <= b3_cb_regi3 (0);
a3_cb_regi3 (2) <= a3_cb_regi3 (1);
b3_cb_regi3 (2) <= b3_cb_regi3 (1);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(3 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(7 downto 4),
facout => faccout1_co1);
u2 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(11 downto 8),
facout => faccout2_co2);
u3 : nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f
port map
(faa => a3_cb_regi3(2),
fab => b3_cb_regi3(2),
facin => faccout2_co2_reg,
fas => fas(13 downto 12),
facout => faccout3_co3);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(3 downto 0);
s1_ca_rego1 (0) <= fas(7 downto 4);
s2_ca_rego2 (0) <= fas(11 downto 8);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
s0_ca_rego0 (2) <= s0_ca_rego0 (1);
s1_ca_rego1 (1) <= s1_ca_rego1 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(3 downto 0) <= s0_ca_rego0(2);
s_tmp(7 downto 4) <= s1_ca_rego1(1);
s_tmp(11 downto 8) <= s2_ca_rego2(0);
s_tmp(13 downto 12) <= fas(13 downto 12);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
generic(N : natural :=4);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
generic(N : natural :=2);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_14ns_14ns_14_4 is
component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4_U : component nfa_accept_samples_generic_hw_add_14ns_14ns_14_4_AddSubnS_4
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity stratix2_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix2_pll is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component stratix2_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix2_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity case05 is
port (
in_en : std_logic;
in_v : std_logic_vector(3 downto 0)
);
end entity case05;
architecture behav of case05 is
begin
process(in_en, in_v)
variable l : boolean;
begin
if in_en = '1' then
case in_v is
when "0010" =>
l := in_v = "0000";
when others =>
report "illegal";
end case;
end if;
end process;
end architecture behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc184.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p05n01i00184ent IS
END c04s04b00x00p05n01i00184ent;
ARCHITECTURE c04s04b00x00p05n01i00184arch OF c04s04b00x00p05n01i00184ent IS
type COORDINATE is
record
X, Y: INTEGER;
end record;
type acccor is access COORDINATE;
attribute ill1 : acccor; --Failure here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s04b00x00p05n01i00184 - In an attribute declaration, the type mark must denote a subtype that is neither an access type nor a file type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p05n01i00184arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc184.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p05n01i00184ent IS
END c04s04b00x00p05n01i00184ent;
ARCHITECTURE c04s04b00x00p05n01i00184arch OF c04s04b00x00p05n01i00184ent IS
type COORDINATE is
record
X, Y: INTEGER;
end record;
type acccor is access COORDINATE;
attribute ill1 : acccor; --Failure here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s04b00x00p05n01i00184 - In an attribute declaration, the type mark must denote a subtype that is neither an access type nor a file type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p05n01i00184arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc184.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p05n01i00184ent IS
END c04s04b00x00p05n01i00184ent;
ARCHITECTURE c04s04b00x00p05n01i00184arch OF c04s04b00x00p05n01i00184ent IS
type COORDINATE is
record
X, Y: INTEGER;
end record;
type acccor is access COORDINATE;
attribute ill1 : acccor; --Failure here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s04b00x00p05n01i00184 - In an attribute declaration, the type mark must denote a subtype that is neither an access type nor a file type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p05n01i00184arch;
|
------------------------------------------------------------------------------------------------------------------------
-- Comment
------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Comment
--+-----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Comment
--|-----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Comment
--|--------------------------------[ abcdef ]===================================
--------------------------------------------------------------------------------
-- Comment
--|-[ abcdef ]==================================================================
--------------------------------------------------------------------------------
-- Comment
--|------------------------------------------------------------------[ abcdef ]=
architecture rtl of fifo is
--+---------------------------------------------------------------------------
-- Comment
--+---------------------------------------------------------------------------
signal sig1 : std_logic;
begin
end architecture rtl;
-- comment
-- comment
--! Doxygen comment
--! Doxygen comment
--! Doxygen comment
--! Doxygen comment
--! Doxygen comment
--! Doxygen comment
--! Doxygen comment
--! Doxygen comment
architecture rtl of FIFO is
begin
inst_dummy : entity lib.module
port map (
-- Clocks
clk => clk
--
-- Dummy comment
--
data_i => data_i
);
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_158 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_158;
architecture augh of cmp_158 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_158 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_158;
architecture augh of cmp_158 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 71968)
`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------------
-- FILE NAME : spi_checker.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity spi_checker is
generic (
SIM_ONLY : natural := 0;
CLK_FREQ : natural := 250
);
port (
clk : in std_logic;
sclk : in std_logic;
sdo : out std_logic;
sdi : in std_logic;
cs_n : in std_logic;
reg0 : out std_logic_vector(31 downto 0)
);
end spi_checker;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of spi_checker is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
constant DEBUG_ENABLE : boolean := FALSE;
attribute keep : string;
attribute S : string;
type cmd_state_machine is (HOLD_CMD, BYTE0_CMD, BYTE1_CMD, BYTE2_CMD, BYTE3_CMD, BYTE4_CMD,
BYTE5_CMD, BYTE6_CMD, BYTE7_CMD, BYTE8_CMD, BYTE9_CMD, BYTE10_CMD,
BYTE11_CMD, BYTE12_CMD, BYTE13_CMD, BYTE14_CMD, BYTE15_CMD);
type bus04 is array(natural range <>) of std_logic_vector( 3 downto 0);
constant WR_BIT : std_logic := '0'; -- 0 means write
constant RD_BIT : std_logic := '1'; -- 1 means read
constant FULL_WIDTH : natural := 24;
constant ADDR_WIDTH : natural := 8;
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal clock_count : std_logic_vector(7 downto 0);
signal write_cmd : std_logic;
signal sdi_reg : std_logic_vector(31 downto 0);
signal sdo_reg : std_logic_vector(31 downto 0);
signal captured : std_logic_vector(31 downto 0) := (others=>'0');
--***********************************************************************************
begin
--***********************************************************************************
process (clk, cs_n)
begin
if rising_edge(clk) then
if cs_n = '1' then
clock_count <= (others => '0');
write_cmd <= '0';
sdi_reg <= (others=>'0');
-- sdo_reg <= x"AAAAAAAA"; -- data to shift out
-- sdo <= '0';
else
-- count clock cycles received
clock_count <= clock_count + 1;
-- shift in data
sdi_reg <= sdi_reg(30 downto 0) & sdi;
if clock_count = 0 and sdi = WR_BIT then
write_cmd <= '1';
end if;
-- shift out data
-- if write_cmd = '0' and clock_count > 15 then
-- sdo_reg <= '0' & sdo_reg(31 downto 1);
-- sdo <= sdo_reg(0);
-- else
-- sdo <= '0';
-- end if;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clock_count = FULL_WIDTH and write_cmd = '1' then
captured <= sdi_reg;
end if;
end if;
end process;
reg0 <= captured;
process (clk)
begin
if rising_edge(clk) then
if cs_n = '1' then
sdo_reg <= x"AAAAAAAA";
sdo <= '0';
else
if write_cmd = '0' and clock_count > 12 then
sdo_reg <= '0' & sdo_reg(31 downto 1);
sdo <= sdo_reg(0);
else
sdo <= '0';
end if;
end if;
end if;
end process;
--process(clk, rst)
--begin
-- if rising_edge(clk) then
--
-- if rst = '1' then
-- recv_sm_reg <= HOLD_CMD;
-- commad <= (others=>'0');
-- cmd_valid <= '0';
--
-- else
--
-- --default
-- cmd_valid <= '0';
--
-- case recv_sm_reg is
-- when HOLD_CMD =>
-- if in_accept = '1' then
-- recv_sm_reg <= BYTE0_CMD;
-- end if;
--
-- when BYTE0_CMD => -- data
-- if in_val = '1' then
-- commad(7 downto 0) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE1_CMD;
-- end if;
-- when BYTE1_CMD =>
-- if in_val = '1' then
-- commad(15 downto 8) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE2_CMD;
-- end if;
-- when BYTE2_CMD =>
-- if in_val = '1' then
-- commad(23 downto 16) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE3_CMD;
-- end if;
-- when BYTE3_CMD =>
-- if in_val = '1' then
-- commad(31 downto 24) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE4_CMD;
-- end if;
--
-- when BYTE4_CMD => -- address
-- if in_val = '1' then
-- commad(39 downto 32) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE5_CMD;
-- end if;
-- when BYTE5_CMD =>
-- if in_val = '1' then
-- commad(47 downto 40) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE6_CMD;
-- end if;
-- when BYTE6_CMD =>
-- if in_val = '1' then
-- commad(55 downto 48) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE7_CMD;
-- end if;
-- when BYTE7_CMD =>
-- if in_val = '1' then
-- commad(63 downto 56) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE8_CMD;
-- end if;
--
-- when BYTE8_CMD => -- cmd
-- if in_val = '1' then
-- commad(71 downto 64) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE9_CMD;
-- end if;
-- when BYTE9_CMD =>
-- if in_val = '1' then
-- commad(79 downto 72) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE10_CMD;
-- end if;
-- when BYTE10_CMD =>
-- if in_val = '1' then
-- commad(87 downto 80) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE11_CMD;
-- end if;
-- when BYTE11_CMD =>
-- if in_val = '1' then
-- commad(95 downto 88) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE12_CMD;
-- end if;
--
-- when BYTE12_CMD => -- size
-- if in_val = '1' then
-- commad(103 downto 96) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE13_CMD;
-- end if;
-- when BYTE13_CMD =>
-- if in_val = '1' then
-- commad(111 downto 104) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE14_CMD;
-- end if;
-- when BYTE14_CMD =>
-- if in_val = '1' then
-- commad(119 downto 112) <= in_dat(7 downto 0);
-- recv_sm_reg <= BYTE15_CMD;
-- end if;
-- when BYTE15_CMD =>
-- if in_val = '1' then
-- commad(127 downto 120) <= in_dat(7 downto 0);
-- recv_sm_reg <= HOLD_CMD;
-- cmd_valid <= '1';
-- end if;
--
-- when others =>
-- recv_sm_reg <= HOLD_CMD;
--
-- end case;
--
-- end if;
--
-- end if;
--end process;
--
-------------------------------------------------------------------------------------
-- Counter process
-------------------------------------------------------------------------------------
--process(clk, rst)
--begin
-- if rising_edge(clk) then
-- if rst = '1' then
--
-- else
--
--
-- end if;
-- end if;
--end process;
-------------------------------------------------------------------------------------
-- Component Instance
-------------------------------------------------------------------------------------
--inst0_vp680_nnn_lx130t:
--entity work.vp680_nnn_lx130t
--generic map (
-- DEBUG => FALSE,
-- ADDRESS => "00010111111"
--)
--port map (
-- gpio_led_8 => ,
-- sys_clk_p_8 => ,
-- sys_clk_n_8 => ,
-- sys_reset_n_8 => ,
-- pci_exp_rxn_8 => ,
-- pci_exp_rxp_8 => ,
-- pci_exp_txn_8 => ,
-- pci_exp_txp_8 => ,
-- fp_cp_8 => ,
-- host_if_i2c_scl_8 =>
--);
-------------------------------------------------------------------------------------
-- Debug
-------------------------------------------------------------------------------------
--generate_debug:
--if (DEBUG_ENABLE = TRUE) generate
--begin
--
--end generate;
--generate_add_loop:
--for I in 0 to 7 generate
-- SUM(I) <= A(I) xor B(I) xor C(I);
-- C(I+1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
--end generate;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
-- Pulse emitter: Emits pulses at regular intervals when enabled
--
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity pulse_emitter is
generic (
MAX : integer
);
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
output : out std_logic
);
end pulse_emitter;
architecture BHV of pulse_emitter is
constant WIDTH : integer := integer(ceil(log2(real(MAX))));
signal count, next_count : unsigned(WIDTH-1 downto 0);
signal reached_max : std_logic;
begin
-- Break out the output signal
output <= reached_max;
-- Comparator for maximum value
process(count)
begin
if(count = MAX) then
reached_max <= '1';
else
reached_max <= '0';
end if;
end process;
-- Adder for the next count value
next_count <= count + 1;
-- Clocked process to increment the count register
process(rst, clk, count, next_count)
begin
if(rst = '1') then
count <= (others => '0');
elsif(rising_edge(clk)) then
if(en = '1') then
if(reached_max = '1') then
count <= (others => '0');
else
count <= next_count;
end if;
else
count <= count;
end if;
end if;
end process;
end BHV;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
freq : integer := 50000 -- frequency of main clock (used for PLLs)
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- flash/ssram bus
address : out std_logic_vector(25 downto 1);
data : inout std_logic_vector(31 downto 0);
romsn : out std_ulogic;
oen : out std_logic;
writen : out std_logic;
rstoutn : out std_ulogic;
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (0 to 3);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
-- ssram_adsp_n : out std_ulogic;
-- ssram_adv_n : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
-- pragma translate_on
ddr_clk : out std_logic;
ddr_clkn : out std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
-- debug support unit
dsubren : in std_ulogic;
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
gpio : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0) -- I/O port
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal lclk, lclkout : std_ulogic;
signal dsubre : std_ulogic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
clk_div => CFG_CLKDIV, sdramen => 1,
freq => freq)
port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
clk2x => open, sdclk => ssram_clkl, pciclk => open,
cgi => cgi, cgo => cgo);
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
rstoutn <= resetn;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 :mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
ramaddr => 16#400#+16#600#*CFG_DDRSP, rammask =>16#F00#, srbanks => 1,
sden => 0, ram16 => 1)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 0, pindex => 0,
iomask => 0, ramaddr => 16#400#+16#600#*CFG_DDRSP,
bus16 => CFG_SSCTRLP16)
port map (rstn, clkm, ahbsi, ahbso(0), apbi, apbo(0), memi, memo);
end generate;
mg0 : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech) port map (romsn, vcc(0));
end generate;
mgpads : if (CFG_MCTRL_LEON2 + CFG_SSCTRL) /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(25 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
-- pragma translate_on
-- ssram_adv_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adv_n, vcc(0));
-- ssram_adsp_n_pad : outpad generic map (tech => padtech)
-- port map (ssram_adsp_n, gnd(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssrams_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.oen);
ssram_rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.wrn);
ssram_wri_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 32)
port map (data(31 downto 0), memo.data(31 downto 0),
memo.vbdrive, memi.data(31 downto 0));
end generate;
ddrsp0 : if (CFG_DDRSP /= 0) generate
ddrc0 : ddrspa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000, rskew => CFG_DDRSP_RSKEW,
clkmul => CFG_DDRSP_FREQ/5, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 16, regoutput => 1)
port map (
resetn, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(3),
ddr_clkv, ddr_clkbv, open, gnd(0),
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkn <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
ddrsp1 : if (CFG_DDRSP = 0) generate
ddr_cke <= '0'; ddr_csb <= '1'; lock <= '1';
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
upads : if CFG_AHB_UART = 0 generate
u1i.rxd <= rxd1; txd1 <= u1o.txd;
end generate;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
gpioi.din(i) <= gpio(i);
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-- invert signal for input via a key
dsubre <= not dsubren;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP3C25 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
|
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
use ieee.vital_timing.all;
entity numeric_tb is
generic (
tperiod_CLK_posedge : VitalDelayType := 0.000 ns);
port (
CLK : in std_ulogic);
attribute VITAL_LEVEL0 of numeric_tb : entity is true;
end numeric_tb;
architecture test of numeric_tb is
begin
process
variable l : line;
begin
write(l, string'("tperiod_CLK_posedge = "));
write(l, tperiod_CLK_posedge);
writeline(output, l);
wait;
end process;
end;
|
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
use ieee.vital_timing.all;
entity numeric_tb is
generic (
tperiod_CLK_posedge : VitalDelayType := 0.000 ns);
port (
CLK : in std_ulogic);
attribute VITAL_LEVEL0 of numeric_tb : entity is true;
end numeric_tb;
architecture test of numeric_tb is
begin
process
variable l : line;
begin
write(l, string'("tperiod_CLK_posedge = "));
write(l, tperiod_CLK_posedge);
writeline(output, l);
wait;
end process;
end;
|
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_primitives.all;
use ieee.vital_timing.all;
entity numeric_tb is
generic (
tperiod_CLK_posedge : VitalDelayType := 0.000 ns);
port (
CLK : in std_ulogic);
attribute VITAL_LEVEL0 of numeric_tb : entity is true;
end numeric_tb;
architecture test of numeric_tb is
begin
process
variable l : line;
begin
write(l, string'("tperiod_CLK_posedge = "));
write(l, tperiod_CLK_posedge);
writeline(output, l);
wait;
end process;
end;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ac_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ac_e-e.vhd,v 1.3 2004/08/18 10:47:02 wig Exp $
-- $Date: 2004/08/18 10:47:02 $
-- $Log: inst_ac_e-e.vhd,v $
-- Revision 1.3 2004/08/18 10:47:02 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ac_e
--
entity inst_ac_e is
-- Generics:
-- No Generated Generics for Entity inst_ac_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ac_e
bus20040728_oc : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_ac_e
);
end inst_ac_e;
--
-- End of Generated Entity inst_ac_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
entity test is
subtype t is foo(bar)(0 to 2);
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inverting_integrator is
port ( terminal input, output : electrical;
signal rst : in std_ulogic );
end entity inverting_integrator;
----------------------------------------------------------------
architecture structural of inverting_integrator is
terminal internal : electrical;
begin
r1 : entity work.resistor(ideal)
port map ( node1 => input, node2 => internal);
c1 : entity work.capacitor(leakage)
port map ( node1 => internal, node2 => output );
amp : entity work.opamp(slew_limited)
port map ( plus_in => electrical_ref, minus_in => internal,
output => output);
switch : entity work.analog_switch(ideal)
port map ( n1 => internal, n2 => output, control => rst );
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inverting_integrator is
port ( terminal input, output : electrical;
signal rst : in std_ulogic );
end entity inverting_integrator;
----------------------------------------------------------------
architecture structural of inverting_integrator is
terminal internal : electrical;
begin
r1 : entity work.resistor(ideal)
port map ( node1 => input, node2 => internal);
c1 : entity work.capacitor(leakage)
port map ( node1 => internal, node2 => output );
amp : entity work.opamp(slew_limited)
port map ( plus_in => electrical_ref, minus_in => internal,
output => output);
switch : entity work.analog_switch(ideal)
port map ( n1 => internal, n2 => output, control => rst );
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inverting_integrator is
port ( terminal input, output : electrical;
signal rst : in std_ulogic );
end entity inverting_integrator;
----------------------------------------------------------------
architecture structural of inverting_integrator is
terminal internal : electrical;
begin
r1 : entity work.resistor(ideal)
port map ( node1 => input, node2 => internal);
c1 : entity work.capacitor(leakage)
port map ( node1 => internal, node2 => output );
amp : entity work.opamp(slew_limited)
port map ( plus_in => electrical_ref, minus_in => internal,
output => output);
switch : entity work.analog_switch(ideal)
port map ( n1 => internal, n2 => output, control => rst );
end architecture structural;
|
library ieee;
library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use WORK.alu_types.all;
use std.textio.all;
-- Entity
entity TREE is
generic(
N: integer := NSUMG;
LOGN: integer := LOG(NSUMG) -- The LOG function is in the P4ADDER_constants file
);
port(
A: in std_logic_vector(N-1 downto 0); -- N bit input
B: in std_logic_vector(N-1 downto 0); -- N bit input
Cin: in std_logic;
C: out std_logic_vector(N/4-1 downto 0) -- Generate a carry every fourth bit
);
end TREE;
-- Architectures
architecture STRUCTURAL of TREE is
-- Every internal signal is stored into a SignalVector. To try to increase the density of the array,
-- the first part of the matrix is contiguous in the rows: The first N elements are the members of the
-- first row, the following N/2 elements are of the second row, the following N/4 are of the third row,
-- and so on. In order to increase the understandability and lower the complexity of the code, however,
-- the signals related to the G/PG part of the tree are stored in a fixed-length fashion, where any
-- hole ( short-circuit ) in the matrix is saved as a direct connection.
--
-- The GETINDEX function handles the array, returning, given the element location ( row, column ), the
-- corresponding index in the array.
function GETINDEX(row : integer; col : integer) return integer is
variable result : integer;
begin
if row <= 2 then
-- report string'("case <= 3");
result := 2*N - 2 ** (LOGN + 1 - row ) + col; -- This returns the number of the column
else -- in which takes the input for the next row(PG or G group).
-- report string'("case > 3");
result := 7*N/4 + (row-3) * N/4 + col;
end if;
-- report integer'image(row) & string'(" - ") & integer'image(col) & string'(" => ") & integer'image(result);
return result;
end GETINDEX;
component INIT_PG
port(
A: in std_logic;
B: in std_logic;
PG: out std_logic_vector(1 downto 0) -- PG(0) = propagate; PG(1) = generate;
);
end component;
component TREE_G -- Gi:j = Gi:k + Pi:k * Gk-1:j;
port(
PG: in std_logic_vector(1 downto 0);-- PG(1) = Gi:k ; PG(0) = Pi:k;
GI: in std_logic; --GI = Gk-1:j;
GO: out std_logic
);
end component;
component TREE_PG -- Gi:j = Gi:k + Pi:k * Gk-1:j; Pi:j=Pi:k *Pk-1:j
port(
PG0: in std_logic_vector(1 downto 0); -- PG0(0) = Pi:k // PG0(1) = Gi:k
PG1: in std_logic_vector(1 downto 0); -- PG1(0) = Pk-1:j // PG1(1) = Gk-1:j
PGO: out std_logic_vector(1 downto 0) -- PGO(0) = Gi:j // PGO(1) = Pi:j
);
end component;
-- IC is an array of PG signals, which in turn are a couple of signals ( one for the
-- propagate bit ( index 0 ), and one for the generate one ( index 1 ).
type SignalVector is array (GETINDEX(LOGN, N/4) downto 0) of std_logic_vector(1 downto 0);
signal IC: SignalVector;
signal propagate_cin: std_logic_vector(1 downto 0);
begin
-- INIT_PG
-- The first row generates the p_i and g_i bits for all the a_i and
-- b_i bits. Their outputs are connected to the first N signals in IC.
GEN_INIT_PG: for col in 1 to N-1 generate
INIT_PGX: INIT_PG
port map(A => A(col), B => B(col), PG => IC(col));
end generate;
INIT_Cin: INIT_PG port map(A(0),B(0),propagate_cin);
CinPropagate: TREE_G port map(propagate_cin, Cin , IC(0)(1));
-- Main Tree
-- Being this a radix-2 sparse tree, this stage aggregates every four PG into a single signal.
-- It thus reduces the number of columns from N to N/4.
ROW_GEN: for row in 1 to 2 generate
COL_GEN: for col in 0 to N-1 generate
-- Current element -> G(row, col)
-- The first element is a TREE_G component.
-- i.e row = 1 and col = 0 takes as input propagate, generate of a(0) b(0)
-- generate of a(1),b(1) - output G1:0
COLUMN_0 : if col = 0 generate
TREE_GX: TREE_G
port map(IC(GETINDEX(row-1, 1)), IC(GETINDEX(row-1, 0))(1), IC(GETINDEX(row, col))(1));
end generate COLUMN_0;
-- Elsewise it's a TREE_PG component.
-- i.e row = 1 and col = 1 takes as input propagate,generate of a(3),b(3) generate
-- of a(2),b(2) - output P3:2 G3:2.
-- i.e row = 2 and col = 1 takes as input G1:0,P3:2 and G3:2 - output G3:0=carry4
-- as shown in the text figure(instead of starting from 1 for a and b we start from 0).
COLUMN_N : if col > 0 and col < (N/(2**row)) generate
TREE_PGX: TREE_PG
port map(IC(GETINDEX(row-1, (2*col+1))), IC(GETINDEX(row-1, 2*col)), IC(GETINDEX(row, col)));
end generate COLUMN_N;
end generate;
end generate;
-- G/PG Network
-- This represents the final stage of the tree, where the number of consecutive blocks increases,
-- specifically in an exponential way ( 2^row ). This algorithm takes care of the proper generation
-- of the blocks and the relative connections between its parts.
--
-- The term ((col - ( col mod (2**row) ))/(2**row)) evaluates the group number for a column in a row,
-- being a group the consecutive instantiation of components of the same type. This is useful to know
-- because it allows us to know the type of the component to generate by only knowing its position (
-- row and column ) in the matrix/tree. Specifically: even groups are made of wires ( connection between
-- vertically ( same column ) adjacent cells ), while odd groups are a TREE_G ( if the group number is
-- 1 ) or a TREE_PG.
RED_ROW: for row in 0 to (LOGN-3) generate
RED_COL: for col in 0 to N/4-1 generate
-- Group number is even ( X mod 2 = 0 ) -> Connection
RED_BUF: if ((col - ( col mod (2**row) ))/(2**row)) mod 2 = 0 generate
IC(GETINDEX(row+3, col)) <= IC(GETINDEX(row+3-1, col));
end generate RED_BUF;
-- Group number is 1 ( X = 1 ) -> Generate
RED_G: if((col - ( col mod (2**row) ))/(2**row)) = 1 generate
RED_G_GX: TREE_G
port map(
IC(GETINDEX(row+3-1, col)),
IC(GETINDEX(row+3-1, (2**row)-1))(1),
IC(GETINDEX(row+3, col))(1)
);
end generate RED_G;
-- Group number is odd and different from 1 ( X mod 2 != 0 and X != 1) -> Propagate / Generate
RED_PG: if
((col - ( col mod (2**row) ))/(2**row)) mod 2 /= 0 and
((col - ( col mod (2**row) ))/(2**row)) /= 1
generate
RED_PG_GX: TREE_PG
port map(
IC(GETINDEX(row+3-1, col)),
IC(GETINDEX(row+3-1, (col - col mod (2**row))-1)),
IC(GETINDEX(row+3, col))
);
end generate RED_PG;
end generate RED_COL;
end generate RED_ROW;
-- COUT
-- The last row of the matrix/tree is made of TREE_G blocks, or connections leading to the corresponding
-- TREE_G block. We can just attach its G bit ( index 1 ) to the output vector.
COUT_GEN: for col in 0 to N/4-1 generate
C(col) <= IC(GETINDEX(LOGN, col))(1);
end generate COUT_GEN;
end STRUCTURAL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector is
begin
if(unsigned(word) < 10) then
return "0011" & word;
elsif(unsigned(word) = 11) then
return "01100001";
elsif(unsigned(word) = 12) then
return "01100010";
elsif(unsigned(word) = 13) then
return "01100011";
elsif(unsigned(word) = 14) then
return "01100100";
elsif(unsigned(word) = 15) then
return "01100100";
else
return "00110000";
end if;
end;
end config;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY bytefifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF bytefifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY bytefifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF bytefifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bytefifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY bytefifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF bytefifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
entity generic_spram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 1024;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := false;
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "write_first";
g_init_file : string := ""
);
port (
rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- byte write enable, actiwe when g_
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
-- global write enable (masked by bwe_i if g_with_byte_enable = true)
we_i : in std_logic;
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_spram;
architecture syn of generic_spram is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
type t_string_file_type is file of string;
impure function f_bitstring_2_slv(s : string; num_bits : integer) return std_logic_vector is
begin
end function f_bitstring_2_slv;
impure function f_load_from_file(file_name : string) return t_ram_type is
file f : t_string_file_type;
variable fstatus : file_open_status;
begin
file_open(fstatus, f, file_name, read_mode);
if(fstatus /= open_ok) then
report "generic_spram: Cannot open memory initialization file: " & file_name severity failure;
end if;
end function f_load_from_file;
signal ram : t_ram_type;
signal s_we : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in : std_logic_vector(g_data_width-1 downto 0);
signal s_ram_out : std_logic_vector(g_data_width-1 downto 0);
begin
assert (g_init_file = "" or g_init_file = "none")
report "generic_spram: Memory initialization files not supported yet. Sorry :("
severity failure;
gen_with_byte_enable_writefirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "write_first") generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if s_we(i) = '1' then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
s_ram_out(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop; -- i
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= s_ram_out;
end if;
end process;
end generate gen_with_byte_enable_writefirst;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
s_we <= bwe_i when we_i = '1' else (others => '0');
process(s_we, d_i)
begin
for i in 0 to c_num_bytes-1 loop
if (s_we(i) = '1') then
s_ram_in(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
else
s_ram_in(8*i+7 downto 8*i) <= ram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
ram(conv_integer(unsigned(a_i))) <= s_ram_in;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
q_o <= d_i;
else
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and (g_addr_conflict_resolution = "read_first" or
g_addr_conflict_resolution = "dont_care")) generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(we_i = '1') then
ram(conv_integer(unsigned(a_i))) <= d_i;
end if;
q_o <= ram(conv_integer(unsigned(a_i)));
end if;
end process;
end generate gen_without_byte_enable_readfirst;
end syn;
|
----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
|
----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
|
----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
|
----------------------------------------------------------------------------
-- UART_TX_CTRL.vhd -- UART Data Transfer Component
----------------------------------------------------------------------------
-- Author: Sam Bobrowicz
-- Copyright 2011 Digilent, Inc.
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- This component may be used to transfer data over a UART device. It will
-- serialize a byte of data and transmit it over a TXD line. The serialized
-- data has the following characteristics:
-- *9600 Baud Rate
-- *8 data bits, LSB first
-- *1 stop bit
-- *no parity
--
-- Port Descriptions:
--
-- SEND - Used to trigger a send operation. The upper layer logic should
-- set this signal high for a single clock cycle to trigger a
-- send. When this signal is set high DATA must be valid . Should
-- not be asserted unless READY is high.
-- DATA - The parallel data to be sent. Must be valid the clock cycle
-- that SEND has gone high.
-- CLK - A 100 MHz clock is expected
-- READY - This signal goes low once a send operation has begun and
-- remains low until it has completed and the module is ready to
-- send another byte.
-- UART_TX - This signal should be routed to the appropriate TX pin of the
-- external UART device.
--
----------------------------------------------------------------------------
--
----------------------------------------------------------------------------
-- Revision History:
-- 08/08/2011(SamB): Created using Xilinx Tools 13.2
----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity UART_TX_CTRL is
Port ( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end UART_TX_CTRL;
architecture Behavioral of UART_TX_CTRL is
type TX_STATE_TYPE is (RDY, LOAD_BIT, SEND_BIT);
constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;
--Counter that keeps track of the number of clock cycles the current bit has been held stable over the
--UART TX line. It is used to signal when the ne
signal bitTmr : std_logic_vector(13 downto 0) := (others => '0');
--combinatorial logic that goes high when bitTmr has counted to the proper value to ensure
--a 9600 baud rate
signal bitDone : std_logic;
--Contains the index of the next bit in txData that needs to be transferred
signal bitIndex : natural;
--a register that holds the current data being sent over the UART TX line
signal txBit : std_logic := '1';
--A register that contains the whole data packet to be sent, including start and stop bits.
signal txData : std_logic_vector(9 downto 0);
signal txState : TX_STATE_TYPE := RDY;
begin
--Next state logic
next_txState_process : process (CLK)
begin
if (rising_edge(CLK)) then
case txState is
when RDY =>
if (SEND = '1') then
txState <= LOAD_BIT;
end if;
when LOAD_BIT =>
txState <= SEND_BIT;
when SEND_BIT =>
if (bitDone = '1') then
if (bitIndex = BIT_INDEX_MAX) then
txState <= RDY;
else
txState <= LOAD_BIT;
end if;
end if;
when others=> --should never be reached
txState <= RDY;
end case;
end if;
end process;
bit_timing_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitTmr <= (others => '0');
else
if (bitDone = '1') then
bitTmr <= (others => '0');
else
bitTmr <= bitTmr + 1;
end if;
end if;
end if;
end process;
bitDone <= '1' when (bitTmr = BIT_TMR_MAX) else
'0';
bit_counting_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
bitIndex <= 0;
elsif (txState = LOAD_BIT) then
bitIndex <= bitIndex + 1;
end if;
end if;
end process;
tx_data_latch_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (SEND = '1') then
txData <= '1' & DATA & '0';
end if;
end if;
end process;
tx_bit_process : process (CLK)
begin
if (rising_edge(CLK)) then
if (txState = RDY) then
txBit <= '1';
elsif (txState = LOAD_BIT) then
txBit <= txData(bitIndex);
end if;
end if;
end process;
UART_TX <= txBit;
READY <= '1' when (txState = RDY) else
'0';
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : TRFSM Package
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package TRFSMPkg is
component TRFSM
generic (
InputWidth : integer range 1 to 256;
OutputWidth : integer range 1 to 256;
StateWidth : integer range 1 to 8;
UseResetRow : integer range 0 to 1;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
-- Configuration
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
-- Scan Chain
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
end TRFSMPkg;
package body TRFSMPkg is
end TRFSMPkg;
|
-------------------------------------------------------------------------------
-- Title : TRFSM Package
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package TRFSMPkg is
component TRFSM
generic (
InputWidth : integer range 1 to 256;
OutputWidth : integer range 1 to 256;
StateWidth : integer range 1 to 8;
UseResetRow : integer range 0 to 1;
NumRows0 : integer;
NumRows1 : integer;
NumRows2 : integer;
NumRows3 : integer;
NumRows4 : integer;
NumRows5 : integer;
NumRows6 : integer;
NumRows7 : integer;
NumRows8 : integer;
NumRows9 : integer
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
-- Configuration
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic;
-- Scan Chain
ScanEnable_i : in std_logic;
ScanClk_i : in std_logic;
ScanDataIn_i : in std_logic;
ScanDataOut_o : out std_logic
);
end component;
end TRFSMPkg;
package body TRFSMPkg is
end TRFSMPkg;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Nov 29 13:29:43 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.3 2005/11/30 14:04:00 wig Exp $
-- $Date: 2005/11/30 14:04:00 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.3 2005/11/30 14:04:00 wig
-- Updated testcase references
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : cntr_top_.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: This is the entity declaration of the fulladder submodule
-- of the VHDL class example.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity cntr_top is
port (clk_i : in std_logic; -- clock input
reset_i : in std_logic; -- central reset
sw_i : in std_logic_vector(15 downto 0); -- 16 input switches
pb_i : in std_logic_vector(3 downto 0); -- 4 control buttons
ss_o : out std_logic_vector(7 downto 0); -- data for all 7-segment digits
ss_sel_o : out std_logic_vector(3 downto 0)); -- selection vector for the 7-segment digit
end cntr_top;
|
-- nios_tester.vhd
-- Generated using ACDS version 18.1 625
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_tester is
port (
audio_in_data : in std_logic_vector(31 downto 0) := (others => '0'); -- audio_in.data
audio_in_valid : in std_logic := '0'; -- .valid
audio_in_ready : out std_logic; -- .ready
audio_out_data : out std_logic_vector(31 downto 0); -- audio_out.data
audio_out_valid : out std_logic; -- .valid
audio_out_ready : in std_logic := '0'; -- .ready
dummy_export : in std_logic := '0'; -- dummy.export
io_ack : in std_logic := '0'; -- io.ack
io_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_read : out std_logic; -- .read
io_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_write : out std_logic; -- .write
io_address : out std_logic_vector(19 downto 0); -- .address
io_irq : in std_logic := '0'; -- .irq
io_u2p_ack : in std_logic := '0'; -- io_u2p.ack
io_u2p_rdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .rdata
io_u2p_read : out std_logic; -- .read
io_u2p_wdata : out std_logic_vector(7 downto 0); -- .wdata
io_u2p_write : out std_logic; -- .write
io_u2p_address : out std_logic_vector(19 downto 0); -- .address
io_u2p_irq : in std_logic := '0'; -- .irq
jtag0_jtag_tck : out std_logic; -- jtag0.jtag_tck
jtag0_jtag_tms : out std_logic; -- .jtag_tms
jtag0_jtag_tdi : out std_logic; -- .jtag_tdi
jtag0_jtag_tdo : in std_logic := '0'; -- .jtag_tdo
jtag1_jtag_tck : out std_logic; -- jtag1.jtag_tck
jtag1_jtag_tms : out std_logic; -- .jtag_tms
jtag1_jtag_tdi : out std_logic; -- .jtag_tdi
jtag1_jtag_tdo : in std_logic := '0'; -- .jtag_tdo
jtag_in_data : in std_logic_vector(7 downto 0) := (others => '0'); -- jtag_in.data
jtag_in_valid : in std_logic := '0'; -- .valid
jtag_in_ready : out std_logic; -- .ready
mem_mem_req_address : out std_logic_vector(25 downto 0); -- mem.mem_req_address
mem_mem_req_byte_en : out std_logic_vector(3 downto 0); -- .mem_req_byte_en
mem_mem_req_read_writen : out std_logic; -- .mem_req_read_writen
mem_mem_req_request : out std_logic; -- .mem_req_request
mem_mem_req_tag : out std_logic_vector(7 downto 0); -- .mem_req_tag
mem_mem_req_wdata : out std_logic_vector(31 downto 0); -- .mem_req_wdata
mem_mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .mem_resp_dack_tag
mem_mem_resp_data : in std_logic_vector(31 downto 0) := (others => '0'); -- .mem_resp_data
mem_mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => '0'); -- .mem_resp_rack_tag
pio_in_port : in std_logic_vector(31 downto 0) := (others => '0'); -- pio.in_port
pio_out_port : out std_logic_vector(31 downto 0); -- .out_port
spi_MISO : in std_logic := '0'; -- spi.MISO
spi_MOSI : out std_logic; -- .MOSI
spi_SCLK : out std_logic; -- .SCLK
spi_SS_n : out std_logic; -- .SS_n
sys_clock_clk : in std_logic := '0'; -- sys_clock.clk
sys_reset_reset_n : in std_logic := '0' -- sys_reset.reset_n
);
end entity nios_tester;
architecture rtl of nios_tester is
component nios_tester_audio_in_dma is
port (
mm_write_address : out std_logic_vector(25 downto 0); -- address
mm_write_write : out std_logic; -- write
mm_write_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mm_write_writedata : out std_logic_vector(31 downto 0); -- writedata
mm_write_waitrequest : in std_logic := 'X'; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_sink_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- data
st_sink_valid : in std_logic := 'X'; -- valid
st_sink_ready : out std_logic -- ready
);
end component nios_tester_audio_in_dma;
component nios_tester_audio_out_dma is
port (
mm_read_address : out std_logic_vector(25 downto 0); -- address
mm_read_read : out std_logic; -- read
mm_read_byteenable : out std_logic_vector(3 downto 0); -- byteenable
mm_read_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
mm_read_waitrequest : in std_logic := 'X'; -- waitrequest
mm_read_readdatavalid : in std_logic := 'X'; -- readdatavalid
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_source_data : out std_logic_vector(31 downto 0); -- data
st_source_valid : out std_logic; -- valid
st_source_ready : in std_logic := 'X' -- ready
);
end component nios_tester_audio_out_dma;
component avalon_to_mem32_bridge is
generic (
g_tag : std_logic_vector(7 downto 0) := "01011011"
);
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
avs_waitrequest : out std_logic; -- waitrequest
avs_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
mem_req_address : out std_logic_vector(25 downto 0); -- mem_req_address
mem_req_byte_en : out std_logic_vector(3 downto 0); -- mem_req_byte_en
mem_req_read_writen : out std_logic; -- mem_req_read_writen
mem_req_request : out std_logic; -- mem_req_request
mem_req_tag : out std_logic_vector(7 downto 0); -- mem_req_tag
mem_req_wdata : out std_logic_vector(31 downto 0); -- mem_req_wdata
mem_resp_dack_tag : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_resp_dack_tag
mem_resp_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- mem_resp_data
mem_resp_rack_tag : in std_logic_vector(7 downto 0) := (others => 'X') -- mem_resp_rack_tag
);
end component avalon_to_mem32_bridge;
component avalon_to_io_bridge is
port (
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(19 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(7 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
clock : in std_logic := 'X'; -- clk
io_ack : in std_logic := 'X'; -- ack
io_rdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- rdata
io_read : out std_logic; -- read
io_wdata : out std_logic_vector(7 downto 0); -- wdata
io_write : out std_logic; -- write
io_address : out std_logic_vector(19 downto 0); -- address
io_irq : in std_logic := 'X'; -- irq
avs_irq : out std_logic -- irq
);
end component avalon_to_io_bridge;
component jtag_host is
port (
clock : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
avs_read : in std_logic := 'X'; -- read
avs_write : in std_logic := 'X'; -- write
avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_ready : out std_logic; -- waitrequest_n
avs_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_readdatavalid : out std_logic; -- readdatavalid
jtag_tck : out std_logic; -- jtag_tck
jtag_tms : out std_logic; -- jtag_tms
jtag_tdi : out std_logic; -- jtag_tdi
jtag_tdo : in std_logic := 'X' -- jtag_tdo
);
end component jtag_host;
component nios_tester_jtagdebug is
port (
mm_write_address : out std_logic_vector(25 downto 0); -- address
mm_write_write : out std_logic; -- write
mm_write_writedata : out std_logic_vector(7 downto 0); -- writedata
mm_write_waitrequest : in std_logic := 'X'; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_n_reset_n : in std_logic := 'X'; -- reset_n
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
csr_write : in std_logic := 'X'; -- write
csr_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_read : in std_logic := 'X'; -- read
csr_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
descriptor_slave_write : in std_logic := 'X'; -- write
descriptor_slave_waitrequest : out std_logic; -- waitrequest
descriptor_slave_writedata : in std_logic_vector(127 downto 0) := (others => 'X'); -- writedata
descriptor_slave_byteenable : in std_logic_vector(15 downto 0) := (others => 'X'); -- byteenable
csr_irq_irq : out std_logic; -- irq
st_sink_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
st_sink_valid : in std_logic := 'X'; -- valid
st_sink_ready : out std_logic -- ready
);
end component nios_tester_jtagdebug;
component nios_tester_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(31 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(29 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component nios_tester_nios2_gen2_0;
component nios_tester_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X'; -- reset_req
freeze : in std_logic := 'X' -- freeze
);
end component nios_tester_onchip_memory2_0;
component nios_tester_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic := 'X'; -- export
irq : out std_logic -- irq
);
end component nios_tester_pio_0;
component nios_tester_pio_1 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
in_port : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
out_port : out std_logic_vector(31 downto 0) -- export
);
end component nios_tester_pio_1;
component nios_tester_spi_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
data_from_cpu : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
data_to_cpu : out std_logic_vector(15 downto 0); -- readdata
mem_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
read_n : in std_logic := 'X'; -- read_n
spi_select : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic; -- irq
MISO : in std_logic := 'X'; -- export
MOSI : out std_logic; -- export
SCLK : out std_logic; -- export
SS_n : out std_logic -- export
);
end component nios_tester_spi_0;
component nios_tester_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
audio_in_dma_mm_write_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
audio_in_dma_mm_write_waitrequest : out std_logic; -- waitrequest
audio_in_dma_mm_write_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
audio_in_dma_mm_write_write : in std_logic := 'X'; -- write
audio_in_dma_mm_write_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
audio_out_dma_mm_read_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
audio_out_dma_mm_read_waitrequest : out std_logic; -- waitrequest
audio_out_dma_mm_read_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
audio_out_dma_mm_read_read : in std_logic := 'X'; -- read
audio_out_dma_mm_read_readdata : out std_logic_vector(31 downto 0); -- readdata
audio_out_dma_mm_read_readdatavalid : out std_logic; -- readdatavalid
jtagdebug_mm_write_address : in std_logic_vector(25 downto 0) := (others => 'X'); -- address
jtagdebug_mm_write_waitrequest : out std_logic; -- waitrequest
jtagdebug_mm_write_write : in std_logic := 'X'; -- write
jtagdebug_mm_write_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_address : in std_logic_vector(31 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(29 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
audio_in_dma_csr_address : out std_logic_vector(2 downto 0); -- address
audio_in_dma_csr_write : out std_logic; -- write
audio_in_dma_csr_read : out std_logic; -- read
audio_in_dma_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
audio_in_dma_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_in_dma_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
audio_in_dma_descriptor_slave_write : out std_logic; -- write
audio_in_dma_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
audio_in_dma_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
audio_in_dma_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
audio_out_dma_csr_address : out std_logic_vector(2 downto 0); -- address
audio_out_dma_csr_write : out std_logic; -- write
audio_out_dma_csr_read : out std_logic; -- read
audio_out_dma_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
audio_out_dma_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
audio_out_dma_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
audio_out_dma_descriptor_slave_write : out std_logic; -- write
audio_out_dma_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
audio_out_dma_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
audio_out_dma_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
avalon2mem_0_avalon_slave_0_address : out std_logic_vector(25 downto 0); -- address
avalon2mem_0_avalon_slave_0_write : out std_logic; -- write
avalon2mem_0_avalon_slave_0_read : out std_logic; -- read
avalon2mem_0_avalon_slave_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
avalon2mem_0_avalon_slave_0_writedata : out std_logic_vector(31 downto 0); -- writedata
avalon2mem_0_avalon_slave_0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
avalon2mem_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
avalon2mem_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_0_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_0_avalon_slave_0_write : out std_logic; -- write
io_bridge_0_avalon_slave_0_read : out std_logic; -- read
io_bridge_0_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_0_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
io_bridge_1_avalon_slave_0_address : out std_logic_vector(19 downto 0); -- address
io_bridge_1_avalon_slave_0_write : out std_logic; -- write
io_bridge_1_avalon_slave_0_read : out std_logic; -- read
io_bridge_1_avalon_slave_0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata
io_bridge_1_avalon_slave_0_writedata : out std_logic_vector(7 downto 0); -- writedata
io_bridge_1_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
io_bridge_1_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_0_avalon_slave_0_address : out std_logic_vector(7 downto 0); -- address
jtag_0_avalon_slave_0_write : out std_logic; -- write
jtag_0_avalon_slave_0_read : out std_logic; -- read
jtag_0_avalon_slave_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_0_avalon_slave_0_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_0_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
jtag_0_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_1_avalon_slave_0_address : out std_logic_vector(7 downto 0); -- address
jtag_1_avalon_slave_0_write : out std_logic; -- write
jtag_1_avalon_slave_0_read : out std_logic; -- read
jtag_1_avalon_slave_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_1_avalon_slave_0_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_1_avalon_slave_0_readdatavalid : in std_logic := 'X'; -- readdatavalid
jtag_1_avalon_slave_0_waitrequest : in std_logic := 'X'; -- waitrequest
jtagdebug_csr_address : out std_logic_vector(2 downto 0); -- address
jtagdebug_csr_write : out std_logic; -- write
jtagdebug_csr_read : out std_logic; -- read
jtagdebug_csr_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtagdebug_csr_writedata : out std_logic_vector(31 downto 0); -- writedata
jtagdebug_csr_byteenable : out std_logic_vector(3 downto 0); -- byteenable
jtagdebug_descriptor_slave_write : out std_logic; -- write
jtagdebug_descriptor_slave_writedata : out std_logic_vector(127 downto 0); -- writedata
jtagdebug_descriptor_slave_byteenable : out std_logic_vector(15 downto 0); -- byteenable
jtagdebug_descriptor_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(8 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
pio_1_s1_address : out std_logic_vector(2 downto 0); -- address
pio_1_s1_write : out std_logic; -- write
pio_1_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_1_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_1_s1_chipselect : out std_logic; -- chipselect
spi_0_spi_control_port_address : out std_logic_vector(2 downto 0); -- address
spi_0_spi_control_port_write : out std_logic; -- write
spi_0_spi_control_port_read : out std_logic; -- read
spi_0_spi_control_port_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
spi_0_spi_control_port_writedata : out std_logic_vector(15 downto 0); -- writedata
spi_0_spi_control_port_chipselect : out std_logic -- chipselect
);
end component nios_tester_mm_interconnect_0;
component nios_tester_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
receiver4_irq : in std_logic := 'X'; -- irq
receiver5_irq : in std_logic := 'X'; -- irq
receiver6_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component nios_tester_irq_mapper;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(29 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal audio_out_dma_mm_read_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_out_dma_mm_read_readdata -> audio_out_dma:mm_read_readdata
signal audio_out_dma_mm_read_waitrequest : std_logic; -- mm_interconnect_0:audio_out_dma_mm_read_waitrequest -> audio_out_dma:mm_read_waitrequest
signal audio_out_dma_mm_read_address : std_logic_vector(25 downto 0); -- audio_out_dma:mm_read_address -> mm_interconnect_0:audio_out_dma_mm_read_address
signal audio_out_dma_mm_read_read : std_logic; -- audio_out_dma:mm_read_read -> mm_interconnect_0:audio_out_dma_mm_read_read
signal audio_out_dma_mm_read_byteenable : std_logic_vector(3 downto 0); -- audio_out_dma:mm_read_byteenable -> mm_interconnect_0:audio_out_dma_mm_read_byteenable
signal audio_out_dma_mm_read_readdatavalid : std_logic; -- mm_interconnect_0:audio_out_dma_mm_read_readdatavalid -> audio_out_dma:mm_read_readdatavalid
signal audio_in_dma_mm_write_waitrequest : std_logic; -- mm_interconnect_0:audio_in_dma_mm_write_waitrequest -> audio_in_dma:mm_write_waitrequest
signal audio_in_dma_mm_write_address : std_logic_vector(25 downto 0); -- audio_in_dma:mm_write_address -> mm_interconnect_0:audio_in_dma_mm_write_address
signal audio_in_dma_mm_write_byteenable : std_logic_vector(3 downto 0); -- audio_in_dma:mm_write_byteenable -> mm_interconnect_0:audio_in_dma_mm_write_byteenable
signal audio_in_dma_mm_write_write : std_logic; -- audio_in_dma:mm_write_write -> mm_interconnect_0:audio_in_dma_mm_write_write
signal audio_in_dma_mm_write_writedata : std_logic_vector(31 downto 0); -- audio_in_dma:mm_write_writedata -> mm_interconnect_0:audio_in_dma_mm_write_writedata
signal jtagdebug_mm_write_waitrequest : std_logic; -- mm_interconnect_0:jtagdebug_mm_write_waitrequest -> jtagdebug:mm_write_waitrequest
signal jtagdebug_mm_write_address : std_logic_vector(25 downto 0); -- jtagdebug:mm_write_address -> mm_interconnect_0:jtagdebug_mm_write_address
signal jtagdebug_mm_write_write : std_logic; -- jtagdebug:mm_write_write -> mm_interconnect_0:jtagdebug_mm_write_write
signal jtagdebug_mm_write_writedata : std_logic_vector(7 downto 0); -- jtagdebug:mm_write_writedata -> mm_interconnect_0:jtagdebug_mm_write_writedata
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_1:avs_readdata -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdata
signal io_bridge_1_avalon_slave_0_waitrequest : std_logic; -- io_bridge_1:avs_ready -> io_bridge_1_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_1_avalon_slave_0_address -> io_bridge_1:avs_address
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_1_avalon_slave_0_read -> io_bridge_1:avs_read
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_1:avs_readdatavalid -> mm_interconnect_0:io_bridge_1_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_1_avalon_slave_0_write -> io_bridge_1:avs_write
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_1_avalon_slave_0_writedata -> io_bridge_1:avs_writedata
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata : std_logic_vector(31 downto 0); -- avalon2mem_0:avs_readdata -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdata
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest : std_logic; -- avalon2mem_0:avs_waitrequest -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_address : std_logic_vector(25 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_address -> avalon2mem_0:avs_address
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_read -> avalon2mem_0:avs_read
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_byteenable -> avalon2mem_0:avs_byteenable
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid : std_logic; -- avalon2mem_0:avs_readdatavalid -> mm_interconnect_0:avalon2mem_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_write -> avalon2mem_0:avs_write
signal mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:avalon2mem_0_avalon_slave_0_writedata -> avalon2mem_0:avs_writedata
signal mm_interconnect_0_jtag_0_avalon_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_0:avs_readdata -> mm_interconnect_0:jtag_0_avalon_slave_0_readdata
signal jtag_0_avalon_slave_0_waitrequest : std_logic; -- jtag_0:avs_ready -> jtag_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_jtag_0_avalon_slave_0_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:jtag_0_avalon_slave_0_address -> jtag_0:avs_address
signal mm_interconnect_0_jtag_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:jtag_0_avalon_slave_0_read -> jtag_0:avs_read
signal mm_interconnect_0_jtag_0_avalon_slave_0_readdatavalid : std_logic; -- jtag_0:avs_readdatavalid -> mm_interconnect_0:jtag_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_jtag_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:jtag_0_avalon_slave_0_write -> jtag_0:avs_write
signal mm_interconnect_0_jtag_0_avalon_slave_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_0_avalon_slave_0_writedata -> jtag_0:avs_writedata
signal mm_interconnect_0_jtag_1_avalon_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_1:avs_readdata -> mm_interconnect_0:jtag_1_avalon_slave_0_readdata
signal jtag_1_avalon_slave_0_waitrequest : std_logic; -- jtag_1:avs_ready -> jtag_1_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_jtag_1_avalon_slave_0_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:jtag_1_avalon_slave_0_address -> jtag_1:avs_address
signal mm_interconnect_0_jtag_1_avalon_slave_0_read : std_logic; -- mm_interconnect_0:jtag_1_avalon_slave_0_read -> jtag_1:avs_read
signal mm_interconnect_0_jtag_1_avalon_slave_0_readdatavalid : std_logic; -- jtag_1:avs_readdatavalid -> mm_interconnect_0:jtag_1_avalon_slave_0_readdatavalid
signal mm_interconnect_0_jtag_1_avalon_slave_0_write : std_logic; -- mm_interconnect_0:jtag_1_avalon_slave_0_write -> jtag_1:avs_write
signal mm_interconnect_0_jtag_1_avalon_slave_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_1_avalon_slave_0_writedata -> jtag_1:avs_writedata
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata : std_logic_vector(7 downto 0); -- io_bridge_0:avs_readdata -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdata
signal io_bridge_0_avalon_slave_0_waitrequest : std_logic; -- io_bridge_0:avs_ready -> io_bridge_0_avalon_slave_0_waitrequest:in
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_address : std_logic_vector(19 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_address -> io_bridge_0:avs_address
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_read : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_read -> io_bridge_0:avs_read
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid : std_logic; -- io_bridge_0:avs_readdatavalid -> mm_interconnect_0:io_bridge_0_avalon_slave_0_readdatavalid
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_write : std_logic; -- mm_interconnect_0:io_bridge_0_avalon_slave_0_write -> io_bridge_0:avs_write
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata : std_logic_vector(7 downto 0); -- mm_interconnect_0:io_bridge_0_avalon_slave_0_writedata -> io_bridge_0:avs_writedata
signal mm_interconnect_0_audio_out_dma_csr_readdata : std_logic_vector(31 downto 0); -- audio_out_dma:csr_readdata -> mm_interconnect_0:audio_out_dma_csr_readdata
signal mm_interconnect_0_audio_out_dma_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:audio_out_dma_csr_address -> audio_out_dma:csr_address
signal mm_interconnect_0_audio_out_dma_csr_read : std_logic; -- mm_interconnect_0:audio_out_dma_csr_read -> audio_out_dma:csr_read
signal mm_interconnect_0_audio_out_dma_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:audio_out_dma_csr_byteenable -> audio_out_dma:csr_byteenable
signal mm_interconnect_0_audio_out_dma_csr_write : std_logic; -- mm_interconnect_0:audio_out_dma_csr_write -> audio_out_dma:csr_write
signal mm_interconnect_0_audio_out_dma_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_out_dma_csr_writedata -> audio_out_dma:csr_writedata
signal mm_interconnect_0_audio_in_dma_csr_readdata : std_logic_vector(31 downto 0); -- audio_in_dma:csr_readdata -> mm_interconnect_0:audio_in_dma_csr_readdata
signal mm_interconnect_0_audio_in_dma_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:audio_in_dma_csr_address -> audio_in_dma:csr_address
signal mm_interconnect_0_audio_in_dma_csr_read : std_logic; -- mm_interconnect_0:audio_in_dma_csr_read -> audio_in_dma:csr_read
signal mm_interconnect_0_audio_in_dma_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:audio_in_dma_csr_byteenable -> audio_in_dma:csr_byteenable
signal mm_interconnect_0_audio_in_dma_csr_write : std_logic; -- mm_interconnect_0:audio_in_dma_csr_write -> audio_in_dma:csr_write
signal mm_interconnect_0_audio_in_dma_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:audio_in_dma_csr_writedata -> audio_in_dma:csr_writedata
signal mm_interconnect_0_jtagdebug_csr_readdata : std_logic_vector(31 downto 0); -- jtagdebug:csr_readdata -> mm_interconnect_0:jtagdebug_csr_readdata
signal mm_interconnect_0_jtagdebug_csr_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:jtagdebug_csr_address -> jtagdebug:csr_address
signal mm_interconnect_0_jtagdebug_csr_read : std_logic; -- mm_interconnect_0:jtagdebug_csr_read -> jtagdebug:csr_read
signal mm_interconnect_0_jtagdebug_csr_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:jtagdebug_csr_byteenable -> jtagdebug:csr_byteenable
signal mm_interconnect_0_jtagdebug_csr_write : std_logic; -- mm_interconnect_0:jtagdebug_csr_write -> jtagdebug:csr_write
signal mm_interconnect_0_jtagdebug_csr_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtagdebug_csr_writedata -> jtagdebug:csr_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest : std_logic; -- audio_out_dma:descriptor_slave_waitrequest -> mm_interconnect_0:audio_out_dma_descriptor_slave_waitrequest
signal mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:audio_out_dma_descriptor_slave_byteenable -> audio_out_dma:descriptor_slave_byteenable
signal mm_interconnect_0_audio_out_dma_descriptor_slave_write : std_logic; -- mm_interconnect_0:audio_out_dma_descriptor_slave_write -> audio_out_dma:descriptor_slave_write
signal mm_interconnect_0_audio_out_dma_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:audio_out_dma_descriptor_slave_writedata -> audio_out_dma:descriptor_slave_writedata
signal mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest : std_logic; -- audio_in_dma:descriptor_slave_waitrequest -> mm_interconnect_0:audio_in_dma_descriptor_slave_waitrequest
signal mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:audio_in_dma_descriptor_slave_byteenable -> audio_in_dma:descriptor_slave_byteenable
signal mm_interconnect_0_audio_in_dma_descriptor_slave_write : std_logic; -- mm_interconnect_0:audio_in_dma_descriptor_slave_write -> audio_in_dma:descriptor_slave_write
signal mm_interconnect_0_audio_in_dma_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:audio_in_dma_descriptor_slave_writedata -> audio_in_dma:descriptor_slave_writedata
signal mm_interconnect_0_jtagdebug_descriptor_slave_waitrequest : std_logic; -- jtagdebug:descriptor_slave_waitrequest -> mm_interconnect_0:jtagdebug_descriptor_slave_waitrequest
signal mm_interconnect_0_jtagdebug_descriptor_slave_byteenable : std_logic_vector(15 downto 0); -- mm_interconnect_0:jtagdebug_descriptor_slave_byteenable -> jtagdebug:descriptor_slave_byteenable
signal mm_interconnect_0_jtagdebug_descriptor_slave_write : std_logic; -- mm_interconnect_0:jtagdebug_descriptor_slave_write -> jtagdebug:descriptor_slave_write
signal mm_interconnect_0_jtagdebug_descriptor_slave_writedata : std_logic_vector(127 downto 0); -- mm_interconnect_0:jtagdebug_descriptor_slave_writedata -> jtagdebug:descriptor_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_pio_1_s1_chipselect : std_logic; -- mm_interconnect_0:pio_1_s1_chipselect -> pio_1:chipselect
signal mm_interconnect_0_pio_1_s1_readdata : std_logic_vector(31 downto 0); -- pio_1:readdata -> mm_interconnect_0:pio_1_s1_readdata
signal mm_interconnect_0_pio_1_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:pio_1_s1_address -> pio_1:address
signal mm_interconnect_0_pio_1_s1_write : std_logic; -- mm_interconnect_0:pio_1_s1_write -> mm_interconnect_0_pio_1_s1_write:in
signal mm_interconnect_0_pio_1_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_1_s1_writedata -> pio_1:writedata
signal mm_interconnect_0_spi_0_spi_control_port_chipselect : std_logic; -- mm_interconnect_0:spi_0_spi_control_port_chipselect -> spi_0:spi_select
signal mm_interconnect_0_spi_0_spi_control_port_readdata : std_logic_vector(15 downto 0); -- spi_0:data_to_cpu -> mm_interconnect_0:spi_0_spi_control_port_readdata
signal mm_interconnect_0_spi_0_spi_control_port_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:spi_0_spi_control_port_address -> spi_0:mem_addr
signal mm_interconnect_0_spi_0_spi_control_port_read : std_logic; -- mm_interconnect_0:spi_0_spi_control_port_read -> mm_interconnect_0_spi_0_spi_control_port_read:in
signal mm_interconnect_0_spi_0_spi_control_port_write : std_logic; -- mm_interconnect_0:spi_0_spi_control_port_write -> mm_interconnect_0_spi_0_spi_control_port_write:in
signal mm_interconnect_0_spi_0_spi_control_port_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:spi_0_spi_control_port_writedata -> spi_0:data_from_cpu
signal irq_mapper_receiver0_irq : std_logic; -- audio_out_dma:csr_irq_irq -> irq_mapper:receiver0_irq
signal irq_mapper_receiver1_irq : std_logic; -- audio_in_dma:csr_irq_irq -> irq_mapper:receiver1_irq
signal irq_mapper_receiver2_irq : std_logic; -- jtagdebug:csr_irq_irq -> irq_mapper:receiver2_irq
signal irq_mapper_receiver3_irq : std_logic; -- io_bridge_1:avs_irq -> irq_mapper:receiver3_irq
signal irq_mapper_receiver4_irq : std_logic; -- pio_0:irq -> irq_mapper:receiver4_irq
signal irq_mapper_receiver5_irq : std_logic; -- spi_0:irq -> irq_mapper:receiver5_irq
signal irq_mapper_receiver6_irq : std_logic; -- io_bridge_0:avs_irq -> irq_mapper:receiver6_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [avalon2mem_0:reset, io_bridge_0:reset, io_bridge_1:reset, irq_mapper:reset, jtag_0:reset, jtag_1:reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal sys_reset_reset_n_ports_inv : std_logic; -- sys_reset_reset_n:inv -> rst_controller:reset_in0
signal mm_interconnect_0_io_bridge_1_avalon_slave_0_inv : std_logic; -- io_bridge_1_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_1_avalon_slave_0_waitrequest
signal mm_interconnect_0_jtag_0_avalon_slave_0_inv : std_logic; -- jtag_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:jtag_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_jtag_1_avalon_slave_0_inv : std_logic; -- jtag_1_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:jtag_1_avalon_slave_0_waitrequest
signal mm_interconnect_0_io_bridge_0_avalon_slave_0_inv : std_logic; -- io_bridge_0_avalon_slave_0_waitrequest:inv -> mm_interconnect_0:io_bridge_0_avalon_slave_0_waitrequest
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_pio_1_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_1_s1_write:inv -> pio_1:write_n
signal mm_interconnect_0_spi_0_spi_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_spi_0_spi_control_port_read:inv -> spi_0:read_n
signal mm_interconnect_0_spi_0_spi_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_spi_0_spi_control_port_write:inv -> spi_0:write_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [audio_in_dma:reset_n_reset_n, audio_out_dma:reset_n_reset_n, jtagdebug:reset_n_reset_n, nios2_gen2_0:reset_n, pio_0:reset_n, pio_1:reset_n, spi_0:reset_n]
begin
audio_in_dma : component nios_tester_audio_in_dma
port map (
mm_write_address => audio_in_dma_mm_write_address, -- mm_write.address
mm_write_write => audio_in_dma_mm_write_write, -- .write
mm_write_byteenable => audio_in_dma_mm_write_byteenable, -- .byteenable
mm_write_writedata => audio_in_dma_mm_write_writedata, -- .writedata
mm_write_waitrequest => audio_in_dma_mm_write_waitrequest, -- .waitrequest
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_audio_in_dma_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_audio_in_dma_csr_write, -- .write
csr_byteenable => mm_interconnect_0_audio_in_dma_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_audio_in_dma_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_audio_in_dma_csr_read, -- .read
csr_address => mm_interconnect_0_audio_in_dma_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_audio_in_dma_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_audio_in_dma_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver1_irq, -- csr_irq.irq
st_sink_data => audio_in_data, -- st_sink.data
st_sink_valid => audio_in_valid, -- .valid
st_sink_ready => audio_in_ready -- .ready
);
audio_out_dma : component nios_tester_audio_out_dma
port map (
mm_read_address => audio_out_dma_mm_read_address, -- mm_read.address
mm_read_read => audio_out_dma_mm_read_read, -- .read
mm_read_byteenable => audio_out_dma_mm_read_byteenable, -- .byteenable
mm_read_readdata => audio_out_dma_mm_read_readdata, -- .readdata
mm_read_waitrequest => audio_out_dma_mm_read_waitrequest, -- .waitrequest
mm_read_readdatavalid => audio_out_dma_mm_read_readdatavalid, -- .readdatavalid
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_audio_out_dma_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_audio_out_dma_csr_write, -- .write
csr_byteenable => mm_interconnect_0_audio_out_dma_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_audio_out_dma_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_audio_out_dma_csr_read, -- .read
csr_address => mm_interconnect_0_audio_out_dma_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_audio_out_dma_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_audio_out_dma_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver0_irq, -- csr_irq.irq
st_source_data => audio_out_data, -- st_source.data
st_source_valid => audio_out_valid, -- .valid
st_source_ready => audio_out_ready -- .ready
);
avalon2mem_0 : component avalon_to_mem32_bridge
generic map (
g_tag => "01011011"
)
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_avalon2mem_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_avalon2mem_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_avalon2mem_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata, -- .writedata
avs_byteenable => mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable, -- .byteenable
avs_waitrequest => mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest, -- .waitrequest
avs_readdata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
mem_req_address => mem_mem_req_address, -- mem.mem_req_address
mem_req_byte_en => mem_mem_req_byte_en, -- .mem_req_byte_en
mem_req_read_writen => mem_mem_req_read_writen, -- .mem_req_read_writen
mem_req_request => mem_mem_req_request, -- .mem_req_request
mem_req_tag => mem_mem_req_tag, -- .mem_req_tag
mem_req_wdata => mem_mem_req_wdata, -- .mem_req_wdata
mem_resp_dack_tag => mem_mem_resp_dack_tag, -- .mem_resp_dack_tag
mem_resp_data => mem_mem_resp_data, -- .mem_resp_data
mem_resp_rack_tag => mem_mem_resp_rack_tag -- .mem_resp_rack_tag
);
io_bridge_0 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
io_ack => io_ack, -- io.ack
io_rdata => io_rdata, -- .rdata
io_read => io_read, -- .read
io_wdata => io_wdata, -- .wdata
io_write => io_write, -- .write
io_address => io_address, -- .address
io_irq => io_irq, -- .irq
avs_irq => irq_mapper_receiver6_irq -- irq.irq
);
io_bridge_1 : component avalon_to_io_bridge
port map (
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_io_bridge_1_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_io_bridge_1_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_io_bridge_1_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata, -- .writedata
avs_ready => io_bridge_1_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid, -- .readdatavalid
clock => sys_clock_clk, -- clock.clk
io_ack => io_u2p_ack, -- io.ack
io_rdata => io_u2p_rdata, -- .rdata
io_read => io_u2p_read, -- .read
io_wdata => io_u2p_wdata, -- .wdata
io_write => io_u2p_write, -- .write
io_address => io_u2p_address, -- .address
io_irq => io_u2p_irq, -- .irq
avs_irq => irq_mapper_receiver3_irq -- irq.irq
);
jtag_0 : component jtag_host
port map (
clock => sys_clock_clk, -- clock.clk
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_jtag_0_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_jtag_0_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_jtag_0_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_jtag_0_avalon_slave_0_writedata, -- .writedata
avs_ready => jtag_0_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_jtag_0_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_jtag_0_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_tck => jtag0_jtag_tck, -- jtag.jtag_tck
jtag_tms => jtag0_jtag_tms, -- .jtag_tms
jtag_tdi => jtag0_jtag_tdi, -- .jtag_tdi
jtag_tdo => jtag0_jtag_tdo -- .jtag_tdo
);
jtag_1 : component jtag_host
port map (
clock => sys_clock_clk, -- clock.clk
reset => rst_controller_reset_out_reset, -- reset.reset
avs_read => mm_interconnect_0_jtag_1_avalon_slave_0_read, -- avalon_slave_0.read
avs_write => mm_interconnect_0_jtag_1_avalon_slave_0_write, -- .write
avs_address => mm_interconnect_0_jtag_1_avalon_slave_0_address, -- .address
avs_writedata => mm_interconnect_0_jtag_1_avalon_slave_0_writedata, -- .writedata
avs_ready => jtag_1_avalon_slave_0_waitrequest, -- .waitrequest_n
avs_readdata => mm_interconnect_0_jtag_1_avalon_slave_0_readdata, -- .readdata
avs_readdatavalid => mm_interconnect_0_jtag_1_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_tck => jtag1_jtag_tck, -- jtag.jtag_tck
jtag_tms => jtag1_jtag_tms, -- .jtag_tms
jtag_tdi => jtag1_jtag_tdi, -- .jtag_tdi
jtag_tdo => jtag1_jtag_tdo -- .jtag_tdo
);
jtagdebug : component nios_tester_jtagdebug
port map (
mm_write_address => jtagdebug_mm_write_address, -- mm_write.address
mm_write_write => jtagdebug_mm_write_write, -- .write
mm_write_writedata => jtagdebug_mm_write_writedata, -- .writedata
mm_write_waitrequest => jtagdebug_mm_write_waitrequest, -- .waitrequest
clock_clk => sys_clock_clk, -- clock.clk
reset_n_reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n
csr_writedata => mm_interconnect_0_jtagdebug_csr_writedata, -- csr.writedata
csr_write => mm_interconnect_0_jtagdebug_csr_write, -- .write
csr_byteenable => mm_interconnect_0_jtagdebug_csr_byteenable, -- .byteenable
csr_readdata => mm_interconnect_0_jtagdebug_csr_readdata, -- .readdata
csr_read => mm_interconnect_0_jtagdebug_csr_read, -- .read
csr_address => mm_interconnect_0_jtagdebug_csr_address, -- .address
descriptor_slave_write => mm_interconnect_0_jtagdebug_descriptor_slave_write, -- descriptor_slave.write
descriptor_slave_waitrequest => mm_interconnect_0_jtagdebug_descriptor_slave_waitrequest, -- .waitrequest
descriptor_slave_writedata => mm_interconnect_0_jtagdebug_descriptor_slave_writedata, -- .writedata
descriptor_slave_byteenable => mm_interconnect_0_jtagdebug_descriptor_slave_byteenable, -- .byteenable
csr_irq_irq => irq_mapper_receiver2_irq, -- csr_irq.irq
st_sink_data => jtag_in_data, -- st_sink.data
st_sink_valid => jtag_in_valid, -- .valid
st_sink_ready => jtag_in_ready -- .ready
);
nios2_gen2_0 : component nios_tester_nios2_gen2_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component nios_tester_onchip_memory2_0
port map (
clk => sys_clock_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_reset_out_reset, -- reset1.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
freeze => '0' -- (terminated)
);
pio_0 : component nios_tester_pio_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
in_port => dummy_export, -- external_connection.export
irq => irq_mapper_receiver4_irq -- irq.irq
);
pio_1 : component nios_tester_pio_1
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_1_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_1_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_1_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_1_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_1_s1_readdata, -- .readdata
in_port => pio_in_port, -- external_connection.export
out_port => pio_out_port -- .export
);
spi_0 : component nios_tester_spi_0
port map (
clk => sys_clock_clk, -- clk.clk
reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
data_from_cpu => mm_interconnect_0_spi_0_spi_control_port_writedata, -- spi_control_port.writedata
data_to_cpu => mm_interconnect_0_spi_0_spi_control_port_readdata, -- .readdata
mem_addr => mm_interconnect_0_spi_0_spi_control_port_address, -- .address
read_n => mm_interconnect_0_spi_0_spi_control_port_read_ports_inv, -- .read_n
spi_select => mm_interconnect_0_spi_0_spi_control_port_chipselect, -- .chipselect
write_n => mm_interconnect_0_spi_0_spi_control_port_write_ports_inv, -- .write_n
irq => irq_mapper_receiver5_irq, -- irq.irq
MISO => spi_MISO, -- external.export
MOSI => spi_MOSI, -- .export
SCLK => spi_SCLK, -- .export
SS_n => spi_SS_n -- .export
);
mm_interconnect_0 : component nios_tester_mm_interconnect_0
port map (
clk_0_clk_clk => sys_clock_clk, -- clk_0_clk.clk
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
audio_in_dma_mm_write_address => audio_in_dma_mm_write_address, -- audio_in_dma_mm_write.address
audio_in_dma_mm_write_waitrequest => audio_in_dma_mm_write_waitrequest, -- .waitrequest
audio_in_dma_mm_write_byteenable => audio_in_dma_mm_write_byteenable, -- .byteenable
audio_in_dma_mm_write_write => audio_in_dma_mm_write_write, -- .write
audio_in_dma_mm_write_writedata => audio_in_dma_mm_write_writedata, -- .writedata
audio_out_dma_mm_read_address => audio_out_dma_mm_read_address, -- audio_out_dma_mm_read.address
audio_out_dma_mm_read_waitrequest => audio_out_dma_mm_read_waitrequest, -- .waitrequest
audio_out_dma_mm_read_byteenable => audio_out_dma_mm_read_byteenable, -- .byteenable
audio_out_dma_mm_read_read => audio_out_dma_mm_read_read, -- .read
audio_out_dma_mm_read_readdata => audio_out_dma_mm_read_readdata, -- .readdata
audio_out_dma_mm_read_readdatavalid => audio_out_dma_mm_read_readdatavalid, -- .readdatavalid
jtagdebug_mm_write_address => jtagdebug_mm_write_address, -- jtagdebug_mm_write.address
jtagdebug_mm_write_waitrequest => jtagdebug_mm_write_waitrequest, -- .waitrequest
jtagdebug_mm_write_write => jtagdebug_mm_write_write, -- .write
jtagdebug_mm_write_writedata => jtagdebug_mm_write_writedata, -- .writedata
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
audio_in_dma_csr_address => mm_interconnect_0_audio_in_dma_csr_address, -- audio_in_dma_csr.address
audio_in_dma_csr_write => mm_interconnect_0_audio_in_dma_csr_write, -- .write
audio_in_dma_csr_read => mm_interconnect_0_audio_in_dma_csr_read, -- .read
audio_in_dma_csr_readdata => mm_interconnect_0_audio_in_dma_csr_readdata, -- .readdata
audio_in_dma_csr_writedata => mm_interconnect_0_audio_in_dma_csr_writedata, -- .writedata
audio_in_dma_csr_byteenable => mm_interconnect_0_audio_in_dma_csr_byteenable, -- .byteenable
audio_in_dma_descriptor_slave_write => mm_interconnect_0_audio_in_dma_descriptor_slave_write, -- audio_in_dma_descriptor_slave.write
audio_in_dma_descriptor_slave_writedata => mm_interconnect_0_audio_in_dma_descriptor_slave_writedata, -- .writedata
audio_in_dma_descriptor_slave_byteenable => mm_interconnect_0_audio_in_dma_descriptor_slave_byteenable, -- .byteenable
audio_in_dma_descriptor_slave_waitrequest => mm_interconnect_0_audio_in_dma_descriptor_slave_waitrequest, -- .waitrequest
audio_out_dma_csr_address => mm_interconnect_0_audio_out_dma_csr_address, -- audio_out_dma_csr.address
audio_out_dma_csr_write => mm_interconnect_0_audio_out_dma_csr_write, -- .write
audio_out_dma_csr_read => mm_interconnect_0_audio_out_dma_csr_read, -- .read
audio_out_dma_csr_readdata => mm_interconnect_0_audio_out_dma_csr_readdata, -- .readdata
audio_out_dma_csr_writedata => mm_interconnect_0_audio_out_dma_csr_writedata, -- .writedata
audio_out_dma_csr_byteenable => mm_interconnect_0_audio_out_dma_csr_byteenable, -- .byteenable
audio_out_dma_descriptor_slave_write => mm_interconnect_0_audio_out_dma_descriptor_slave_write, -- audio_out_dma_descriptor_slave.write
audio_out_dma_descriptor_slave_writedata => mm_interconnect_0_audio_out_dma_descriptor_slave_writedata, -- .writedata
audio_out_dma_descriptor_slave_byteenable => mm_interconnect_0_audio_out_dma_descriptor_slave_byteenable, -- .byteenable
audio_out_dma_descriptor_slave_waitrequest => mm_interconnect_0_audio_out_dma_descriptor_slave_waitrequest, -- .waitrequest
avalon2mem_0_avalon_slave_0_address => mm_interconnect_0_avalon2mem_0_avalon_slave_0_address, -- avalon2mem_0_avalon_slave_0.address
avalon2mem_0_avalon_slave_0_write => mm_interconnect_0_avalon2mem_0_avalon_slave_0_write, -- .write
avalon2mem_0_avalon_slave_0_read => mm_interconnect_0_avalon2mem_0_avalon_slave_0_read, -- .read
avalon2mem_0_avalon_slave_0_readdata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdata, -- .readdata
avalon2mem_0_avalon_slave_0_writedata => mm_interconnect_0_avalon2mem_0_avalon_slave_0_writedata, -- .writedata
avalon2mem_0_avalon_slave_0_byteenable => mm_interconnect_0_avalon2mem_0_avalon_slave_0_byteenable, -- .byteenable
avalon2mem_0_avalon_slave_0_readdatavalid => mm_interconnect_0_avalon2mem_0_avalon_slave_0_readdatavalid, -- .readdatavalid
avalon2mem_0_avalon_slave_0_waitrequest => mm_interconnect_0_avalon2mem_0_avalon_slave_0_waitrequest, -- .waitrequest
io_bridge_0_avalon_slave_0_address => mm_interconnect_0_io_bridge_0_avalon_slave_0_address, -- io_bridge_0_avalon_slave_0.address
io_bridge_0_avalon_slave_0_write => mm_interconnect_0_io_bridge_0_avalon_slave_0_write, -- .write
io_bridge_0_avalon_slave_0_read => mm_interconnect_0_io_bridge_0_avalon_slave_0_read, -- .read
io_bridge_0_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdata, -- .readdata
io_bridge_0_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_0_avalon_slave_0_writedata, -- .writedata
io_bridge_0_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_0_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_0_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_0_avalon_slave_0_inv, -- .waitrequest
io_bridge_1_avalon_slave_0_address => mm_interconnect_0_io_bridge_1_avalon_slave_0_address, -- io_bridge_1_avalon_slave_0.address
io_bridge_1_avalon_slave_0_write => mm_interconnect_0_io_bridge_1_avalon_slave_0_write, -- .write
io_bridge_1_avalon_slave_0_read => mm_interconnect_0_io_bridge_1_avalon_slave_0_read, -- .read
io_bridge_1_avalon_slave_0_readdata => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdata, -- .readdata
io_bridge_1_avalon_slave_0_writedata => mm_interconnect_0_io_bridge_1_avalon_slave_0_writedata, -- .writedata
io_bridge_1_avalon_slave_0_readdatavalid => mm_interconnect_0_io_bridge_1_avalon_slave_0_readdatavalid, -- .readdatavalid
io_bridge_1_avalon_slave_0_waitrequest => mm_interconnect_0_io_bridge_1_avalon_slave_0_inv, -- .waitrequest
jtag_0_avalon_slave_0_address => mm_interconnect_0_jtag_0_avalon_slave_0_address, -- jtag_0_avalon_slave_0.address
jtag_0_avalon_slave_0_write => mm_interconnect_0_jtag_0_avalon_slave_0_write, -- .write
jtag_0_avalon_slave_0_read => mm_interconnect_0_jtag_0_avalon_slave_0_read, -- .read
jtag_0_avalon_slave_0_readdata => mm_interconnect_0_jtag_0_avalon_slave_0_readdata, -- .readdata
jtag_0_avalon_slave_0_writedata => mm_interconnect_0_jtag_0_avalon_slave_0_writedata, -- .writedata
jtag_0_avalon_slave_0_readdatavalid => mm_interconnect_0_jtag_0_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_0_avalon_slave_0_waitrequest => mm_interconnect_0_jtag_0_avalon_slave_0_inv, -- .waitrequest
jtag_1_avalon_slave_0_address => mm_interconnect_0_jtag_1_avalon_slave_0_address, -- jtag_1_avalon_slave_0.address
jtag_1_avalon_slave_0_write => mm_interconnect_0_jtag_1_avalon_slave_0_write, -- .write
jtag_1_avalon_slave_0_read => mm_interconnect_0_jtag_1_avalon_slave_0_read, -- .read
jtag_1_avalon_slave_0_readdata => mm_interconnect_0_jtag_1_avalon_slave_0_readdata, -- .readdata
jtag_1_avalon_slave_0_writedata => mm_interconnect_0_jtag_1_avalon_slave_0_writedata, -- .writedata
jtag_1_avalon_slave_0_readdatavalid => mm_interconnect_0_jtag_1_avalon_slave_0_readdatavalid, -- .readdatavalid
jtag_1_avalon_slave_0_waitrequest => mm_interconnect_0_jtag_1_avalon_slave_0_inv, -- .waitrequest
jtagdebug_csr_address => mm_interconnect_0_jtagdebug_csr_address, -- jtagdebug_csr.address
jtagdebug_csr_write => mm_interconnect_0_jtagdebug_csr_write, -- .write
jtagdebug_csr_read => mm_interconnect_0_jtagdebug_csr_read, -- .read
jtagdebug_csr_readdata => mm_interconnect_0_jtagdebug_csr_readdata, -- .readdata
jtagdebug_csr_writedata => mm_interconnect_0_jtagdebug_csr_writedata, -- .writedata
jtagdebug_csr_byteenable => mm_interconnect_0_jtagdebug_csr_byteenable, -- .byteenable
jtagdebug_descriptor_slave_write => mm_interconnect_0_jtagdebug_descriptor_slave_write, -- jtagdebug_descriptor_slave.write
jtagdebug_descriptor_slave_writedata => mm_interconnect_0_jtagdebug_descriptor_slave_writedata, -- .writedata
jtagdebug_descriptor_slave_byteenable => mm_interconnect_0_jtagdebug_descriptor_slave_byteenable, -- .byteenable
jtagdebug_descriptor_slave_waitrequest => mm_interconnect_0_jtagdebug_descriptor_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
pio_1_s1_address => mm_interconnect_0_pio_1_s1_address, -- pio_1_s1.address
pio_1_s1_write => mm_interconnect_0_pio_1_s1_write, -- .write
pio_1_s1_readdata => mm_interconnect_0_pio_1_s1_readdata, -- .readdata
pio_1_s1_writedata => mm_interconnect_0_pio_1_s1_writedata, -- .writedata
pio_1_s1_chipselect => mm_interconnect_0_pio_1_s1_chipselect, -- .chipselect
spi_0_spi_control_port_address => mm_interconnect_0_spi_0_spi_control_port_address, -- spi_0_spi_control_port.address
spi_0_spi_control_port_write => mm_interconnect_0_spi_0_spi_control_port_write, -- .write
spi_0_spi_control_port_read => mm_interconnect_0_spi_0_spi_control_port_read, -- .read
spi_0_spi_control_port_readdata => mm_interconnect_0_spi_0_spi_control_port_readdata, -- .readdata
spi_0_spi_control_port_writedata => mm_interconnect_0_spi_0_spi_control_port_writedata, -- .writedata
spi_0_spi_control_port_chipselect => mm_interconnect_0_spi_0_spi_control_port_chipselect -- .chipselect
);
irq_mapper : component nios_tester_irq_mapper
port map (
clk => sys_clock_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
receiver4_irq => irq_mapper_receiver4_irq, -- receiver4.irq
receiver5_irq => irq_mapper_receiver5_irq, -- receiver5.irq
receiver6_irq => irq_mapper_receiver6_irq, -- receiver6.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => sys_reset_reset_n_ports_inv, -- reset_in0.reset
clk => sys_clock_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
sys_reset_reset_n_ports_inv <= not sys_reset_reset_n;
mm_interconnect_0_io_bridge_1_avalon_slave_0_inv <= not io_bridge_1_avalon_slave_0_waitrequest;
mm_interconnect_0_jtag_0_avalon_slave_0_inv <= not jtag_0_avalon_slave_0_waitrequest;
mm_interconnect_0_jtag_1_avalon_slave_0_inv <= not jtag_1_avalon_slave_0_waitrequest;
mm_interconnect_0_io_bridge_0_avalon_slave_0_inv <= not io_bridge_0_avalon_slave_0_waitrequest;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_pio_1_s1_write_ports_inv <= not mm_interconnect_0_pio_1_s1_write;
mm_interconnect_0_spi_0_spi_control_port_read_ports_inv <= not mm_interconnect_0_spi_0_spi_control_port_read;
mm_interconnect_0_spi_0_spi_control_port_write_ports_inv <= not mm_interconnect_0_spi_0_spi_control_port_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
end architecture rtl; -- of nios_tester
|
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`protect end_protected
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
library tech;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of cache_core_1rw is
constant assoc : natural := 2**log2_assoc;
type comb_type is record
tag_en : std_ulogic;
tag_we : std_ulogic;
tag_banken : std_ulogic_vector(assoc-1 downto 0);
tag_addr : std_ulogic_vector(index_bits-1 downto 0);
tag_wdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
tag_rdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits-1 downto 0);
data_en : std_ulogic;
data_we : std_ulogic;
data_banken : std_ulogic_vector(assoc-1 downto 0);
data_addr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_wdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
data_rdata : std_ulogic_vector2(assoc-1 downto 0, word_bits-1 downto 0);
end record;
signal c : comb_type;
begin
c.tag_en <= en and tagen;
c.tag_we <= we;
c.tag_banken <= way;
c.tag_addr <= index;
c.data_en <= en and dataen;
c.data_we <= we;
c.data_addr <= index & offset;
c.data_banken <= way;
way_loop : for n in assoc-1 downto 0 generate
tag_bit_loop : for m in tag_bits-1 downto 0 generate
c.tag_wdata(n, m) <= wtag(m);
end generate;
data_bit_loop : for m in word_bits-1 downto 0 generate
c.data_wdata(n, m) <= wdata(m);
end generate;
end generate;
rtag <= c.tag_rdata;
rdata <= c.data_rdata;
tag_sram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => index_bits,
word_bits => tag_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
en => c.tag_en,
we => c.tag_we,
banken => c.tag_banken,
addr => c.tag_addr,
wdata => c.tag_wdata,
rdata => c.tag_rdata
);
data_sram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => index_bits + offset_bits,
word_bits => word_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
en => c.data_en,
we => c.data_we,
banken => c.data_banken,
addr => c.data_addr,
wdata => c.data_wdata,
rdata => c.data_rdata
);
end;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0;
USE lmb_v10_v3_0.lmb_v10;
ENTITY design_1_ilmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END design_1_ilmb_v10_0;
ARCHITECTURE design_1_ilmb_v10_0_arch OF design_1_ilmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_v10_0_arch : ARCHITECTURE IS "design_1_ilmb_v10_0,lmb_v10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "design_1_ilmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END design_1_ilmb_v10_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY lmb_v10_v3_0;
USE lmb_v10_v3_0.lmb_v10;
ENTITY design_1_ilmb_v10_0 IS
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END design_1_ilmb_v10_0;
ARCHITECTURE design_1_ilmb_v10_0_arch OF design_1_ilmb_v10_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "yes";
COMPONENT lmb_v10 IS
GENERIC (
C_LMB_NUM_SLAVES : INTEGER;
C_LMB_DWIDTH : INTEGER;
C_LMB_AWIDTH : INTEGER;
C_EXT_RESET_HIGH : INTEGER
);
PORT (
LMB_Clk : IN STD_LOGIC;
SYS_Rst : IN STD_LOGIC;
LMB_Rst : OUT STD_LOGIC;
M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
M_ReadStrobe : IN STD_LOGIC;
M_WriteStrobe : IN STD_LOGIC;
M_AddrStrobe : IN STD_LOGIC;
M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_ReadStrobe : OUT STD_LOGIC;
LMB_WriteStrobe : OUT STD_LOGIC;
LMB_AddrStrobe : OUT STD_LOGIC;
LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
LMB_Ready : OUT STD_LOGIC;
LMB_Wait : OUT STD_LOGIC;
LMB_UE : OUT STD_LOGIC;
LMB_CE : OUT STD_LOGIC;
LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
);
END COMPONENT lmb_v10;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_ilmb_v10_0_arch : ARCHITECTURE IS "design_1_ilmb_v10_0,lmb_v10,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_ilmb_v10_0_arch: ARCHITECTURE IS "design_1_ilmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
BEGIN
U0 : lmb_v10
GENERIC MAP (
C_LMB_NUM_SLAVES => 1,
C_LMB_DWIDTH => 32,
C_LMB_AWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
PORT MAP (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
END design_1_ilmb_v10_0_arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:58:40 10/03/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/Tbfirstpart.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: firstrpart
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Tbfirstpart IS
END Tbfirstpart;
ARCHITECTURE behavior OF Tbfirstpart IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT firstrpart
PORT(
Resetext : IN std_logic;
Clkinext : IN std_logic;
Adressext : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Resetext : std_logic := '0';
signal Clkinext : std_logic := '0';
--Outputs
signal Adressext : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clkinext_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: firstrpart PORT MAP (
Resetext => Resetext,
Clkinext => Clkinext,
Adressext => Adressext
);
-- Clock process definitions
Clkinext_process :process
begin
Clkinext <= '0';
wait for Clkinext_period/2;
Clkinext <= '1';
wait for Clkinext_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Resetext <= '0';
wait for 100 ns;
Resetext <= '1';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
Resetext <= '0';
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_cpu_2_crossbar_wrap_pack is
function clogb2(bit_depth : in integer ) return integer;
component plasoc_cpu_2_crossbar_wrap is
generic
(
axi_address_width : integer := 32;
axi_data_width : integer := 32;
axi_slave_id_width : integer := 0;
axi_master_amount : integer := 5;
axi_slave_amount : integer := 1;
axi_master_base_address : std_logic_vector := X"f0030000f0020000f0010000f000000000000000";
axi_master_high_address : std_logic_vector := X"f003fffff002fffff001fffff000ffffefffffff"
);
port
(
cpu_s_axi_awid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_awlen : in std_logic_vector(7 downto 0);
cpu_s_axi_awsize : in std_logic_vector(2 downto 0);
cpu_s_axi_awburst : in std_logic_vector(1 downto 0);
cpu_s_axi_awlock : in std_logic;
cpu_s_axi_awcache : in std_logic_vector(3 downto 0);
cpu_s_axi_awprot : in std_logic_vector(2 downto 0);
cpu_s_axi_awqos : in std_logic_vector(3 downto 0);
cpu_s_axi_awregion : in std_logic_vector(3 downto 0);
cpu_s_axi_awvalid : in std_logic;
cpu_s_axi_awready : out std_logic;
cpu_s_axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
cpu_s_axi_wlast : in std_logic;
cpu_s_axi_wvalid : in std_logic;
cpu_s_axi_wready : out std_logic;
cpu_s_axi_bid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_bresp : out std_logic_vector(1 downto 0);
cpu_s_axi_bvalid : out std_logic;
cpu_s_axi_bready : in std_logic;
cpu_s_axi_arid : in std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
cpu_s_axi_arlen : in std_logic_vector(7 downto 0);
cpu_s_axi_arsize : in std_logic_vector(2 downto 0);
cpu_s_axi_arburst : in std_logic_vector(1 downto 0);
cpu_s_axi_arlock : in std_logic;
cpu_s_axi_arcache : in std_logic_vector(3 downto 0);
cpu_s_axi_arprot : in std_logic_vector(2 downto 0);
cpu_s_axi_arqos : in std_logic_vector(3 downto 0);
cpu_s_axi_arregion : in std_logic_vector(3 downto 0);
cpu_s_axi_arvalid : in std_logic;
cpu_s_axi_arready : out std_logic;
cpu_s_axi_rid : out std_logic_vector(axi_slave_id_width-1 downto 0);
cpu_s_axi_rdata : out std_logic_vector(axi_data_width-1 downto 0);
cpu_s_axi_rresp : out std_logic_vector(1 downto 0);
cpu_s_axi_rlast : out std_logic;
cpu_s_axi_rvalid : out std_logic;
cpu_s_axi_rready : in std_logic;
ip_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_awlen : out std_logic_vector(7 downto 0);
ip_m_axi_awsize : out std_logic_vector(2 downto 0);
ip_m_axi_awburst : out std_logic_vector(1 downto 0);
ip_m_axi_awlock : out std_logic;
ip_m_axi_awcache : out std_logic_vector(3 downto 0);
ip_m_axi_awprot : out std_logic_vector(2 downto 0);
ip_m_axi_awqos : out std_logic_vector(3 downto 0);
ip_m_axi_awregion : out std_logic_vector(3 downto 0);
ip_m_axi_awvalid : out std_logic;
ip_m_axi_awready : in std_logic;
ip_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
ip_m_axi_wlast : out std_logic;
ip_m_axi_wvalid : out std_logic;
ip_m_axi_wready : in std_logic;
ip_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_bresp : in std_logic_vector(1 downto 0);
ip_m_axi_bvalid : in std_logic;
ip_m_axi_bready : out std_logic;
ip_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
ip_m_axi_arlen : out std_logic_vector(7 downto 0);
ip_m_axi_arsize : out std_logic_vector(2 downto 0);
ip_m_axi_arburst : out std_logic_vector(1 downto 0);
ip_m_axi_arlock : out std_logic;
ip_m_axi_arcache : out std_logic_vector(3 downto 0);
ip_m_axi_arprot : out std_logic_vector(2 downto 0);
ip_m_axi_arqos : out std_logic_vector(3 downto 0);
ip_m_axi_arregion : out std_logic_vector(3 downto 0);
ip_m_axi_arvalid : out std_logic;
ip_m_axi_arready : in std_logic;
ip_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
ip_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
ip_m_axi_rresp : in std_logic_vector(1 downto 0);
ip_m_axi_rlast : in std_logic;
ip_m_axi_rvalid : in std_logic;
ip_m_axi_rready : out std_logic;
cpuid_gpio_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_awlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_awsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_awlock : out std_logic;
cpuid_gpio_m_axi_awcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_awqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_awvalid : out std_logic;
cpuid_gpio_m_axi_awready : in std_logic;
cpuid_gpio_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
cpuid_gpio_m_axi_wlast : out std_logic;
cpuid_gpio_m_axi_wvalid : out std_logic;
cpuid_gpio_m_axi_wready : in std_logic;
cpuid_gpio_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_bresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_bvalid : in std_logic;
cpuid_gpio_m_axi_bready : out std_logic;
cpuid_gpio_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
cpuid_gpio_m_axi_arlen : out std_logic_vector(7 downto 0);
cpuid_gpio_m_axi_arsize : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arburst : out std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_arlock : out std_logic;
cpuid_gpio_m_axi_arcache : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arprot : out std_logic_vector(2 downto 0);
cpuid_gpio_m_axi_arqos : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arregion : out std_logic_vector(3 downto 0);
cpuid_gpio_m_axi_arvalid : out std_logic;
cpuid_gpio_m_axi_arready : in std_logic;
cpuid_gpio_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
cpuid_gpio_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
cpuid_gpio_m_axi_rresp : in std_logic_vector(1 downto 0);
cpuid_gpio_m_axi_rlast : in std_logic;
cpuid_gpio_m_axi_rvalid : in std_logic;
cpuid_gpio_m_axi_rready : out std_logic;
int_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_awlen : out std_logic_vector(7 downto 0);
int_m_axi_awsize : out std_logic_vector(2 downto 0);
int_m_axi_awburst : out std_logic_vector(1 downto 0);
int_m_axi_awlock : out std_logic;
int_m_axi_awcache : out std_logic_vector(3 downto 0);
int_m_axi_awprot : out std_logic_vector(2 downto 0);
int_m_axi_awqos : out std_logic_vector(3 downto 0);
int_m_axi_awregion : out std_logic_vector(3 downto 0);
int_m_axi_awvalid : out std_logic;
int_m_axi_awready : in std_logic;
int_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
int_m_axi_wlast : out std_logic;
int_m_axi_wvalid : out std_logic;
int_m_axi_wready : in std_logic;
int_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_bresp : in std_logic_vector(1 downto 0);
int_m_axi_bvalid : in std_logic;
int_m_axi_bready : out std_logic;
int_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
int_m_axi_arlen : out std_logic_vector(7 downto 0);
int_m_axi_arsize : out std_logic_vector(2 downto 0);
int_m_axi_arburst : out std_logic_vector(1 downto 0);
int_m_axi_arlock : out std_logic;
int_m_axi_arcache : out std_logic_vector(3 downto 0);
int_m_axi_arprot : out std_logic_vector(2 downto 0);
int_m_axi_arqos : out std_logic_vector(3 downto 0);
int_m_axi_arregion : out std_logic_vector(3 downto 0);
int_m_axi_arvalid : out std_logic;
int_m_axi_arready : in std_logic;
int_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
int_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
int_m_axi_rresp : in std_logic_vector(1 downto 0);
int_m_axi_rlast : in std_logic;
int_m_axi_rvalid : in std_logic;
int_m_axi_rready : out std_logic;
signal_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_awlen : out std_logic_vector(7 downto 0);
signal_m_axi_awsize : out std_logic_vector(2 downto 0);
signal_m_axi_awburst : out std_logic_vector(1 downto 0);
signal_m_axi_awlock : out std_logic;
signal_m_axi_awcache : out std_logic_vector(3 downto 0);
signal_m_axi_awprot : out std_logic_vector(2 downto 0);
signal_m_axi_awqos : out std_logic_vector(3 downto 0);
signal_m_axi_awregion : out std_logic_vector(3 downto 0);
signal_m_axi_awvalid : out std_logic;
signal_m_axi_awready : in std_logic;
signal_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
signal_m_axi_wlast : out std_logic;
signal_m_axi_wvalid : out std_logic;
signal_m_axi_wready : in std_logic;
signal_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_bresp : in std_logic_vector(1 downto 0);
signal_m_axi_bvalid : in std_logic;
signal_m_axi_bready : out std_logic;
signal_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
signal_m_axi_arlen : out std_logic_vector(7 downto 0);
signal_m_axi_arsize : out std_logic_vector(2 downto 0);
signal_m_axi_arburst : out std_logic_vector(1 downto 0);
signal_m_axi_arlock : out std_logic;
signal_m_axi_arcache : out std_logic_vector(3 downto 0);
signal_m_axi_arprot : out std_logic_vector(2 downto 0);
signal_m_axi_arqos : out std_logic_vector(3 downto 0);
signal_m_axi_arregion : out std_logic_vector(3 downto 0);
signal_m_axi_arvalid : out std_logic;
signal_m_axi_arready : in std_logic;
signal_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
signal_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
signal_m_axi_rresp : in std_logic_vector(1 downto 0);
signal_m_axi_rlast : in std_logic;
signal_m_axi_rvalid : in std_logic;
signal_m_axi_rready : out std_logic;
timer_m_axi_awid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_awaddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_awlen : out std_logic_vector(7 downto 0);
timer_m_axi_awsize : out std_logic_vector(2 downto 0);
timer_m_axi_awburst : out std_logic_vector(1 downto 0);
timer_m_axi_awlock : out std_logic;
timer_m_axi_awcache : out std_logic_vector(3 downto 0);
timer_m_axi_awprot : out std_logic_vector(2 downto 0);
timer_m_axi_awqos : out std_logic_vector(3 downto 0);
timer_m_axi_awregion : out std_logic_vector(3 downto 0);
timer_m_axi_awvalid : out std_logic;
timer_m_axi_awready : in std_logic;
timer_m_axi_wdata : out std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_wstrb : out std_logic_vector(axi_data_width/8-1 downto 0);
timer_m_axi_wlast : out std_logic;
timer_m_axi_wvalid : out std_logic;
timer_m_axi_wready : in std_logic;
timer_m_axi_bid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_bresp : in std_logic_vector(1 downto 0);
timer_m_axi_bvalid : in std_logic;
timer_m_axi_bready : out std_logic;
timer_m_axi_arid : out std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_araddr : out std_logic_vector(axi_address_width-1 downto 0);
timer_m_axi_arlen : out std_logic_vector(7 downto 0);
timer_m_axi_arsize : out std_logic_vector(2 downto 0);
timer_m_axi_arburst : out std_logic_vector(1 downto 0);
timer_m_axi_arlock : out std_logic;
timer_m_axi_arcache : out std_logic_vector(3 downto 0);
timer_m_axi_arprot : out std_logic_vector(2 downto 0);
timer_m_axi_arqos : out std_logic_vector(3 downto 0);
timer_m_axi_arregion : out std_logic_vector(3 downto 0);
timer_m_axi_arvalid : out std_logic;
timer_m_axi_arready : in std_logic;
timer_m_axi_rid : in std_logic_vector((clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
timer_m_axi_rdata : in std_logic_vector(axi_data_width-1 downto 0);
timer_m_axi_rresp : in std_logic_vector(1 downto 0);
timer_m_axi_rlast : in std_logic;
timer_m_axi_rvalid : in std_logic;
timer_m_axi_rready : out std_logic;
aclk : in std_logic;
aresetn : in std_logic
);
end component;
end;
package body plasoc_cpu_2_crossbar_wrap_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
entity FIFO is
end entity;
entity --Comment
--Comment
--Comment
FIFO is
end entity
;
|
entity FIFO is
end entity;
entity --Comment
--Comment
--Comment
FIFO is
end entity
;
|
-- NEED RESULT: ARCH00182.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00182: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00182
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00182
-- PKG00182/BODY
-- ENT00182(ARCH00182)
-- ENT00182_Test_Bench(ARCH00182_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00182 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00182 ;
--
package body PKG00182 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00182 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00182.all ;
entity ENT00182 is
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00182 ;
--
architecture ARCH00182 of ENT00182 is
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00182" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00182 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00182.all ;
entity ENT00182_Test_Bench is
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
end ENT00182_Test_Bench ;
--
architecture ARCH00182_Test_Bench of ENT00182_Test_Bench is
begin
L1:
block
component UUT
port (
s_r_st_arr1_vector : inout r_st_arr1_vector
; s_r_st_arr2_vector : inout r_st_arr2_vector
; s_r_st_arr3_vector : inout r_st_arr3_vector
; s_r_st_rec1_vector : inout r_st_rec1_vector
; s_r_st_rec2_vector : inout r_st_rec2_vector
; s_r_st_rec3_vector : inout r_st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00182 ( ARCH00182 ) ;
begin
CIS1 : UUT
port map (
s_r_st_arr1_vector
, s_r_st_arr2_vector
, s_r_st_arr3_vector
, s_r_st_rec1_vector
, s_r_st_rec2_vector
, s_r_st_rec3_vector
) ;
end block L1 ;
end ARCH00182_Test_Bench ;
|
-- $Id: tb_basys3_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_basys3_core - sim
-- Description: Test bench for basys3 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any basys3 target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4; ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_basys3_core is
port (
I_SWI : out slv16; -- b3 switches
I_BTN : out slv5 -- b3 buttons
);
end tb_basys3_core;
architecture sim of tb_basys3_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT tx_buf_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library work;
use work.common_pkg.all;
use work.common_data_types_pkg.all;
use work.counter_pkg.all;
use work.permutation_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity perm_sp_core is
generic(
dimensions : positive;
p_dimensions : positive;
serial_dim : natural;
parallel_dim : natural;
left_ps_latency : natural;
right_ps_latency : natural;
input_high : natural;
input_low : natural
);
port(
clk : in std_ulogic;
start : in std_ulogic;
input : in sulv_v;
finish : out std_ulogic;
output : out sulv_v(input_high downto input_low)
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture perm_sp_core_1 of perm_sp_core is
--parallel dimensions
constant P : natural := p_dimensions;
--serial dimensions
constant S : natural := dimensions - P;
constant LATENCY : positive := integer((2.0**serial_dim)/(2.0**P));
--latencies after removing delays whenever there are 2 consecutive sp permutations
constant LATENCY_0 : natural := LATENCY - minimum(right_ps_latency, LATENCY);
constant LATENCY_1 : natural := LATENCY - minimum(left_ps_latency, LATENCY);
constant common_LATENCY : natural := LATENCY_0;
signal count_is_not_zero : std_ulogic;
signal counter_out : std_ulogic;
signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt,
0, --COUNTER_WIDTH_dep,
true, --TARGET_MODE,
(2 ** S)- 1, --TARGET_dep,
true, --TARGET_WITH_COUNT_opt = t_true,
false, --USE_SET,
1) - 1 --SET_TO_dep)
downto 0); --only the serial indexes (N downto P) mapped to downto 0
signal control : std_ulogic;
signal start_delayed : std_ulogic_vector(0 to common_LATENCY);
/*================================================================================================*/
/*================================================================================================*/
begin
count_is_not_zero <= '1' when to_integer(unsigned(count)) /= 0 else
'0';
counter:
entity work.counter
generic map(
UNSIGNED_2COMP_opt => true,
OVERFLOW_BEHAVIOR_opt => t_wrap,
--COUNT_MODE_opt => t_up,
--COUNTER_WIDTH_dep => ,
TARGET_MODE => true,
TARGET_dep => (2 ** S)- 1,
TARGET_WITH_COUNT_opt => t_true,
TARGET_BLOCKING_opt => t_false,
USE_SET => false,
--SET_TO_dep => ,
USE_RESET => true,
--SET_RESET_PRIORITY_opt => ,
USE_LOAD => false
)
port map(
clk => clk,
enable => count_is_not_zero or start_delayed(0),
--set => ,
reset => counter_out,
--load => ,
--count_mode_signal => ,
--value_to_load => ,
count => count,
count_is_TARGET(1) => counter_out
);
control <= count(serial_dim - P);
generate_serial_parallel_permutation:
for i in 1 to 2**(P-1) generate
constant index0 : natural := calculate_indexes(integer(i-1), P, parallel_dim, 0);
constant index1 : natural := calculate_indexes(integer(i-1), P, parallel_dim, 1);
signal in0, in1 : std_ulogic_vector(input(input'left)'range);
signal inter0 : sulv_v(0 to LATENCY_0-1)(input(input'left)'range);
signal inter1 : sulv_v(0 to LATENCY_1-1)(input(input'left)'range);
begin
in0 <= input(index0);
in1 <= input(index1);
more_than_one_register_in_0:
if LATENCY_0 > 0 generate
begin
process (clk) is
begin
if rising_edge(clk) then
if LATENCY_1 > 0 then
inter0(0) <= in0 when control='0' else
inter1(LATENCY_1 - 1);
inter1(0) <= in1;
if LATENCY_1 > 1 then
inter1(1 to LATENCY_1 - 1) <= inter1(0 to LATENCY_1 - 2);
end if;
end if;
if LATENCY_0 > 1 then
inter0(1 to LATENCY_0 - 1) <= inter0(0 to LATENCY_0 - 2);
end if;
end if;
end process;
output(index0) <= inter0(LATENCY_0 - 1);
latency_1_is_not_zero:
if LATENCY_1 > 0 generate
begin
output(index1) <= inter1(LATENCY_1 - 1) when control = '0' else
in0;
end;
else generate
begin
output(index1) <= in1 when control='0' else
in0;
end;
end generate;
end;
else generate
begin
more_than_one_register_in_1:
if LATENCY_1 > 0 generate
begin
process (clk) is
begin
if rising_edge(clk) then
inter1(0) <= in1;
inter1(1 to LATENCY_1 - 1) <= inter1(0 to LATENCY_1 - 2);
end if;
end process;
output(index1) <= inter1(LATENCY_1 - 1) when control = '0' else
in0;
output(index0) <= in0 when control='0' else
inter1(LATENCY_1 - 1);
end;
else generate
begin
output(index1) <= in1 when control='0' else
in0;
output(index0) <= in0 when control='0' else
in1;
end;
end generate;
end;
end generate;
end;
end generate;
finish <= start_delayed(common_LATENCY);
start_delayed(0) <= start;
process (clk) is
begin
if rising_edge(clk) then
if common_LATENCY > 0 then
start_delayed(1 to common_LATENCY) <= start_delayed(0 to common_LATENCY-1);
end if;
end if;
end process;
end architecture; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:38:29 12/18/2014
-- Design Name:
-- Module Name: Trigger_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Trigger_generator is
Port ( clk : in STD_LOGIC;
Trigger : out STD_LOGIC);
end Trigger_generator;
architecture Behavioral of Trigger_generator is
component Counter is
generic(n: POSITIVE := 10);
Port(clk: in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
Counter_output : out STD_LOGIC_VECTOR(n-1 downto 0));
end component;
signal resetCounter : STD_LOGIC;
signal outputCounter : STD_LOGIC_VECTOR(23 downto 0);
begin
trigg: Counter generic map (24) port map(clk,'1',resetCounter,outputCounter);
process(clk)
constant ms250 : STD_LOGIC_VECTOR(23 downto 0) := "101111101011110000100000";
constant ms250And100us: STD_LOGIC_VECTOR(23 downto 0):="101111101100111110101000";
begin
if(outputCounter > ms250 and outputCounter < ms250And100us) then
trigger <= '1';
else
trigger <='0';
end if;
if(outputCounter = ms250And100us or outputCounter = "XXXXXXXXXXXXXXXXXXXXXXXX") then
resetCounter <= '0';
else
resetCounter <='1';
end if;
end process;
end Behavioral;
|
-- NEED RESULT: ARCH00550: Constant declarations - composite globally static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00550
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00550)
-- ENT00550_Test_Bench(ARCH00550_Test_Bench)
--
-- REVISION HISTORY:
--
-- 19-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00550 of GENERIC_STANDARD_TYPES is
begin
process
variable correct : boolean := true ;
constant co_bit_vector_1 : bit_vector
:= c_st_bit_vector_1 ;
constant co_string_1 : string
:= c_st_string_1 ;
constant co_t_rec1_1 : t_rec1
:= c_st_rec1_1 ;
constant co_st_rec1_1 : st_rec1
:= c_st_rec1_1 ;
constant co_t_rec2_1 : t_rec2
:= c_st_rec2_1 ;
constant co_st_rec2_1 : st_rec2
:= c_st_rec2_1 ;
constant co_t_rec3_1 : t_rec3
:= c_st_rec3_1 ;
constant co_st_rec3_1 : st_rec3
:= c_st_rec3_1 ;
constant co_t_arr1_1 : t_arr1
:= c_st_arr1_1 ;
constant co_st_arr1_1 : st_arr1
:= c_st_arr1_1 ;
constant co_t_arr2_1 : t_arr2
:= c_st_arr2_1 ;
constant co_st_arr2_1 : st_arr2
:= c_st_arr2_1 ;
constant co_t_arr3_1 : t_arr3
:= c_st_arr3_1 ;
constant co_st_arr3_1 : st_arr3
:= c_st_arr3_1 ;
begin
correct := correct and co_bit_vector_1 = c_st_bit_vector_1 ;
correct := correct and co_string_1 = c_st_string_1 ;
correct := correct and co_t_rec1_1 = c_t_rec1_1 ;
correct := correct and co_st_rec1_1 = c_st_rec1_1 ;
correct := correct and co_t_rec2_1 = c_t_rec2_1 ;
correct := correct and co_st_rec2_1 = c_st_rec2_1 ;
correct := correct and co_t_rec3_1 = c_t_rec3_1 ;
correct := correct and co_st_rec3_1 = c_st_rec3_1 ;
correct := correct and co_t_arr1_1 = c_t_arr1_1 ;
correct := correct and co_st_arr1_1 = c_st_arr1_1 ;
correct := correct and co_t_arr2_1 = c_t_arr2_1 ;
correct := correct and co_st_arr2_1 = c_st_arr2_1 ;
correct := correct and co_t_arr3_1 = c_t_arr3_1 ;
correct := correct and co_st_arr3_1 = c_st_arr3_1 ;
test_report ( "ARCH00550" ,
"Constant declarations - composite globally static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00550 ;
--
entity ENT00550_Test_Bench is
end ENT00550_Test_Bench ;
--
architecture ARCH00550_Test_Bench of ENT00550_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00550 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00550_Test_Bench ;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 17:33:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_buffer_register_0_0 -prefix
-- system_buffer_register_0_0_ system_buffer_register_0_0_sim_netlist.vhdl
-- Design : system_buffer_register_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0_buffer_register is
port (
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
clk : in STD_LOGIC
);
end system_buffer_register_0_0_buffer_register;
architecture STRUCTURE of system_buffer_register_0_0_buffer_register is
begin
\val_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(0),
Q => val_out(0),
R => '0'
);
\val_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(10),
Q => val_out(10),
R => '0'
);
\val_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(11),
Q => val_out(11),
R => '0'
);
\val_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(12),
Q => val_out(12),
R => '0'
);
\val_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(13),
Q => val_out(13),
R => '0'
);
\val_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(14),
Q => val_out(14),
R => '0'
);
\val_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(15),
Q => val_out(15),
R => '0'
);
\val_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(16),
Q => val_out(16),
R => '0'
);
\val_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(17),
Q => val_out(17),
R => '0'
);
\val_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(18),
Q => val_out(18),
R => '0'
);
\val_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(19),
Q => val_out(19),
R => '0'
);
\val_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(1),
Q => val_out(1),
R => '0'
);
\val_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(20),
Q => val_out(20),
R => '0'
);
\val_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(21),
Q => val_out(21),
R => '0'
);
\val_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(22),
Q => val_out(22),
R => '0'
);
\val_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(23),
Q => val_out(23),
R => '0'
);
\val_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(24),
Q => val_out(24),
R => '0'
);
\val_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(25),
Q => val_out(25),
R => '0'
);
\val_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(26),
Q => val_out(26),
R => '0'
);
\val_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(27),
Q => val_out(27),
R => '0'
);
\val_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(28),
Q => val_out(28),
R => '0'
);
\val_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(29),
Q => val_out(29),
R => '0'
);
\val_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(2),
Q => val_out(2),
R => '0'
);
\val_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(30),
Q => val_out(30),
R => '0'
);
\val_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(31),
Q => val_out(31),
R => '0'
);
\val_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(3),
Q => val_out(3),
R => '0'
);
\val_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(4),
Q => val_out(4),
R => '0'
);
\val_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(5),
Q => val_out(5),
R => '0'
);
\val_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(6),
Q => val_out(6),
R => '0'
);
\val_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(7),
Q => val_out(7),
R => '0'
);
\val_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(8),
Q => val_out(8),
R => '0'
);
\val_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => val_in(9),
Q => val_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_buffer_register_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_buffer_register_0_0 : entity is "system_buffer_register_0_0,buffer_register,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_buffer_register_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_buffer_register_0_0 : entity is "buffer_register,Vivado 2016.4";
end system_buffer_register_0_0;
architecture STRUCTURE of system_buffer_register_0_0 is
begin
U0: entity work.system_buffer_register_0_0_buffer_register
port map (
clk => clk,
val_in(31 downto 0) => val_in(31 downto 0),
val_out(31 downto 0) => val_out(31 downto 0)
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ExtADCSimple_tb is
end ExtADCSimple_tb;
architecture behavior of ExtADCSimple_tb is
component ExtADCSimple
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
SensorPower_o : out std_logic;
SensorStart_o : out std_logic;
SensorReady_i : in std_logic;
AdcStart_o : out std_logic;
AdcDone_i : in std_logic;
AdcValue_i : in std_logic_vector(15 downto 0);
PeriodCounterPreset_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0)
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal SensorPower_o : std_logic;
signal SensorStart_o : std_logic;
signal SensorReady_i : std_logic;
signal AdcStart_o : std_logic;
signal AdcDone_i : std_logic;
constant AdcValueWidth : integer := 16;
signal AdcValue_i : std_logic_vector(AdcValueWidth-1 downto 0);
signal PeriodCounterPreset_i : std_logic_vector(15 downto 0);
signal SensorValue_o : std_logic_vector(15 downto 0);
constant ClkPeriode : time := 100 ns;
begin
DUT: ExtADCSimple
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
SensorPower_o => SensorPower_o,
SensorStart_o => SensorStart_o,
SensorReady_i => SensorReady_i,
AdcStart_o => AdcStart_o,
AdcDone_i => AdcDone_i,
AdcValue_i => AdcValue_i,
PeriodCounterPreset_i => PeriodCounterPreset_i,
SensorValue_o => SensorValue_o
);
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
SensorReady_i <= '0';
AdcDone_i <= '0';
AdcValue_i <= (others => '0');
PeriodCounterPreset_i <= "0000000000001010";
-- Check constant values of dynamic signals coming out of the application modules
wait for 0.1*ClkPeriode;
-- none to check
wait for 2.2*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
report "Enable, first cycle at value 0" severity note;
Enable_i <= '1';
wait for 9*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 35*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 0.1*ClkPeriode;
assert AdcStart_o = '1' report "AdcStart_o should be '1'" severity error;
wait for 0.9*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
wait for 35*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 38
report "2nd cycle, new sensor value: 38" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(38,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(0,16)) report "SensorValue_o should be 0" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 30
report "3rd cycle, new sensor value: 30" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(30,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(38,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(30,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 28
report "4th cycle, new sensor value: 28" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(28,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(30,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(28,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
-- new sensor value: 27
report "5th cycle, new sensor value: 27" severity note;
wait for 2*ClkPeriode;
AdcValue_i <= std_logic_vector(to_unsigned(27,AdcValueWidth));
wait for 6*ClkPeriode;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should be '1'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
wait for 1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should be '1'" severity error;
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should still be '0'" severity error;
SensorReady_i <= '1';
wait for 3*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
AdcDone_i <= '1';
wait for 0.1*ClkPeriode;
assert SensorPower_o = '1' report "SensorPower_o should still be '1'" severity error;
assert SensorStart_o = '1' report "SensorStart_o should still be '1'" severity error;
assert AdcStart_o = '1' report "AdcStart_o should still be '1'" severity error;
assert CpuIntr_o = '1' report "CpuIntr should be '1'" severity error;
assert SensorValue_o = std_logic_vector(to_unsigned(28,16)) report "SensorValue_o should be 38" severity error;
wait for 0.9*ClkPeriode;
assert SensorValue_o = std_logic_vector(to_unsigned(27,16)) report "SensorValue_o should be 30" severity error;
SensorReady_i <= '0';
AdcDone_i <= '0';
wait for 1*ClkPeriode;
assert CpuIntr_o = '0' report "CpuIntr should be back to '0'" severity error;
assert SensorPower_o = '0' report "SensorPower_o should be '0'" severity error;
assert SensorStart_o = '0' report "SensorStart_o should be '0'" severity error;
assert AdcStart_o = '0' report "AdcStart_o should be '0'" severity error;
report "done testing" severity note;
wait for 10*ClkPeriode;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY ANN_ap_fadd_3_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END ANN_ap_fadd_3_full_dsp_32;
ARCHITECTURE ANN_ap_fadd_3_full_dsp_32_arch OF ANN_ap_fadd_3_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ANN_ap_fadd_3_full_dsp_32_arch : ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ANN_ap_fadd_3_full_dsp_32_arch: ARCHITECTURE IS "ANN_ap_fadd_3_full_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END ANN_ap_fadd_3_full_dsp_32_arch;
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